micro controller based system design1

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Micro controller Based System Design

Module 1

VARIOUS LOGIC FAMILIES

The IC digital logic families are classified as

1) Resistor transistor logic (RTL)

2) Diode transistor logic (DTL)

3) Direct coupled transistor logic (DCTL)

4) High threshold logic (HTL)

5) Integrated injection logic (I2L)

6) Transistor transistor logic (TTL)

7) Emitter coupled logic (ECL)

8) Metal oxide semiconductor (MOS)

9) Complementary metal-oxide semiconductor (CMOS)

RTL Basic Gate

The Basic Circuit of the RTL digital logic family is the NOR gate shown in fig 1.1

FIGURE 1.1

Each input is associated with one resistor and one transistor. The collectors of the transistors

are tied together at the output. The voltage levels for the circuit are 0.2V for the low-level and 1

to 3.6V for the high level.

If any input of RTL gate is high, the corresponding transistor is driven into saturation.

This causes the output to be low, regardless of the states of other transistors. If all inputs are

low at 0.2V, all transistors are cut off because VBE < 0.6V this causes the output to be high. The

power dissipation of the RTL gate is about 12mw and the propagation delay averages 25ns.

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DTL Basic Gate

The basic circuit in the DTL digital logic family is the NAND gate shown in fig 1.2.

FIGURE 1.2

Each input is associated with one diode. The diodes and the 5K resistor forms an AND gate. The

transistor serves as a current amplifier while inverting the digital signal.

If any input of the gate is low at 0.2V, the corresponding input diode conducts current

through VCC and the 5K resister into the inputs node. The voltage at point P equal to 0.9V (ie

input voltage 0.2V+ diode drop 0.7V). In order for the transistor to start conducting the voltage

at point P must overcome 1.8V (ie one VBE drop in Q1 plus two diode drops). Since the voltage

at P is 0.9V by the input conducting diode, the transistor is cut off and the output voltage is high

at 5V.

If all inputs of the gate are high, the transistor is driven into the saturation region. With

the transistor saturated, the output drops to VCE of 0.2V which is the low level. The power

dissipation of a DTL gate is about 12mw and the propagation delay averages 30ns.

I2L

It is reasonably good speeds and low power requirement

Base of T1 and emitter of Q1 common

Emitter of T1 and base of Q1 is common

T1 is called a current injection transistor

if the input to 0 then the current of T1 flows through

the input switch to GND. There will be no current to Q1. When the Input switch open the

current injected to Q1.refer fig1.3

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Extremely high density compare to TTL ( 10 times )

LSI functions

Fabrication easier,

Low power

Good speed

HTL

A variant of DTL called high threshold logic circuits incorporated Zener diodes to create

large difference between 0 to 1 levels. Normally it operates on 15 V in Industry application. The

high difference is intended to minimize the noise effect.

Integrated Injection logic (I2L)

The main advantage of I2L is the high packing density of gates that can be achieved in a

given area of semiconductor chip. This allows more circuits to be placed in the chip to form

complex digital functions. This family is mostly used for LSI functions.

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The I2L basic gate is similar in operation to the RTL gate, with few major differences. (1)

The base resistor used in the RTL gate is removed in the I2L gate. (2) The collector resistor used

in the RTL gate is replaced by a PNP transistor that acts as a load for the I2L gate. (3) The I

2L

transistors use multiple collectors instead of the individual transistors employed in RTL.

The schematic diagram of the basic I2L is shown fig1.4

Figure1.4

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It has an NPN transistor Q1, with multiple collectors for the outputs. The basic circuit has a

PNP transistor, TI, connected to supply voltage VBB.

Transistor Transistor Logic (TTL)

The original basic TTL gate was a slight improvement over the DTL gate. There are many

various of the TTL basic gate and they are

1. Standard TTL

2. Low power TTL

3. High speed TTL

4. Schottky TTL

5. Low power schottky TTL

6. Advanced Low power Schottky TTL

Figure 1.5

The standard TTL gate was the first version in the TTL family. This basic gate was then

constructed with different resistor values to produce gates with lower dissipation or higherspeed. In the low-power TTL gate the resistor values are higher than the standard gate to

reduce the power dissipation, but the propagation delay is increased. In the high-speed TTL

gate, resistor values are lowered to reduce the propagation delay, but the power dissipation is

increased. The schottky TTL removes the Storage time of transistors by preventing them from

going into saturation. This version increases the speed of operation without an excessive

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increase in power dissipation. The low-power schottky TTL version sacrifices some speed for

reduced power dissipation.

All TTL versions are available in SSI packages and in more complex forms as MSI and LSI

functions. TTL gates in all versions come in 3 different types of output configurations.

1) Open-collector output

2) Totem-pole output

3) Three state (or tri state) output

Emitter Coupled logic (ECL)

ECL is a non saturated digital logic family since transistors do not saturate, it is possible

to achieve propagation delays of 2ns and even below Ins. This family has the lowest

propagation delay and is used mostly in systems requiring vary high speed operation. Its noise

immunity and power dissipation, however, are the worst of all the logic families available.

The noise margin is about 0.3V and not as good as in the TTL gate. High fan-out is possible in

the ECL gate because of the high input impedance of the differential amplifier and low output

impedance of the emitter-follower. Because of the extreme high speed of the signals, external

wives act like transmission lines.

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Figure 1.6 ( ECL GATE)

Metal Oxide Semiconductor (MOS)

The basic structure of the MOS transistor is shown in fig 1.7

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Figure 1.7

Figure 1.8

Figure 1.9

There are 4 basic types of Mos structures the channel

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can be a p-and n-type, depending on whether the majority carriers are holes or electrons. The

mode of operation can be enhancement or depletion, depending an the state of the channel

region at zero gate voltage. If the channel is initially doped tightly with p-type impurity (diffused

channel), a conducting channel exists at zero gate

voltage and the device is said to operate in the depletion mode. If the region beneath the gate

is left initially uncharged, a channel must be induced by the gate field before current can flow-

thus, the channel current is enhanced by the gate voltage and such a device is said to operate in

the enhancement mode.

One advantage of the MOS device is that it can be used not only as a transistor, but as a

resistor as well. A resistor is obtained from the MOS by permanently biasing the gate terminal

for conduction. The ratio of the source-drain voltage to the channel current determines the

value of the resistance.

Complementary MOS (CMOS)

CMOS circuits take advantage of the fact that both n-channel and p-channel devices can

be fabricated on the same substrate CMOS circuits consist of both types of MOS devices

interconnected to form logic functions. The basic circuit is the inverter, which consists of one p-

channel transistor and one n-channel transistor. THE Figure 1.11 of inverter is shown below

when the input is low, both gates at zero potentials. The input is at -VOD relative to the

source of the p-channel device and at OV relative to the source of n-channel device the result is

that the p-channel device is turned ON and the n-channel device is turned OFF. Therefore the

output voltage is high When input is high, the p-channel device is OFF and n-channel device is

ON therefore output is low.

In either logic state, one MOS transistor is On while the other is OFF. Because one

transistor is always turned OFF, the dc power dissipation of the CMOS circuit is extremely low,

usually on the order of IO nw. The CMOS nor gate Shown below.

PMOS\NMOS\CMOS NOR GATE IS SHOWN Figure1.10

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FIG1.10

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CMOS INVERTOR Figure 1.11

Comparision of major logic families

Logic

parameter

RTL DTL HTL TTL ECL MOS CMOS

Basic gate

Fan out

Power

Dissipated

Per gate,MW

Noise immunity

Propagation

Delay per

Gate, ns

NOR

5

12

nominal

12

NAND

8

8-12

Good

30

NAND

10

55

excellent

90

NAND

20-40

12-22

C10mw

Very

good

12-6

(10 nsw)

OR-NOR

25

40-55

Good

4-1

NAND

20

0.2-10

nominal

300

NOR or

NAND

50

Iuv static

Imwat

100KHZ

Very good

105

ALS-4nscc,1mw,20

1) AS-1.5nscc,8.5mw,50

2) LSTTL 10nscc,2mw,20

3) S-3nscc,19mw,50

REFERENCES

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1) Digital Logic and computer Design

-M Morris Mano

2) Integrated Electronics

-Jacob Millmam and Christos-C. Halkias

3) Digital fundamentals FLOYD

PROGRAMMABLE LOGIC DEVICES [PLDS]

The logic devices in which the logic function is programmed by the user and, in some

cases, can be reprogrammed many times are called as programmable Logic devices.

One advantage of PLDS over fixed function logic devices is that many more logic circuits

can be stuffed into a much smaller area with PLDS. A second advantage is that, with certain

PLDS, Logic designs can be readily changed without rewriting or replacing components. A PLD

design can be implemented faster than one using fixed-function ICS.

TYPES OF PLDS

The 3 major types of programmable logic are

1. SPLD [Simple programmable Logic Device]

2. CPLD [complex PLD] and3. FPGA [Field programmable Gate Array]

1. SPLD :-

They are the least complex form of SPLDS. They are the first type of programmable logic

available. A few categories of SPLD are -----

a. PAL (Programmable array logic)

b. GAL (generic array logic)

c. PLA (Programmable logic Array)

d. PROM (Programmable read only memory)

2. CPLD :-

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CPLDS have a much higher capacity than CPLDS, permitting more complex logic circuits to

be programmed into them. A typical CPLD is the equivalent of 2 to 64 SPLDS. The development

of these devices followed SPLD as basic and advanced in technology permitted higher-density

chips to be implemented. [Typically 44-160 pin packages].

3. FPGA :-

They are different from SPLDS and CPLDS in their internal organization and have the

greatest logic capacity. It consists of an array of any where from 64 to thousands of logic gate

groups that are some times called logic blocks. FPGAS are classified into 2 category as

Course grained [have large logic blocks]

Fine grained [have much smaller logic blocks

Programmable Arrays :-

All PLDS consist of programmable Arrays. A programmable arrays is essentially a grid of

conductors that form rows and columns with a fusible link at each cross point. Arrays can be

either fixed or programmable.

The OR array

It consists of an array of OR gates connected to a programmable matrix with fusible links

at each cross point of a row and column as shown in fig 1.12

PALs and PLAs

Example Continued All possible connections are availablebefore programming

A B C

F0 F1 F2 F3

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Difference between Programmable Array Logic (PAL) andProgrammable Logic Array (PLA):

PAL concept -- implemented by Monolithic Memoriesconstrained topology of the OR Array I.e., the OR

array cannot be fully programmed.

A given column of the OR arrayhas access to only a subset of

the possible product terms

PLA concept generalized topologies in AND and OR planes

PALs and PLAs

Figure 1.12

The array can be programmed by blowing fuses to eliminate selected variable from the

output functions, as illustrated above. For each input to an OR gate, only one fuse is left intact

in order to connect the desired variable to the gate input. Once a fuse is blown it cannot be

connected.

The AND array

It consists of AND gates connected to a programmable matrix with fusible links at each

rows & columns. Another method of programming PLD is the anti fuse, which is opposite of the

fuse. Here instead of burning fusible link a normally open contact is shorted by melting theanti fuse material to form a connection.

Any way the OR array , AND array with fusible links or with anti fuse is one-time

programmable.

SPLDS

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1. PROM

It consists of a set of fixed [non programmable] AND gates connected as a decoder

and a programmable OR array as shown below.

PROM is used primarily as an addressable memory and not as a logic device, because of

limitations imposed by the fixed AND gates

2. Programmable Logic Array (PLA) :-

It consists of a programmable AND array and a programmable OR array. It was

developed to overcome some of the limitations of PROM. It is also called as FPLA [field

programmable logic array] because the user in the field, not the manufactures, programs it.

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Alternative representation for high fan-in structures

Short-hand notationso that all the wires need

not be drawn!

Notation for implementingF0 = A B + A' B'F1 = C D' + C' D

PALs and PLAs

AB

AB

CD

CD

A B C D

AB AB+ CD CD+

Figure 1.15

Programmable Array logic (PAL) :_

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PLA has some disadvantages like longer delays due to the additional fusible links

(because of two programmable arrays) and more circuit complexity. PAL is developed to over

come these disadvantages. It consists of a programmable AND array and a fixed OR array with

of logic. As shown fig 1.16.

Eg:- the simplified diagram of a programmed PAL is shown below.

PALs and PLAs

ABC

A

B

C

A

B

C

ABC

ABC

ABC

ABC

ABC

ABC

ABC

F1 F2 F3 F4 F5 F6

Design Example

F1 = A B C

F2 = A + B + C

F3 = A B C

F4 = A + B + C

F5 = A xor B xor C

F6 = A xnor B xnor C

Multiple functions of A, B, C

A B C

Figure 1.17

A typical PAL has 8 or more i/ps to its AND array and upto 8 o/ps from its o/p logic.ie

nx8. Some PALS provide combined i/o pin that can be programmed an either o/or i/-.

PAL Output combination logic

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There are three basic types of combinational o/p logic with tri state outputs and the

associated OR gate.

1. Combinational output

This o/p is used for an SOP function and is usually available as active low or active high o/p

Figure 1.18, Figure 1.18.A, Figure 1.9

(active low). Active high would be shown without the bubble on the tri state gate symbol.

2.Combinational I/o

This o/p is used when the o/p fn. must feed back to be an i/p to the array or be used to

make the I/o pin an i/p only.

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3.Programmable polarity o/p

This o/p is used to selecting either the o/p fn. Or its complement by programming the X-

OR gate. The fuse on X-OR i/p is blown open for inversion.

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PAL USING FLIP FLOPS

It contains two matrices namely product term generator matrix and sop generator

matrix. With clocked f/fs in feed back path. Since AND matrix contain 1000 to 20,000 swimming

nodes great logical complexity will be there. Feed back loop must be clocked carefully. Clocked

f/f must be connected into all f/f paths from SOP matrix to product matrix. The reset of f/f

initialize the logic can be controlled. Figure is shown above.1.20

GENERIC ARRAY LOGIC [GAL]

It consists of a reprogrammable AND array and a fixed OR array with programmable o/p

Logic Similar to pal array logic .refer the figure no 1.16

The structure of GAL allows any SOP expression with a defined no: of variables to be

implemented. The basic structure of GAL is shown below. Instead of fuse in PAL, we use E2

CMOS cell at each cross point.

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Un programmed GAL

Each row is connected to i/p AND gate each column is connected to an i/p variable or its

complement of programming applied to the AND gates.

Standard GAL Numbering

GAL 16 V 8

16 :- no: of inputs

V :- Variable output configuration

8 :- no: of outputs

GAL 16V8

16input & 8 output high performance E2

MOS generic array logic. The propagation in

delay is 3.5ns max and it can operate max of 250MHZ. The power consumption in less by 50 to75% compare to bipolar and used active pull ups in all pins.

Feature 100% field programmable

-Re configurable Logic

-Re programmable cells

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-High speed electrical erasure

-100 erase/write cycles

-20 years data retention

-50% to 75% less power than Bi polar

-8 OUTPUTS and 16 inputs device

-OLMC configurable as combinational OP/or IP

-OLMC also configurable as registered O/P

-Emulates 20 PIN/PAL devices with full compatibility of fuse, map, function, and parametric

-OUTPUT is programmable

APPLICATION

-High speed graphics processing

-DMA control

-Standard logic, high speed application

-State machine control

-GAL 22VIO

The block schematic is shown in figure 1.23 above

-22 Inputs 10 outputs DEVICE

Feature

-10 outputs Logic Micro cells

-PRE load and power on reset of registers

-High performance E2CMOS Technology

-4ns max propagation delay

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Combination O/P

Combinational I/P-O/P

Programmable polarity

Combinational mode with

1. ADactive low

2. active high

registered mode with

3. active low

4. active high

Output logic Macro cells (OLMC)

OLMC contains programmable logic circuits that can be configured either

(1) for a combinational O/P or I/P

(2) for a registered O/P

OLMC combinational mode configuration are automatically set by programming. Each

OLMC can be programmed for either as active-HIGH or an active low O/P. Also each OLMC can

be programmed as an input.

A basic logic diagram for GAL 22VIO OLMC is

s hown below

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The logic consists of a flip flop and two multiplexer the 1-of-4

MUX connects are of its four input lines to the tri stable O/P buffer based on the states of twoselect inputs, S0 & SI

The inputs to the 1-of-4 MUX are

OR gate O/P

The complement of the OR-gate O/P

The flip flop O/P

The complement of the flip flop output

The 1-of-2 MUX consist either

The O/P of-the-tri state buffer (2) The flip flop back through a buffer to the AND array

based on the state of S1

The four OLMC configuration are

Combinational mode with active-LOW O/P

Combinational mode with active HIGH O/P

Registered mode with active LOW O/P

Registered mode with active-High O/P

Combinational mode

In this mode figure 1.24 have the following condition

So=0 & S1=1 this is combinational mode active LOW O/P

The 1-of-4 MUX selects OR gate O/P. The O/P polarity is active-LOW because of the

inversion of the tri slate O/P buffer.

S1=1, So=1-Combinational mode active HIGH O/P

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The 1-of-4 MUX selects the complement of OR gate. The O/P is active-high because of

the double inversion (complement of the OR & tri state inversion)

The OLMC can be configured as an O/P or an I/P by controlling the tri state O/P buffer

Flip flop are not used. The above is output with active LOW

Next input of this flip flop and 1-of-4 MUX are not used for combinational I\O

1 1 of 2 MUX S1= 1 Input from the buffer.

2 1 of 2 MUX S1= 0 input from Q* of FF.

Registered Mode

Registered mode with active HIGH O/P

Registered mode with active LOW O/P

In this mode the figure 1.24 will have the following conditions

S=0 S1=0 selects the FF Q output to 1-of-4 MUX and output will be low.

In MUX 1 of 2

S1=0 selects the input of FF output Q*.

The above diagram is OLMC in the active-LOW registered mode of the effective logic diagram.

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For condition S1=0 S0=1 selects the Q* output to 1of 4 MUX and output will be high.

In MUX 1of 2

S1=0 selects the input of FF output Q*.

The diagram is OLMC in the active HIGH registered mode

& the effective logic

diagram .

Complex programmable logic devices (CPLD)

CPLD is a logic device that consist of multiple SPLDS inter connected on a single chip-

CPLD can be used to implement large logic functions including shift registers

A CPLD basically consists of multiple groups of PAL/GAL like arrays with programmable

interconnections each PAL/GAL group is called a logic array block (LAB), function block. Each

LAB contains several PAL/GAL like array called macro cell. Each LAB can be interconnected with

other LAB or to other I/o using programmable interconnect array to form large complex logic

functions. Any SOPS function can be implemented.

Micro cells

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Each LAB in a CPLD contains several macro cells CPLD architecture varies from

manufactures to manufacture. But generally there are 32 to several hundred macro cells in one

LAB. A typical macro cell has an AND array, a product term select matrix, an OR gate and a

programmable registers. The logic is similar to OLMC logic in PAL/GAL

Basic CPLD Macro cell

Refer basic micro cell diagram 1.31 and logic array block in figure 1.30.

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Each macro cells has a fixed no: of AND gate that feed into a product term selection

matrix, where product terms can be selected and applied to an OR gate. Additionally, product

term expands inputs from other macro cells allow more product terms to be selected in

addition to those from the macro cell AND array. Also, a product term expands O/P provides

any selected product term to other macro cells in the LAB or in other LABS through the PIA.

The OR gate provides an SOP O/P through programmable select blocks to the I/O or to a

flip flop. In this implementation there are three programmable selects, they are essentially data

selectors (multiplexers)

One programmable select block provides either a global clock or a product term CLK to

be used as the clock input for the flip flop. A second programmable select block provides

either a global clear or a product term clear to the flip flop. A third programmable select block

routes either the O/P of the OR gate or the O/P of the flip flop to the I/O. The OR gate provides

an combinational O/P and the flip flop provides a registered O/P.

In CPLDS, the term registered is used in reference to the flip flop its associated circuits.

The flip flops in a CPLD can be used for implementing shift registers or counters logic.

Programmable Interconnect Array (PIA)

PIA consists of conductors that run through out the CPLD chip and to which connections

from the macro cells in each LAB can be made. By using PIA, any macro cells can be connected

to other macro cells within the same LAB, or macro cells in other LABS

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Field programmable Gate Array (FPGA)

CPLD consist of multiple PAL/GAL type logic blocks that are linked by programmable

interconnection CPLDS are based on SOP logic

FPGAS are distinctly different from CPLD in terms of architecture and it offer higher logic

capacity.

It consist of an array of logic blocks, surrounded by programmable I/O blocks and connected

with programmable interconnect.

The interconnection between elements are user programmable.

FPGA consist of a two-dimensional array of logic block that can be connected by general

interconnection resources. The interconnect comprises segments of wire, where

The segment may be of various Length. Present in the interconnect are programmable

switches that serves to connect the logic blocks to the wire segments, or one wire segment to

another. See figure 1.33

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Logic Blocks

The structure and content of a logic blocks is called its architecture each logic block in a

generic FPGA contains several logic elements. Logic block architecture can be designed in many

different ways varies from manufacturer to another. Generally there can be over 10 thousands

logic elements in a single chip refer figure1.34

Logic element contains an LUT,(look up table) associated logic and a flip flop Figure 1.35

In the above mentioned logic element contains 4 I/P LUT, it can programmed as a logic

function generator. It can be used to produces SOP functions or logic functions such as adder

and comparators

When configured as an adder, the carry in and carry out allow for adder expansion.

Using cascading logic, an LUT can be expanded by cascade with LUT in other logic elements. The

programmable selects choose either combinational function from the LUT O/P or registered

function from the flip flop O/P

The LUT

The LUT is a memory device that can be programmed to perform logic function LUTreplaces the AND/OR array logic in a CPLD.

Consider this logic function Y=ABC+ABC+ABC. When any one of the three product terms

appears on the LUT I/PS, the corresponding memory cell storing a 1 is selected and the 1

(HIGH) appears on the output. For any product term that are not part of the SOP function, the

LUT O/P is O (LOW)

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FIFO (First-In-First-Out)

This type of memory is formed by an arrangement of shift registers. The term FIFO, first

in first out data bit written into the memory is the first to be read out. In a conventionalregister, a data bit moves through the register only as new data is entered FIFO register, a data

bit immediately goes through the register to the eight most bit location that is empty

Conventional shift register FIFO

I\P X X X X O\P I\P - - - -

0 0 X X X 0 - - - 0

1 1 0 X X 1 - - 1 0

1 1 1 0 X 1 - 1 1 0

0 0 1 1 0 0 0 1 1 0

Output of FIFO 1.37

BLOCK DIAGRAM FIFO SERIAL MEMORY

This particular memory has 4 serial 64 bit data register and a 64-bit control register

(marker register). When data are entered by a shift in pulse, they move automatically sender

control of the marker register to the empty location closest to the O/P. Data advance into

occupied position. However when a data bit is shifted out by a shift out pulse, the data bits

remaining in the register

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automatically move to the next position toward the O/P. In FIFO,

data are shifted out independent of data entry, with the use of two separate clocks.Serial

memory block diagram is shown figure 1.38.

FIFO Application

One important application area for the FIFO register is the case in which systems of

differing data rates must communicate. Data can be entered into a FIFO register at one rate and

taken out at another rate.

Irregular rate data to constant rate data

lower rate data to higher data rate

Constant rate data to lo burst data

Burst data to constant rate data

Dual Port RAM

Dual port RAM are effective devices for high-speed communication between microprocessors.

Typical dual port RAM are specialty SRAMS of small size (IK to 4K bytes} and medium speed (25-

50ns). Because of their relatively low density, it usually impractical in terms of chip count and

cost to make large dual port RAM systems from these chips

A dual port RAM is a single RAM, typically an SRAM, which can be accessed

Simultaneously from two different ports, one port per microprocessor. Each microprocessor

sees a simple SRAM interface, and the contents of the SRAM are common to both

microprocessor. A block diagram of a dual port RAM in a dual microprocessor system is shownbelow. In this case, a conventional CPU communicates with a DSP CPU through the common

memory of the dual port RAM FIGURE 1.39 shown above.

A true port RAM has one set of SRAM cells and two independent

sets of addressing logic, called ports. The RAM cells may be read on written by either side

independently and simultaneously. This capability is valuable because each port may access the

RAM cells without regard to activities on the other port. There is one exception to this

simultaneous access. If one port is writing to a cell while the other port is reading the same cell,

the data may be changing during the read which could cause errors. Most dual port RAMS

provide address contention logic to prevent this unlikely condition by causing one side to wait if

both are trying to access the same cell

True dual port RAM, have some limitations. The dual port RAM cell is approximately

twice as large as its single port SRAM counter port. This makes true dual port RAMS more

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expensive than SRAMS, especially at higher densities. However three is more than one way to

achieve the dual port RAM function

They are

Time shared Dual port SRAMTime shared dual port SRAM using quick switches

Ping-pong dual SRAM

Features of DS 1609 Dual port RAM

-Totally asynchronous 256-byte dual port memory

-Multiplexed address and data bus keeps pin count low

-Deal port memory cell allows random access with minimum arbitration

-Each port has standard independent RAM control signals

-Fast access time-Low power CMOS design

-24 pin DIP or 24 pin SOIC surface mount package

-Both CMOS & TTL compatible

Description

The DS1609 is a random access 256-byte dual port memory designed to connect two

asynchronous address/data buses together with a common memory element. Both ports have

unrestricted access to all 256 bytes of memory and with modest system discipline no

arbitration is required Each port is controlled by three control signals : O/P enable, writeenable, port enable

The obvious advantage of the multiplexed bus is the slightly reduced system

performance because address and data information is being transmitted serially. The equally

obvious advantage is the reduced pin count achievable by multiplexing the addressing and data

buses.The pin diagram is shown Fig 1.40 above.

OPERATION READ CYCLE

A read cycle to either port begins by placing an address on the multiplexed bus pinsADO-AD7. The port enable control (CE) is then transitioned low. This control signal causes

address to be latched internally. Addresses can be removed from the bus provided address hold

time is met. Next, the output enable control (OE) is transitioned low, which begins the data

access portion of the read cycle. With both CE and OE active low, data will appears valid after

the output enable access time. Data will remain valid as long as both port enable and output

enable occurring rising remains low. A read cycle is determinate with first (edge of either CE or

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DE. The address/data bus will return to a high impedance state after time TCEZ or toez as

referred to the first occurring rising edge. We must remaining high during read cycle toez)edge

of either CE or OE.

OPERATION WRITE CYCLE

A write cycle to either port begins by placing an address on the multiplexed bus pins

AD0-AD7. The port enable control (CE) is then transitioned low. This control signal causes

address to be latched internally. As with a read cycle, the address can be removed from the bus

provided address hold time is met. Next the write enable control signed (WE) is transitioned

low which begins the write data portion of the write cycle. With CE and WE active low the data

to be written to the selected memory location is placed on the multiplexed bus. The data setup

(tps) and data hold time (tdh) times are met, data is written into the memory and the write

cycle is terminated on the first occurring rising edge of either CE or WE. Data can be removed

from the bus as soon as the write cycle is terminated. OE must remain high during write cycles.

ARBITRATION

THE DS1609 DUAL PORT ram has a special cell design that allows for simultaneous

accesses from two ports. Because of this cell design, no arbitration is required for read cycles

accessing at the same instant. However, an argument for arbitration can be made for reading

and writing the cell at the exact same instant for writing from both ports at the same instant. A

simple way to assure that read / write conflicts dont occur is to perform redundant read cycles.

Write/write arbitration needs can be avoided by assigning groups of addresses for write

operation to one port only. Groups of data can be assigned check sum bytes which wouldguarantee correct transmission. A software arbitration system using a mail box to pass status

information can also be employed each port could be assigned a unique byte for writing status

information which the other port would read. The status information could tell the reading port

if any actively is in progress and indicate when activity is going to occur.

Interfacing of DS1609 with microprocessor

For implementation with the Intel 8086/8088 microprocessor family, the address/data pins of

either port may be tied directly to the lower 8 address data lines of the Intel 8086 or 8088. The

active-low RD pin from the microprocessor provides the active-low OE input to the port on theDS1609, while active-low WR provides the active-low WE input to the port. The ports active

low CE input may be conditioned by a system decoder, which would require the 8086 ALE

output as an input to provide address latching. Several of the un used address/data lines from

the 8086 would also be required as input to indicate the DS1609 resides in the system memory

map. In application where multiple DS 1609 ports are required, multiple active-low CE

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outputs could be provided from a system decoder using the ALE signal from an Intel 8086/8088

with user specified address lines to generate multiple chip selects.

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Micro controller Based system Design

Embedded C Compiler Module

2

Compiler translates program written in high level language into assembly language.

Advantages

Easy source code portability

Multiplatform programming

Easier is to modify and update

Reduction of the development time and the development costs

The source codes are more readable

Lucidity of the Source codes of the program and global implication of the developing

process

Optimization and validation tools

Disadvantage

Higher price of the high quality development tool

Higher data and code memory requirements

More difficult to learn.

Header file # include < reg 51.h>

Data types

CX51 provides a number of basic data types. It offers standard C data types and also supports8051 platform.

Data types Bytes Value range

Bit

Signed character

Unsigned character

Signed integer

1 bytes

1 bytes

1 bytes

2 bytes

0 to 1

-128 to 127

0 to 255

-32768 to +32767

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Unsigned integer

S bit

S fr

2 bytes

1 bytes

8 bit

0 to 65535

0 to 1

0 to 255

Loop( generating delay)

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Limitations is due to addressing scheme used (indirect), @ R,

Not efficient as small but faster than large modes

Large model

All variables reside in external data memory (up to) 64 bytes)DPTR is used for addressing

Memory access through DPTR is inefficient

Data access generates more code than the small compact models.

memory model

Memory Models C 166 users guide memory models

Tiny

Small

Medium

Compact

Large

Huge

Memory model determines the default memory selection for variables. Unless special reasons

exist, we should always use the small memory model. The programs will run faster and code

generated will be smaller.

1. Tiny Memory Model

Used for program those are limited to 2 K bytes in size

Do not use external data memory all

Compiler generates ACALL & AJMP instruction instead of LCALL & L J M P.

No references to external data memory are allowed.

So the complier well never generate the MOVX instruction

Tiny & SMALL memory models are identical

Variables are stored in near memory

Functions are stored in near memory and are accessed

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Using near calls

-generates 16 bit line as addresses by limiting codes

-Generate data space to 64 K

-This memory model is the best choice for program that have small code & small data

requirements. It do not require access to additional address space.

2. Small Memory Model (Total RAM 128 bytes)

- All variables and parameter passing segments will be placed in the 8051 internal memory.

-Used for target systems do not have external data memory or where the data requirements of

the program allow small memory model to be used.

-Local variables & function arguments are located in internal data memory

-By default global & static variables are located in internal data memory unless they are

constant objects.

-By using-x data keyword, we can make global & static variables (located) in external data

memory

-Single chip 8051 users may only use the SMALL models, unless they have an external ram

-Variables are stored in near memory

-Functions are stored in near memory and are accessed using near cells

-This memory model is the best choice for programs that have small code & small data

requirements

3. MEDIUM MEMORY MODEL

-For application using larger amounts of RAM, this model will allow the use of external data

memory.

-Code efficiency is not quite as good as the small model, due to the over heads of addressingXDATA memory

-compiled stack is still used like small model

Static & global are in XDATA memory

-Variables are stored in near memory

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-Functions are stored in for memory and are accessed using far calls.

-This memory model is the best choice for programs that have large code & small data

requirements.

4. COMPACT MODEL

(Total RAM 256 bytes off-chip, 128 or 256 bytes on-chip)

All variables by default reside in one page of external data memory.

-This memory model can accommodate a maximum of 256 bytes of variables.

-The limitation is due to the addressing scheme used, which is indirect through registers R0 &

R1 (@R0,@R1)

-It is not as efficient as the small model therefore variable access is not as fast.

-However the compact model is faster than large model

-Variables are stored in far memory

-Functions are stored in near memory and accessed using near calls.

-This model is the best choice for programs that have small code & large data requirements

5. LARGE MODEL

-All variables, by default, reside in external data memory (up to 64 K bytes)

-Variables..are placed in external memory addressed by @ DPTR

-Local variables and function arguments are located in x data memory

-By default, global & static variables are located x data memory unless they are const. object

(which are located in program memory)

-If the target s/m has no x data memory, the large memory cannot be used

-This permits slow access to a very large memory space & easiest model to use.

-Not often used for an entire program.

Code Optimization

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Optimization techniques are used to produce smallest, fastest code possible. They are

independent of the target processor and the code generation strategy. Some of the

optimizations performed include.

Constant folding :

Constant expressions (including floating point) are evaluated at compile time. Expressions only

involving constants are replaced by their result.

Strength reduction:

Multiplication is reduced by shifting and adding where possible.

Expression reordering

Expressions are reordered and associative operators grouped to minimize complexity i.e.

expressions are rearranged to allow more constant folding.

-Expression simplification : Multiplication by 0 or 1 and addition or subtractions of 0 are

removed. Such useless expressions may be introduced by macros in C or by the compiler itself.

-Logical expression optimization : expressions involving , 11 and 1 are interpreted

and translated into a series of conditional jumps.

* Common code elimination / merging

Where separate pieces of code produce common sequences they are merged.

-Constant copy propagation: - A references to a variable with known contents is replaced by

those contents.

-Common sub expression elimination: - The compiler has the ability to detect repeated uses of

the same (Sub-) expression such a common expression may be temporarily saved to avoid re-

computation. This method is called common sub expression elimination (CSE)

* Global Register Allocation

Registers ae allocated to variables and temporaries based on function-wide analysis ofvariable usage.

-Register parameters :- Function parameters are passed in registers where possible

* Jump / Branch Optimization

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-Loop rotation: - With for and while loops, the expressions is evaluated once at the

top and then at the bottom of the loop. This optimization does not save code, but speeds up

execution.

-Switch optimization: - A number of optimizations of a switch statement are performed, such

as the deletion of redundant cause labels or even the deletion of the switch.

-Control flow optimization: - By reversing jump conditions and moving code, the number of

jump instructions is minimized. This reduces both the code size and the execution time.

-Remove useless jumps: - An unconditional jump to a label directly following the jump is

removed. A conditional jump to such a label is replaced by an evaluation of the jump condition.

The evaluation is necessary because it may have side effects.

-Conditional jump reversal :- A conditional jump over an unconditional jump is transformed into

one conditional jump with jump condition reversed. This reduces both the code size andexecution time.

-Loop optimization: - In variant expression may be moved out of a loop and expressions

involving an index variable may be reduced in strength.

-Loop un rolling Eliminate short loops by replacing them with a number of copies

* Dead code elimination

Unreachable code can be removed from the intermediate code without affecting the

program. However, the compiler generates a warning message, because the unreachable code

may be result of a coding error.

Sharing of string literals and floating point constants

String literals and floating point constants are put in ROM memory. The compiler overlays

identical strings and let them above the same space, thus saving ROM space. Like wise identical

floating point constants are overlays and allocated only once.

Frequency reduction

Execution time of a program can be reduced by moving code from a part of a program which is

executed very frequently to another part of the program which is executed fewer times.

89C2051 Microcontroller

89C2051 and 89C51 are CMOS 8 bit microcontroller both have flash programmable and

erasable read only memory (PEROM) [Flash memory is a non-Volatile memory, which can be

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electrically erased for lines and blocks. The mechanism for erasing the memory is easier and

faster than that needed for E2

PROM, ie there is no waiting time for erasing the program

memory] Both devices have the same instruction set as that of 8051. Both support fully static

operation. Operating frequency could be from OHZ to 24MHZ. 89C51 is a 40-pin device and

89C2051 is a 20-pin device 89C2051 has two timers and 2K flash PEROM.

89C2051 Architectures over view

The architecture is similar to 89C51 except port 0 port 2. Analog comparator is not available for

89C51.No Port three alternate function like RD,WR,ALE,EA etc. The architecture is shown below

both 89C51 and 89C951. The memory organization of both 89C51 and 89C2051 also given in fig

2, fig2.1

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ARCHITECHURE OF 89C51

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89C51 PIN DIAGRAM

Features of 89C51

89C51 has 4K on chip flash program memory

It has 2 16bit timer /counter

It has one full duplex, serial port.

It has 128 bytes of on-chip RAM

It has 32 I/O lines

It has on chip oscillator and CLK circuitry

It has 6 interrupt sources

89C2051 has a precision analog comparator P3.6 is not available externally, however, it

can be read in software. P3.6 is the output of the precision analog comparator. It has 15 I/O

lines. Only P1 &P3 are available

Program written for 89C51 may not always work an 89C2051 because of the absence of

ports P0 & P2 in 89C2051

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Any program related to 89C2051 precision comparator will not work on 89C51

Register structure, memory organization is almost same that of 89C51

The architecture does not support any external address/data bus and therefore RD, WR

signals are absent in 89C2051

Similarly ALE, PSEN, EA signals are not there in 89C2051

89C2051 supports the full duplex serial communication and 6 interrupt sources

It has idle mode and power-down mode

Pin diagram of 89C2051

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Precision analog comparator

89C2051 has a precision analog comparator. Pin P12 and pin P13 are the corresponding

inputs. P3.6 is the output of this comparator accessible though software A. Precision analog

comparator may be used for application where a comparison between the desired value and

actual value is required.

Power Saving Options

The power requirement of a microprocessor board is a very important aspect. There are

power saving methods based on oscillator frequency, power down & idle modes.

Fully static operation

0 to 24MHZ frequency

Important factor in selecting the oscillator frequencies are the power dissipation and

speed of operation required.

Idle mode

- CPU to sleep

- On chip peripherals operational

- Internal clock signal to CPU is gated off

- Clock to time r, interrupt and serial port function continues

Contents of on-chip RAM and all SFRs and complete CPU status including the PSW, stack

pointer, accumulator are preserved

To enter into ups idle mode, IDLE bit in PCON is to set by software

Come out from idle mode by software

- By have were reset

- Activation of an enabled interrupt

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Power down mode

Oscillator is frozen

No clock is generated

On chip RAM-SFRS maintain their values

Hardware reset is the only way to come out of power down mode

Reset action will modify SFRs but the one chip RAM will be pressured

Memory Organization of 89C 51

89C51 has internal RAM and ROM memory for variable data and program codes

respectively. 4K Rom (or E2

PROM) is used for program codes and 128 byte internal RAM is used

for data .figure is shown above fig 2.1

The 128 byte RAM is organized into 3 distinct areas as-

1. 32 bytes from address 00-IF that make up 32 working register, organized on 4 register

banks of 8 register each. Bank is selected by the RS and RS o pins of PSW. Eight registers

is named as R0-R7 in each bank. Register bank 0 is selected on reset.

2. A bit addressable area of 16 byte occupies RAM byte address 20h to 2Fh. There are a

total of 128 bits in this area, which corresponds to the 128 byte of RAM. e.g. byte

address 4FH is equivalent bit 7 of byte address 29.

3. A general purpose RAM area above the bit area, from 30H to 7FH, addressable as bytes.

128 byte internal RAM +128 bytes of SFRS is collectively known as the data memory.

The 4K ROM is used for program codes. It is arranged as registers (8bit) of address from

0000 to OFFF. The additional memory can be added externally using suitable circuits. Theprogram addresses higher than OFFF will cause the 89C51 to automatically fetch code bytes

from external memory. This internal and external ROM collectively known as program memory.

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LED and Switch Interfacing

Refer figure 2.2 above shows how LED and switch is connected with 89C51

When switch is pressed, LED should blink

Algorithm

1. Start

2. P1.5 as I/p pin

3. Put p1.7 (LED) is in OFF state (by setting the pin)

4. Check whether switch is pressed, i.e. p1.5 is ground or not

5. P1.5 is connected to ground, LED should be on by clearing the pin

6. Continue

7. END

Assembly Code

ORG 0000H

SETB P1.5

WAIT: SETB P1.7 (LED OFF)

JB P1.5, WAIT

GLOW CLR P1.7

JNB P1.5 GLOW

SJMP WAIT

END

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Interfacing Seven-Segment Display

Seven segment displays commonly contain LED segments arranged as an 8, with one

common lead (anode or cathode) and seven individual leads for each segment.

2 types of seven segment display

Common Cathode

Common Anode

Figure 2.3 figure 2.4

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Seven segment display

In order to display 1, the corresponding segments (b,c ) should be enabled

In common cathode, each segment well be lit only if the segment line brought high and

common cathode is brought low.

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In common anode, each segment will be lit only if the segment line brought low and

common anode is brought high.

Common cathode to display 1

DP g f e d c b a

0 0 0 0 0 1 1 0 06H

Common Anode to display 1

DP g f c d c b a

1 1 1 1 1 0 0 1 F 9H

Before writing the program, we have to create a LUT containing the seven segment

pattern to display the corresponding hex digit

We can now interface a single 7-segment to microcontroller but for interfacing multiple

7 segment are use scanning principle where one 7 segment is displayed after another, but this

process is very fast hence the flickering cannot be seen by human eye

Interfacing of Multiple 7-segment display

For displaying 2 digit no using single module 7-seg.

For displaying a 2 digit no loaded from a single port on two single module displays using

multi-flexing. We use scanning principle for interfacing multiple 7 segment display, but this

process is very fast hence the flickering cannot be seen by human eye.

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Figure 2.5

Refer the interface diagram is shown in fig 2.5 in the first module.

Assembly language

ORG 500H

DB 40H, 79H, 24H, 30H, 19H, 12H, 02H, 78H, 00H, 10H, 08H, 03H, 46H, 21H, 06H, OCH

ORG 0000H

MOV P1, #OFFH

MOV DPTR, #500H

CLR P3.0

CLR P3.1

MOV A, P1

MOV R3, A

ANL A, # OFH

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MOVC A, @ A+DPTR

SETB P3.0

MOV P2, A

ACALL DELAY

MOV A,R3

ANL A, # OFOH

SWAPA

MOV C, A @A+DPTR

MOV A,R3

SWAP A

MOVC A, @A+DPTR

CLRP3-0

SETB P3-1

A CALL DELAY

SJMP TOP

DELAY : MOV R4, # 01FH

LOOP 2 : MOV R5, # 01FH

LOOP 1: DJNZ R5, LOOP1

DTNZ R4 LOOP2

RET

7 segment displays interface

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This seven segment display interface connected to the 89C2051 micro controller using

port P1,and port P3. The control is made by software control of the two ports programs. No

separate driver or decoder is required for this configuration. It is a common cathode

configuration. By enabling the output P1.0 to P1.6 to high level positive voltage will be applied

to a b c d e f g anode of the seven segment display. Port P3.0 to P3.3 will drive the cathodetransistor. If output P3.0 to P3.3 is enabled by high voltage the transistor BC 547 is switched on

which in turn supplies GND potential to the cathode. The current through the LED can be

limited by a resister R220. If you want to reduce the current the value of the register can be

increased.

The seven segment codes and cathode of seven segment code is to be stored in the

registers and outputted periodically. The period of updating the LED should be such that our

eye should not able to distinguish the period. The frequency of up dating should be more than

20HZ i.e. our persistence of an eye. Take 100HZ is the updating time i.e. 10 m second; we have

to refresh 4 no 7 segment display. one seven segment display is refreshed every 2.5 m sec.

This can be achieved by enabling a interrupt for every 2.5 m sec and service it so that the seven

segment display is up dated by software. Every interrupt the timer THI and TLI should be

updated and seen segment display code is to be inputted through port 1 & port 3. Display 1to 4

pointer is to be updated for every interrupt.

Now by the control of software the seven segment interface can be achieved. It is not

required any BCD driver or transistor driver chip. The designer should decide, the configuration

by considering.

-cost

-space

-time

-system capacity

Assembly Language

ORG 000H

SJMP Start

ORG 001 BH

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SJMP INT-T1

START MOV SP # 54H Initialize stack pointer

MOV RO # 40H Pointer of Internal RAM

MOV TMOD # IOH Timer is mode 1

MOV TLI # COUNT L Timer for refresh 3msc

MOV THI # COUNTH T1

SETB ETI

SETB EA Enable timer global interrupt

SETB TRI Start timer 1

SJMP $ Wait for interrupt

INT. Ti = MOV TLI # COUNTL

MOV THI # COUNTH

MOV PI @ RO Least significant digit

INRO Increment next memory

MOV P3 @ RO Load cathode out put

INRO Increment

CJNE R, # 48h Next check for 48

MOV RO # 40H If so R0=40 H

NEXT Dia R E T I

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LCD INTERFACE

LCD liquid crystal display is a better use for any text messages. It consumes very less

power compare to LED display. For better use of interaction LCD more suitable display. Now

LCD controller same available which can be directly connected to all micro controllers. Even

serial interface also available in LCD controllers.

LCD displays are available 16x2 characters or 20x2 characters. Totally 2 lines with either

16 or 20 characters. All LCD controllers have data lines and controller lines to interface with

micro controllers.

LCD pin descriptions HD 4480

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During power on reset please ensure LCD is ready for receiving command or data.

Normally wait for 15 m sec and provide necessary data to it.

LCD HD44780 is connected to 89C51, port 1 and port 3. The data lines are connected to port 1

for programming command and input text data to the LCD Port 3 outputs the control signals RS,

RW, EN lines Data D7 bit is polled for the LCD busy. Status for writing command or text. refer

diagram 2.10 above

Programming of LCD Text in the Display by 89C51

EN EQU P3.2

RS EQU P3.1

RW EQU P3.3

BUSY EQU P1.7

MOVA #38h 8 bit data is 2 lines display

CALL LCD COMD (5x7 character (DL,N,F)

MOVA # OEH Turn on LCD and cursor (D, C)

CALL LCD COMD (Move cursor position right automatically)

CALL LCD COMD

MOVA # O1H clear display cursor at home

CALL LCD-COMD

MOVA # L

CALL LCD TEXT

MOVA # C

CALL LCD TEXT

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MOVA # D

CALL LCD TEXT

LOOP SJMP LOOP in definite loop

LCD COMD

CLR C Turn off cursor

CALL Write

Ret

LCD Text SETB C turn on cursor

CALL write

RET

WRITE Set b Busy p1.7 busy line as an input

Set b RW read from LCD

CLR RS Select command register RS=0 command

WAIT set b EN 1 to 0 an EN line

CLR EN

Tb Busy WAIT Test bit Db7=1 IS/LCD BUSY if busy wait

MOV RS, C Test or command information in C, flag put in RS

MOV P1, A Test or command 8 bit to LCD

Clr RW write operation

Set b EN

Clr EN- 1 to 0 for execute the command

END

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LCD INTERFACING

LCD discussed in this section has 14 pins. The functions of each pin is given below.

1. VSS - Ground

2. VCC - +5V power supply

3. VEE - power supply to control contrast

4. RS - Register select

0- Select command register

1- Select data register

5. R/W - 0-for write

1-for read

6. E - Enable pin

(7-14)DBO-DB7-8 bit data buses

VCC and VSS provide _5V supply and VEE is used for LCD contrast.

There are two important registers inside the LCD RS pin is used for their selection. If

RS=0, the instructions command code register is selected, allowing user to send a command

such as clear display, curser at home etc. If RS=1, data register is selected in order to send data

to be displayed.

The enable pin is used to latch the information presentation to its data pins. A H to L

pulse must be applied to this pin for latching.

LCD command codes

01 - clear display screen

02 - Return home

06 - increment cursor

OE - display on, cursor blinking

80 - Force cursor to the beginning of 1st

line

38 - 2 lines and 5X7 matrix. Etc.

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Programming steps

1. Select 2 lines 5x7 matrix

2. Display on, cursor on

3. Clear LCD

4. Shift cursor right

5. Move cursor to beginning of 1st

line

6. send data to be displayed

PROGRAM TO DISPLAY NO in LCD (USING PORT2 0)

MOV A, #38 A CALL DATA

A CALL COMMAND A CALL DELAY

A CALL DELAY HERE : SJMP HERE

MOV A, # OE COMMAND : MOV P1,A

A CALL COMAND CLR P2.0

A CALL DELAY CLR P2.1

MOV A, #01 SETB P2.2

A CALL COMMAND CLR P2.2

A CALL DELAY RET

MOV A, #06 DATA MOV PI,A

A CALL COMMAND SETB P2.0

A CALL DELAY CLR P2.1

MOV A, # 81 SETB P2.2

A CALL COMMAND CLR P2.2

A CALL DELAY RET

MOV A, # N DELAY MOV R3, #50

A CALL DATA H2 MOV R4 #FF

A CALL DELAY H1 DJNZ R4, H1

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MOV A, # 0 DJNZ R3 H2

RET

END

Electromechanical Relays

A relay is an electrically controllable switch widely used in industrial controls,

automobiles and appliances. It allows the isolation of two separate sections of a system with

two different voltage sources. For e.g. +5V system can be isolated from a 120V system by

placing a relay between them. One such relay is called an electromechanical relay. The

electromechanical relays have three components - coil, spring and contacts. When current

flows through the coil, a magnetic field is created around the coil (coil is energized) which

causes the armature lobe attracted to the coil. The armature contacts acts like a switch and

closes or opens the circuit. When coil is not energized, a spring pulls the armature to its normalstate of open or closed.

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Driving a relay

Digital systems and microcontroller pins lack sufficient current to drive the relay. While

the relays coil needs around 10 mA to be energized, microcontroller pin can provide a

maximum of 1-2m A current. For this reason we place a driver such as the ULN 2803 or a power

transistor between the microcontroller and the relay.

In choosing a relay, the following characteristic need to be considered.

1) The contacts can be normally open (No) or normally closed (NC). In the NC type, the

contacts are closed when the coil is not energized. In No, the contacts are open when

the coil is energized.

2) The current and voltage needed to energize the coil. The voltage can very from a few

volt to 50V, while the current can be from a few mA to 20mA depends upon relay type.

The relay has minimum voltage, below which the coil will not be energized. This

minimum voltage is called the pull-in voltage.

In the datasheet for relay, we see coil resistance V/R gives pull in current. For example if

coil voltage is 5V & coil resistance is 500 ohms, we need a minimum of 10 mA (5/500 )

pull in current.

Interfacing diagram shown in fig 2.12

Port pin can per of 20mA current to drive the relay. So base

resistance around 1 K result into this much basic current.

Now, base as the current through an inductor cannot be suddenly reduced to zeros, a

free wheeling diode is employed. A free wheeling diode across the relay coil is required because

when the transistor is switched off, the energy stored already in the inducator can be dissipate

through the diode and internal resistance of the inductor . The operation of this circuit is very

simple. If the port pin is made high, the basic current flows and the transistor is switched on.

This will cause collector current that also flows through the relay coil. Thus, the contact will be

closed.

Putting O on port pin makes the transistor off the inductor current now flows through

the free wheeling diode and slowly decays to zero as power is dissipated in the internal

resistance of the coil and internal diode.

PGM for light the lamp for 1 see and off it for isec

ORG 0000H

MAIN SETB p1.0

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MOV R5,#55

ACALL DELAY

CLR P1.0

MOV R5,#55

ACALL DELAY

SJMP MAIN

DELAY:

H1: MOV R4,#100

H2: MOV R3,#253

H3: DJNZ R3,H3

DJNZ R4,H2

DJNZ R5H1

RET

TRAFFIC LIGHT CONTROL

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Consider a 4 way junction as shown fig 2.13. There are two lights in each direction. One Red

and One green. Green for permitting vehicles on that way and Red for stopping.

We can control these traffic lights by the use of a Microcontroller.

If we are using bulbs, we cannot connect it directly to MC, because it cannot drive the bulb.Then we connect it through relays as shown above diagram fig2.14.

Here when the port pin activates relay operates and thus the bulb glows.

When the port pin make Zero LED will glows : when it is one LED will OFF. We prefer this

method.

The condition for traffic control is; permit vehicles only in one direction. I.e. only one green

light. Will glow at a time and, in all other direction, red will glow. For this we connect these

lights (Say LEDS) to a port as shown :

If we want to glow GA (green in North direction) make P1-0 low. At that time all other green

will be off by making corresponding pins high. All reds except RA will glow.

I.e. for passage of vehicles in north direction, we have to store ;

To port 1. It will make green in north direction and Red in all other direction

After a delay make the next green to glow and red in all other direction and so on,

Bit Sequence Hex Code

0110 1010 6A passage in N direction

1001 1010 9A passage in W Direction

1010 0110 A6 passage in S direction

1010 1001 A9 passage in E direction

PROGRAM

BACK : MOV A, # 6A

MOV P1, A # make flow in North direction

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ACALL DELAY

MOV A, # 9A

MOV P1, A # make flow in West direction

A CALL DELAY

MOV , # A6

MOV P1, A # make flow in South direction

A CALL DELAY

MOV A, # A9

MOV P1, A # Make flow in East direction

A CALL DELAY

SJMP, BACK

DELAY : MOV R3, #50

HERE2 : MOV R4, #255

HERE : DJNZ R4, HERE

DJNZ R3, HERE 2

RET

If we are using bulbs, we can glow it by making corresponding port pins high. Ie just opposite of

the above operation. Then the hex codes are;

95H, 65H, 59H, and 56H respectively.

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Trainer kit design

The typical trainer kit design shown in figure 2.15

MODULE-3

ANALOG TO DIGITAL CONVERTER

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An ADC produces a digital output that is proportional to the value of the input analog

signal. When an analog signal is processed by a digital system, an ADC is used to convert analog

voltage to digital form suitable for processing by a digital system.

Types of ADCs

1) DELTA SIGMA ADC

FIGURE 3.1

In a convertor, the analog input voltage signal is connected to the input of an integrator,

producing a voltage rate- of change or slope, at the output corresponding to input magnitude.

This ramping voltage is then compared against ground potential (0Volts) by a comparator. The

comparator acts as 1-bit ADC, producing 1 bit of output depending on whether integrated

output is positive or negative. The comparators output is then latched through a D-type flip

flop clocked at a high frequency, and fed back to another input channel on the integrator to

drive the integrator in the direction of a 0 volt output.

This method is based on the data modulation where the difference between 2 successive

sample is quantized delta modulation is a 1 bit quantization method.

The O/P of a delta modulator is a single bit data stream where the relative number 1 is

and 0s indicates the level or amplitude of the input signal. The number of 1 is over a given

number of clock cycles establishes the signal amplitudes during that interval. A max number of

1 is corresponds to the max positive i/p voltage. A number of 1 is equal to the one half the

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maximum corresponds to the i/p V. This is shown in figure below. E.g.:- assume that 4096 is

occur during the interval when the i/p signal is a +ve menu. Since 0 is the mid point of the

dynamic range of the i/p signal, 2048 is occur during the interval when the i/p s

One of the more advanced ADC technologies is the so-called delta-sigma, or

(using the proper Greek letter notation). In mathematics and physics, the

capital Greek letter delta () represents difference or change, while the

capital letter sigma () represents summation: the adding of multiple terms

together. Sometimes this converter is referred to by the same Greek letters

in reverse order: sigma-delta, or .

In a converter, the analog input voltage signal is connected to the input

of an integrator, producing a voltage rate-of-change, or slope, at the output

corresponding to input magnitude. This ramping voltage is then compared

against ground potential (0 volts) by a comparator. The comparator acts as

a sort of 1-bit ADC, producing 1 bit of output ("high" or "low") depending on

whether the integrator output is positive or negative. The comparator's

output is then latched through a D-type flip-flop clocked at a high frequency,

and fed back to another input channel on the integrator, to drive the

integrator in the direction of a 0 volt output. The basic circuit looks like this:

The leftmost op-amp is the (summing) integrator. The next op-amp the

integrator feeds into is the comparator, or 1-bit ADC. Next comes the D-type

flip-flop, which latches the comparator's output at every clock pulse, sending

either a "high" or "low" signal to the next comparator at the top of the

circuit. This final comparator is necessary to convert the single-polarity 0V /

5V logic level output voltage of the flip-flop into a +V / -V voltage signal to

be fed back to the integrator.

If the integrator output is positive, the first comparator will output a "high"

signal to the D input of the flip-flop. At the next clock pulse, this "high"

signal will be output from the Q line into the noninverting input of the last

comparator. This last comparator, seeing an input voltage greater than the

threshold voltage of 1/2 +V, saturates in a positive direction, sending a full

+V signal to the other input of the integrator. This +V feedback signal tends

to drive the integrator output in a negative direction. If that output voltage

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ever becomes negative, the feedback loop will send a corrective signal (-V)

back around to the top input of the integrator to drive it in a positive

direction. This is the delta-sigma concept in action: the first comparator

senses a difference () between the integrator output and zero volts. The

integrator sums () the comparator's output with the analog input signal.

Functionally, this results in a serial stream of bits output by the flip-flop. If

the analog input is zero volts, the integrator will have no tendency to ramp

either positive or negative, except in response to the feedback voltage. In

this scenario, the flip-flop output will continually oscillate between "high" and

"low," as the feedback system "hunts" back and forth, trying to maintain the

integrator output at zero volts:

Signal is a ve maximum.

SUCCESSIVE APPROXIMATION ADC

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FIGURE 3.2

It consists of a very special counter circuit known as a successive approximation register.

Instead of counting up in binary sequence, this register counts by trying all values of bits

starting with the MSB and finishing at the LSB. Throughout the count process, the register a

monitor the comparators output to see if the binary count is less than or greater than the

analog signal input, adjusting the bit values accordingly. The way the register counts is identical

to the trial and fit method of decimal to binary conversion, whereby different values of bits

are tried from MSB to LSB to get a binary number that equals the original decimal number. The

advantage to this counting is much faster results the DAC output converges on the analog signalinput in much larger steps than with the 0 to full count sequence of a regular counter.

Figure shows a basic block diagram of a 4 bit successive approximation ADC. It consist of

a DAC, SAR and comparator. The bits of ADC are enabled one at a time. Starting with the MSB.

As each bit is enabled, the comparator produces an o/p that indicate whether the analog i/p

voltage is greater or less than the o/p of DAC. If the D/A o/p is greater than the analog i/p, the

comparators o/p is now, causing the bit in the register to reset. If the DAC o/p is less than

analog. i/p the bit is retained in the register.

In order to better understand the operation, take a 4 bit conversion. Assume that DAC

has the following characteristics. V out = 8V, for 23

bit,(MSB), v out =4V, for the 22

bit, V

out=2V for 21

bit and v out=IV for the 20

bit (LSB

FLASH ADC

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FIGURE 3.3

It is also called parallel A/D connecter. It is formed of a series of comparators, each one

comparing the input signal to a unique reference voltage. The comparator outputs connects to

the input of a priority encoder circuit, which then produces a binary output.

V ref is a stable reference voltage provided by a precision voltage regulator. As the

analog input voltage exceeds the reference voltage at each comparators, the comparator

outputs will sequentially saturate to a high state. The priority encoder generates a binary

number based on the highest-order active input, ignoring all other active inputs.

An additional advantage of the flash converter is the ability for it to produce a non-

linear output. With equal-value resistors in the reference voltage divider network, each

successive binary count represents the same amount of analog signal increase providing a

proportional response.

2) SINGLE SLOPE ADC

In this system a continuous sequence of equally spaced pulses is passed through a gate.

The gate is normally closed and is opened at the instant of the beginning of a linear ramp. The

number of pulses which pass through the gate is proportional to the voltage being measured.

The clear pulse resets the counter to the zero count. The counter then records in binary form

the number of pulses from the clock time. The clock is a source of pulse. Since the number of

pulses counted increases linearly with time, the binary word representing this count is used as

the input of D/A converter. As long as the analog input Va is greater than Vd, the comparator

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output is high and the AND gate is open for the transmission of pulses to the counter when Vd

exceeds Va, the comparator output changes to the low value and the AND gate is disable.

FIGURE 3.4

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It does not require a D/A converter. It uses a linear ramp generator to produce a

constant slope reference voltage.

All the beginning of the conversion cycle the counter is reset and the ramp generator

0/p is 0 V. The analog i/p is greater than the sequence voltage at this point and therefore

produce a high o/p from the comparator. This high enables +ve clock to the counter and startsthe ramp generator. Assume that the slope of ramp is iv/ms. It will be increase until it equals

the analog i/p. At this point the ramp is reset and binary count is stored in the latches by the

control logic. Let us assume that the analog i/p is 2 v at the point of comparison. This means the

ramp is also 2V and has been running for 2ms. Since the comparator o/p has been high for 2ms,

200 clock pulses have been allowed to pass through the gate to the counter. At the point of

comparison, the counter is in the binary state representing decimal 200 with the proper scaling

and recording, this binary number can be displayed as 2.00 V.

3) DAUL SLOPE ADC

The analog part of the circuit consists of a high input impedance buffer A, precision

integrator A2 and a voltage comparator. The converter first integrates the analog input signal

Va for a fixed duration of 2 n clock periods. Then it integrates an internal reference voltage VR

of opposite polarity until the integrator output is zero. The number N of clock cycles required to

return the integrator to zero is proportional to the value of Va averaged over the integration

period. N represents the desired output code.

FIGURE 3.5

The operation of this type of ADC is similar to that of the single slope ADC. Except that a

variable slope ramp and a fixed slope ramp or both used. This converter in common is digital

voltmeters and other types of measurement instruments.

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A ramp generator A is used to produce the dual stope characteristics. Assuming that the

counter is reset and o/p of the integrator zero. Now, assume that a + ve i/p v tg is applied

through the switch as selected the control logic. Since the inverting up of A1 is at virtual ground

and assume that Vin is constant for a period of time, here will be constant current through the

i/p resistor R and thereafter the capacitor C . C with charge linearity as the current is constant,and thus a ve going linear vtg. Ramp on the o/p of A1.

When the converter reaches a specific count, it will be reset, and the control logic will

switch the ve reference voltage (-vref) to i/p A1. This point, the capacitor is charged to a

negative (-ve) proportional to the i/p analog voltage.

Now capacitor discharges linearly due to the constant current from the v ref. This produces a

+ve going ramp on the A1 o/p starting at ve end with a constant slope that is independent ofthis charge voltage.

As the capacitor discharges, the counter advances from reset state. The time taken to

discharge to zero depends on the initial voltage ve across the discharge rate is constant. When

the integrator o/p reaches zero. The comparator switches to the low state disable the clock to

the counter. The binary counter is proportional to this because it takes the capacitor to

discharge depends only on ve and the counter records this interval of time

DIGITAL TO ANALOG CONVERSIONDigital to analog conversion is an important interface process in many application. An

example is a voice signal that has been digitized for processing or transmission and must be

charged into an approximation of the originated signal to ultimately drive a speaker.

In real time applications, we need to use physical quantities. In order to work with then

it is required to connect analog signal to digital and vice versa. Digital signals are easy to be

processed. Once digital data have been processed by DSP, they are converted to analog form

using digital to analog converter.

Types of DA converters are

BINARY-WEIGHTED INPUT D/A CONVERTER

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The one method of D/A conversion uses a resistor net work with value that refers the

binary weight of the i/p but if the digital code. In fig the switch symbol represents the

transistor. The op-amp provides high impedance load to the resister net work and at inverting

i\p look like virtual ground so that the o/p is proportional to the current through the feedback

resister Rf. Almost all load impedance o/p of the op-amp. The inverting/ i/p is approximately atOV.

The lowest value of resistor (R) corresponds to the highest binary weighted input (23). Each of

the other resistors is a multiple of R, 2R,4R and 8R corresponding to the binary weights 23,2

2,

and 21

respectively. One of the disadvantages of this type of D/A converter to the number

different resister values.

FIGURE 3.6

It was network of resistance values that represent binary weights of input bits of digitalcode. Each input will have current or have no current depending on input voltage level. If

micro controller based system design1

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