micro process

8/11/2019 Micro Process

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Conversion subroutine::

CONVERSION:

MVI A,00H

OUT PB ; Send address to select IN0

MVI A,08H ;Latch address by giving ALE High

OUT PB

BACK: MVI A,18H


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OUT PB ; Make SOC High

MVI A,08H

OUT PB ; Make SOC Low

MVI A,00H

OUT PB ; Make ALE Low

LOOP: IN PC

ANI 01H

JZ LOOP ; Wait for EOC

IN PA

RET ; Return value and store Accumulator

MVI A,98H

OUT CWR

L2: CALL CONVERSION

CPI 80H

JC L1

MVI A,0EH

OUT CWR


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JMP L2

L1: MVI A,OFH

OUT CWR

JMP L2

SUBROUTINE conversion :

MVI A,00H

OUT PB

MVI A,08H

OUT PB

MVI C,0AH

L3: DCR C

JNZ L3

MVI A,18H

OUT PB

MVI A,08H

OUT PB

MVI A,00H

OUT PB


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L4: IN PC

ANI 01H

JZ L4

IN PA

RET

Program:

MVI A,98H

OUT CWR

L2: CALL CONVERSION

CPI 80H

JC L1

MVI A,0EH

OUT CWR

JMP L2

L1: MVI A,OFH

OUT CWR


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JMP L2


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Interfacing Analog to Digital Data

ConvertersIn most of the cases, the PIO 8255 is used for interfacing

the analog to digital converters with microprocessor.

We have already studied 8255 interfacing with 8086 as an

I/O port, in previous section. This section we will only

emphasize the interfacing techniques of analog to digital

converters with 8255.

The analog to digital converters is treaded as an input

device by the microprocessor, that sends an initialisingsignal to the ADC to start the analogy to digital data

conversation process. The start of conversation signal is a

pulse of a specific duration.


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M Krishhna Kumar MAM/M3/LU9g/V1/2004 2

The process of analog to digital conversion is a slow

process, and the microprocessor has to wait for the digital

data till the conversion is over. After the conversion isover, the ADC sends end of conversion EOC signal to

inform the microprocessor that the conversion is over and

the result is ready at the output buffer of the ADC. These

tasks of issuing an SOC pulse to ADC, reading EOC signal

from the ADC and reading the digital output of the ADC

are carried out by the CPU using 8255 I/O ports.

The time taken by the ADC from the active edge of SOC

pulse till the active edge of EOC signal is called as theconversion delay of the ADC.

It may range any where from a few microseconds in case

of fast ADC to even a few hundred milliseconds in case of

slow ADCs.

The available ADC in the market use different conversion

techniques for conversion of analog signal to digitals.

Successive approximation techniques and dual slopeintegration techniques are the most popular techniques

used in the integrated ADC chip.


Converters (cont..) M Krishhna Kumar

MAM/M3/LU9g/V1/2004 4

General algorithm for ADC interfacing contains the

following steps:

1. Ensure the stability of analog input, applied to the ADC.

2. Issue start of conversion pulse to ADC

3. Read end of conversion signal to mark the end of

conversion processes.

4. Read digital data output of the ADC as equivalent digital


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output.


Converters (cont..)

M Krishhna Kumar MAM/M3/LU9g/V1/2004 5Analog input voltage must be constant at the input of the

ADC right from the start of conversion till the end of the

conversion to get correct results. This may be ensured by a

sample and hold circuit which samples the analog signal

and holds it constant for a specific time duration. The

microprocessor may issue a hold signal to the sample and

hold circuit.If the applied input changes before the complete

conversion process is over, the digital equivalent of the

analog input calculated by the ADC may not be correct.


Converters (cont..)


ADC 0808/0809 :The analog to digital converter chips 0808 and 0809 are 8-

bit CMOS, successive approximation converters. This

technique is one of the fast techniques for analog to digital

conversion. The conversion delay is 100s at a clock

frequency of 640 KHz, which is quite low as compared to

other converters. These converters do not need any

external zero or full scale adjustments as they are alreadytaken care of by internal circuits. These converters

internally have a 3:8 analog multiplexer so that at a time

eight different analog conversion by using address lines -



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Converters (cont..) M Krishhna Kumar

MAM/M3/LU9g/V1/2004 7

ADD A, ADD B, ADD C. Using these address inputs,

multichannel data acquisition system can be designedusing a single ADC. The CPU may drive these lines using

output port lines in case of multichannel applications. In

case of single input applications, these may be hardwired

to select the proper input.

There are unipolar analog to digital converters, i.e. they are

able to convert only positive analog input voltage to their

digital equivalent. These chips do no contain any internal

sample and hold circuit.Interfacing Analog to Digital Data

Converters (cont..)


If one needs a sample and hold circuit for the conversion


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of fast signal into equivalent digital quantities, it has to be

externally connected at each of the analog inputs.

Vcc Supply pins +5V

GND GNDVref + Reference voltage positive +5 Volts

maximum.

Vref_ Reference voltage negative 0Volts

minimum.


Converters (cont..)

M Krishhna Kumar MAM/M3/LU9g/V1/2004 10I/P0

I/P7 Analog inputs

ADD A,B,C Address lines for selecting analog

inputs.

O7 O0 Digital 8-bit output with O7 MSB and

O0 LSB

SOC Start of conversion signal pin

EOC End of conversion signal pin

OE Output latch enable pin, if high enables

output

CLK Clock input for ADC



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Converters (cont..)


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Example: Interfacing ADC 0808 with 8086 using 8255

ports. Use port A of 8255 for transferring digital data

output of ADC to the CPU and port C for control signals.

Assume that an analog input is present at I/P2 of the ADCand a clock input of suitable frequency is available for

ADC.

Solution: The analog input I/P2 is used and therefore

address pins A,B,C should be 0,1,0 respectively to select

I/P2. The OE and ALE pins are already kept at +5V to

select the ADC and enable the outputs. Port C upper acts

as the input port to receive the EOC signal while port C

lower acts as the output port to send SOC to the ADC.Interfacing Analog to Digital Data

Converters (cont..)


Port A acts as a 8-bit input data port to receive the digital

data output from the ADC. The 8255 control word is

written as follows:

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 1 0 0 0

The required ALP is as follows:

MOV AL, 98h ;initialise 8255 as

OUT CWR, AL ;discussed above.

MOV AL, 02h ;Select I/P2 as analog

OUT Port B, AL ;input.

Interfacing Analog to Digital DataConverters (cont..) M Krishhna Kumar

MAM/M3/LU9g/V1/2004 16

MOV AL, 00h ;Give start of conversion

OUT Port C, AL ; pulse to the ADC


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MOV AL, 01h

OUT Port C, AL

MOV AL, 00h

OUT Port C, ALWAIT: IN AL, Port C ;Check for EOC by

RCR ; reading port C upper and

JNC WAIT ;rotating through carry.

IN AL, Port A ;If EOC, read digital equivalent

;in AL

HLT ;Stop.


Converters (cont..)

Interfacing with 8085


Interfacing Digital To Analog

Converters (cont..)


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INTERFACING DIGITAL TO ANALOG CONVERTERS: The

digital to analog converters convert binary number into

their equivalent voltages. The DAC find applications in

areas like digitally controlled gains, motors speed controls,programmable gain amplifiers etc.

AD 7523 8-bit Multiplying DAC : This is a 16 pin DIP,

multiplying digital to analog converter, containing R-2R

ladder for D-A conversion along with single pole double

thrown NMOS switches to connect the digital inputs to the

ladder.


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The pin diagram of AD7523 is shown in fig the supply

range is from +5V to +15V, while Vref may be any where

between -10V to +10V. The maximum analog output

voltage will be any where between -10V to +10V, when allthe digital inputs are at logic high state.

Usually a zener is connected between OUT1 and OUT2 to

save the DAC from negative transients. An operational

amplifier is used as a current to voltage converter at the

output of AD to convert the current out put of AD to a

proportional output voltage.


Converters (cont..)


It also offers additional drive capability to the DAC output.

An external feedback resistor acts to control the gain. One


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may not connect any external feedback resistor, if no gain

control is required.

EXAMPLE: Interfacing DAC AD7523 with an 8086 CPU

running at 8MHZ and write an assembly language programto generate a sawtooth waveform of period 1ms with

Vmax 5V.

Solution: Fig shows the interfacing circuit of AD 74523

with 8086 using 8255. program gives an ALP to generate a

sawtooth waveform using circuit.


Converters (cont..)


ASSUME CS:CODE

CODE SEGMENT

START: MOV AL,80h ;make all ports output

OUT CW, AL

AGAIN: MOV AL,00h ;start voltage for ramp

BACK : OUT PA, AL

INC AL

CMP AL, 0FFh

JB BACK

JMP AGAIN

CODE ENDS

END START

Example (cont..)


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In the above program, port A is initialized as the output

port for sending the digital data as input to DAC. The rampstarts from the 0V (analog), hence AL starts with 00H. To

increment the ramp, the content of AL is increased during

each execution of loop till it reaches F2H.

After that the saw tooth wave again starts from 00H, i.e.

0V(analog) and the procedure is repeated. The ramp period

given by this program is precisely 1.000625 ms. Here the

count F2H has been calculated by dividing the required

delay of 1ms by the time required for the execution of the

loop once. The ramp slope can be controlled by calling a

controllable delay after the OUT instruction.


Converters (cont..)


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Interfacing of LCD with P

A liquid crystal display(LCD) is a thin, flat electronic visual

display that uses the light modulating properties of liquid

crystals (LCs).

Applications:-

Used in computer monitors , televisions , instrument panels,

video players, gaming devices, clocks , watches, calculators ,

and telephones etc.


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Interfacing of ADC with P

1. A, B, C addresses to select IN0-IN7

2. activate Address latch enable (ALE) to latch in the address.

3. SC is for Start Conversion.

4.EOC is for End of Conversion

5. OE is for Output Enable.

6. The output pins D0-D7 provides the digital output from the chip.

7. Vref (-) and Vref (+) are the reference voltages


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SELECTING AN ANALOG CHANNEL How to select the channel

using three address pins A, B, C is shown in Table below:


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Interfacing of ADC0808 with P

Program : MVI A,99H

OUT 63H

MVI B,00H

LOOP: MOV A,B

ANI 1CH

ORI 01H

OUT 61H


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ANI 1CH

OUT 61H

UP: IN 62H

ANI 01H

CPI 01H

JNZ UP

MVI A,02H

OUT 61H

IN 60H

OUT DISPLAY

CALL DELAY

MOV A,B

ADI 04H

MOV B,A

JMP LOOP

Interfacing of DAC with P

Interfacing and pin diagram

Pin Description

The supply range is from +5V to +15V, while Vref may be any where

between -10V to +10V.

The maximum analog output voltage will be any where between -10V to

+10V, when all the digital inputs are at logic high state.


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Usually a zener diode is connected between OUT1 and OUT2 to save the

DAC from negative transients.

An operational amplifier is used as a current to voltage converter at the

output of AD to convert the current out put of AD to a proportional outputvoltage.

DAC AD-7523


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Temperature control


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Interfacing of Traffic light controller


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Interfacing of stepper motor

A stepper motor(or step motor) is a brushless DC electric motorthat divides a full rotation into a number of equal steps.

The motor's position can then be commanded to move and hold

at one of these steps without any feedback sensor (an open-loop


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controller), as long as the motor is carefully sized to the

application.

Interfacing

There are two possible modes:-

1.Mode 1(Full stepping):-

Stepping motors have 200 rotor teeth, or 200 full steps per

revolution of the motor shaft. Dividing the 200 steps into the 360 of

rotation equals a 1.8 full step angle

2. Mode 2(Half stepping):-

Half step simply means that the step motor is rotating at 400 steps

per revolution. In this mode, one winding is energized and then two


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windings are energized alternately, causing the rotor to rotate at half

the distance, or 0.9.

In mode1(Full stepping) ,the motor moves by 1.8, to do this two bits

are changed at a time ,the bit pattern is as

Program for full stepping:

MVI A,80H

OUT 6BH

BACK:LXI H,2000H

MVI C,04H

UP: MOV A,M

OUT 68H

CALL DELAY

INX H

DCR C

JNZ UP

JMP BACK

Address Data


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2000 0A

2001 09

2002 05

2003 06


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8259 PIC

Used when number of input/output device transfer the data to

the P and when all of them are connected to same interrupt

level

Commonly used as interfacing device along with 8085 or 8086

FEATURES: Can manage 8 interrupts

Can be cascaded with another 8259 to increase the interrupts to

64.

Internal priority resolver.

Individually mask each interrupt request.

Read the status of pending , in-service and the masked interrupts


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Pin functions

D0-D7 Bidirectional tri-stated buffered data lines.

connected to data bus directly or throughbuffers

RD Active low read control

WR Active low write control

A0 Address input line used to select the control

register

CS Active low chip select

CAS0-2 Bi-directional 3 cascaded lines .In master mode ,

PIC places slave ID no. on these lines and in

slave mode , the PIC reads slave ID no. from

master on these lines. It may be regarded as

slave select

SP/EN Slave program/enable. In non buffered mode , itis SP input ,used to distinguish master slave PIC

and in buffered mode ,it is output line used to

enable the buffer

INT Interrupt lines, connected to INTR of

microprocessor

INTA Interrupt acknowledge , received active low

from microprocessor

IR0-7 Interrupt request lines generated by peripherals

devices


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8279 Programmable keyboard/display interface

It is designed by Intel

8279 has two sections: keyboard and display

used to interface keyboard and display of a system to the

microprocessor


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Advantage of 8279 is that it is able to drive the signals for

both keyboard and display and hence it is possible for the

microprocessor to concentrate in its routine tasks

Support 64 contact key matrix with two more keys

CONTROL and SHIFT

Provides 2 operating modes:- Input and output

Input mode provides 3 basic modes:-

1. Scanned keyboard mode

2.Scanned sensor matrix mode

3.Strobed Input mode.

Two output modes:

1.Left entry (Typewriter type).

2.Right entry (Calculator type).

It provides 16 byte display RAM to display 16 digits and

interfacing 16 digits.

It has inbuilt debounce key .

8279 chip provides a set of four scan lines and eight returnlines for interfacing keyboards and a set of eight output

lines for interfacing display


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DB0-DB7: These are bidirectional data bus lines. The data

and command words to and from the CPU are transferred

on these lines.

RD, WR ( Input / Output ) READ/WRITE:

These input pins enable the data buffers to receive or send

data over the data bus.

A0(Address lines) : This is used to select one of the

internal registers of 8279.

A0 Selected register

0 Data register

1 Control/status register


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CS : -Chip SelectA low on this line enables 8279 for normal

read or write operations. Other wise, this pin should remain

high.

RESET : -This pin is used to reset 8279. A high on this line reset

8279.

CLK : -This is a clock input used to generate internaltiming

required by 8279.

Vss, Vcc : -These are the ground and power supply lines for the

circuit.

IRQ : This interrupt output lines goes high when there is a data

in the FIFO sensor RAM. The interrupt lines goes low with each

FIFO RAM read operation but if the FIFO RAM further contains

any key-code entry to be read by the CPU, this pin again goes

high to generate an interrupt to the CPU.

Key board Data:-

RL0RL7(Return Lines):- These are the input lineswhich are

connected to one terminal of keys, while the other terminal of

the keys are connected to the decoded scan lines. These are

normally high, but pulled low when a key is pressed.

SHIFT :- The status of the shift input lines is stored along with

each key code in FIFO, in scanned keyboard mode. It is pulled

up internally to keep it high, till it is pulled low with a key

closure.


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CNTL/STB- CONTROL/STROBED I/P Mode : Inkeyboard mode,

this lines is used as a control input and stored in FIFO on a key

closure. The line is a strobed lines that enters the data into FIFO

RAM, in strobed input mode. It has an interrupt pull up. The

lines is pulled down with a key closer.

Display output lines:-

OUT A0A3and OUT B0B3:- These are the output ports for two

16*4 or 16*8 internal display refresh registers. The data from

these lines is synchronized with the scan lines to scan thedisplay and keyboard. The two 4-bit ports may also as one 8-bit

port.

BD (Blank Display) :- This output pin is used to blank the

display.

SL 0-SL 3-Scan Lines : -These lines are used to scan the keyboardmatrix and display digits. These lines can be programmed as

encoded or decoded, using the mode control register.


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FUNCTIONAL BLOCK DIAGRAM :

It consists 4 main section.

1.

CPU interface and control section.

2.Scan section

3.Keyboard Section

4.Display section.

CPU INTERFACE AND CONTROL SECTION:

It consists of

1.Data buffers

2. I/O control


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3.Control and timing registers.

4.Timing and control logic.

Data Buffers:

8-bit bidirectional buffer.

Used to connect the internal data bus and external data bus.

I/O control:

I/O control section uses the A0,CS, RD and WR signals to controls

the data flow.

The data flow is enabled by CS=0 otherwise it is the high

impedance state.

A0=0 means the data is transferred.

A0=1 means status or command word is transferred.

Timing and control registers:-

Store the keyboard and display modes and others operating condition

programmed by the CPU.


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The modes are programmed by sending proper command A0=1.

Timing and control logic:-

It consist of timing counter chain.

First counter is divided by N pre-scalar that can be programmed to give

an internal frequency of 100 KHz.

The other counter is divide by basic internal frequency .Listed below

It has two modes,

1.Encoded mode

2.Decoded mode.

ENCODED MODE:

It provide binary count from 0000 to 1111 by four scan lines(SC3-

SC0)by active high inputs. It is externally decoded to provide 16scan lines Display use all 16 lines to interface 16 digit 7 segment

display.

But keyboard use only 8 scan lines out of 16 lines.DECODED

MODE:


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In this mode ,the internal decoder decodes the least 2 significant

bits.

It provide four possible combination from (SC0-SC3) such as 1110

,1101 ,1011 and 0111.

This four active low outputs line is used directly to interface 4

digit 7-segment display ,8*4 matrix keyboard

This is consist of

Return buffers.

Keyboard debounce control.

FIFO / sensor RAM.

FIFO / sensor RAM status.

RETURN BUFFERS:

8 return lines(RL7-RL0) are buffered and latched by when each

row scan in scanned keyboard or sensor matrix mode.

In strobed mode ,the contents of return lines are transferred to

FIFO Ram.

KEYBOARD DEBOUNCE AND CONTROL:

It is enabled only when keyboard mode is selected.

In this mode , return lines are scanned whether any keys are

closed in the row.

If debounce circuit is detect any closed switch it wait about 10

msec.


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It is continued , the status of SHIFT and CONTROL keys are

transferred into RAM.

FIFO/SENSOR RAM:

This is a dual function of 8*8 RAM.

In scanned key board mode and Strobed input mode , It is FIFO.

In sensor matrix mode it is a sensor RAM.

FIFO/SENSOR RAM status:

This is used to tell the status of FIFO/SENSOR RAM.

The status of logic also makes IRQ signal is High , When FIFO is not

empty.

It consists of,

1.Display RAM.

2.

Display Address registers.

3.Display registers.

DISPLAY RAM:-

It is a 16*8 RAM which stores 16 digits display codes.

It can be accessed by CPU directly.

In Decoded mode,8279 uses only first four location of Display

RAM.

In Encoded mode,8279 uses only first eight location of Display

RAM.


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DISPLAY ADDRESS REGISTERS:

Used to hold address of the byte currently write or read by the

CPU and scan count value.

In auto increment mode, address in the register is automatically

incremented for each write or read.

DISPLAY REGISTERS:

It is a Two 4-bit registers such as , A and B.

They hold the bit patterns of character to be displayed.

The content of display registers A and B can B blanked and

inhibited individually.

It is two types,

1. Input modes.

2.Display modes.

INPUT MODES:

It is basically 3 types,

1.Scanned keyboard.

2.Scanned sensor matrix.

3.

Strobed mode.

SCANNED KEYBOARD:

Key board can be scanned in two ways.

1.Encoded Scan 2.Decoded Scan.


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ENCODED SCAN:

In this scan, scan lines (SL2-SL0) are decoded externally to provide

8 scan lines.

Additionally it provides 8 return lines.

So the size of matrix keyboard is 8*8 (i.e Scan * Return)=64.

When the key is pressed , it is stored the status of return lines ,

Scan lines ,SHIFT and CNTL/STB keys into FIFO RAM.

The Scanned keyboard structure is,

2-KEY LOCKOUT:

In this mode, the two key depression is not allowed.

When any key is depressed, the debounce logic is set and 8279

checks for any key depress next two scans.

N-KEY ROLLOVER:

Each key is depression is treated as independently from all others.

It is basically two types,

1.Left entry (Type writer mode).

2.Right entry (Calculator mode).

LEFT ENTRY:


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In this mode , 8279 display characters from left to right.

Like a typewriter.

RIGHT ENTRY:

In this mode , 8279 display characters from Right to left.

Like a Calculator.

micro process

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