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7/21/2019 Micro Wind

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INTRODUCTION TO MICROWIND

LAYOUT

Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the

representation of anintegrated circuit in terms of planargeometric shapes which correspond to the

patterns of metal,oxide,or semiconductor layers that make up the components of the integratedcircuit. In simple words, layout means laying out the circuit components on a silicon substrate. In

todays era there can be multiple layers of different materials on the same silicon, and/or there can

be different arrangements of the smaller parts for the same component and so on. Using a

computer-aided layout tool, the layout engineeror layout technicianplaces and connects all of

the components that make up the chip such that they meet certain criteriontypically:

performance, size, density, and manufacturability.Thus from a layout one ends with a mask set.A mask set or a photomask set is a series of electronic data that define geometry for the

photolithography steps of semiconductor fabrication. A mask set for a modern process typically

contains as many as twenty or more masks, each of which defines a specific photolithographic step

in the semiconductor fabrication process. Examples of masks include: n-well, p-well, n-diff, p-diff,

polysilicon, contact, metal layers etc.

The generated layout must pass a series of checks in a process known as physical verification. The

most common checks in this verification process are design rule checking(DRC),layout versus

schematic (LVS), parasitic extraction, antenna rule checking, and electrical rule checking

(ERC).When all verification is complete, the data is translated into an industry standard format,

typically GDSII, and sent to a semiconductor foundry. The process of sending this data to the

foundry is called tapeout. Standard format is GDSII (Gerber Data Stream Information

Interchange). It includes information on the layers of the design and the 2D geometries. OASIS

(Open Artwork System Interchange Standard) is a new (2004) specification which is attempting to

replace GDSII. It is more efficient in its storage format (10-50 times) than GDSII. Other common

formats are CIF (Caltech Interchange Format), DXF(Drawing Exchange FormatAutoCAD), and

Gerber (Printed Circuit BoardPCB) files.
https://en.wikipedia.org/wiki/Integrated_circuithttps://en.wikipedia.org/wiki/Geometric_shapehttps://en.wikipedia.org/wiki/Metalhttps://en.wikipedia.org/wiki/Silicon_oxidehttps://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Photolithographyhttps://en.wikipedia.org/wiki/Design_rule_checkinghttps://en.wikipedia.org/wiki/Design_rule_checkinghttps://en.wikipedia.org/wiki/Layout_versus_schematichttps://en.wikipedia.org/wiki/Layout_versus_schematichttps://en.wikipedia.org/wiki/Layout_versus_schematichttps://en.wikipedia.org/wiki/Layout_versus_schematichttps://en.wikipedia.org/wiki/Parasitic_extractionhttps://en.wikipedia.org/wiki/Parasitic_extractionhttps://en.wikipedia.org/wiki/Physical_verification#Antenna_Checkhttps://en.wikipedia.org/wiki/Physical_verification#Antenna_Checkhttps://en.wikipedia.org/wiki/Physical_verification#ERC_.28Electrical_rule_check.29https://en.wikipedia.org/wiki/Physical_verification#ERC_.28Electrical_rule_check.29https://en.wikipedia.org/wiki/Physical_verification#ERC_.28Electrical_rule_check.29https://en.wikipedia.org/wiki/Physical_verification#ERC_.28Electrical_rule_check.29https://en.wikipedia.org/wiki/GDSIIhttps://en.wikipedia.org/wiki/Tapeouthttps://en.wikipedia.org/wiki/Tapeouthttps://en.wikipedia.org/wiki/Tapeouthttps://en.wikipedia.org/wiki/GDSIIhttps://en.wikipedia.org/wiki/Physical_verification#ERC_.28Electrical_rule_check.29https://en.wikipedia.org/wiki/Physical_verification#ERC_.28Electrical_rule_check.29https://en.wikipedia.org/wiki/Physical_verification#Antenna_Checkhttps://en.wikipedia.org/wiki/Parasitic_extractionhttps://en.wikipedia.org/wiki/Layout_versus_schematichttps://en.wikipedia.org/wiki/Layout_versus_schematichttps://en.wikipedia.org/wiki/Design_rule_checkinghttp://en.wikipedia.org/wiki/Photolithographyhttps://en.wikipedia.org/wiki/Semiconductorhttps://en.wikipedia.org/wiki/Silicon_oxidehttps://en.wikipedia.org/wiki/Metalhttps://en.wikipedia.org/wiki/Geometric_shapehttps://en.wikipedia.org/wiki/Integrated_circuit


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LAYOUT RULES

The physical mask layout of any circuit to be manufactured using a particular process must

conform to a set of geometric constraints or rules, which are generally called layout design rules.

These rules usually specify the minimum allowable line widths for physical objects on-chip such as

metal and polysilicon interconnects or diffusion areas, minimum feature dimensions, and minimum

allowable separations between two such features.

If a metal line width is made too small, for example, it is possible for the line to break during the

fabrication process or afterwards, resulting in an open circuit. If two lines are placed too close to

each other in the layout, they may form an unwanted short circuit by merging during or after the

fabrication process. The main objective of design rules is to achieve a high overall yield and

reliability while using the smallest possible silicon area, for any circuit to be manufactured with a

particular process.

A layout which violates some of the specified design rules may still result in an operational circuit

with reasonable yield, whereas another layout observing all specified design rules may result in a

circuit which is not functional and/or has very low yield. To summarize, we can say, in general,

that observing the layout design rules significantly increases the probability of fabricating a

successful product with high yield.

The design rules are usually described in two ways:

Micron rules, in which the layout constraints such as minimum feature sizes and minimum

allowable feature separations, are stated in terms of absolute dimensions in micrometers, or,

Lambda rules, which specify the layout constraints in terms of a single parameter () and, thus,

allow linear, proportional scaling of all geometrical constraints.

Lambda-based layout design rules were originally devised to simplify the industry- standard

micron-based design rules and to allow scaling capability for various processes.

Lambda based design rules are the following (detailed design rules are given in later section):

Metal and diffusion have a minimum width and spacing of 4. Contacts are 2x2 and must be surrounded by 1 on layers above and below. Ploysilicon uses a width of 2. Polysilicon overlaps diffusion by 2 where a transistor is desired and has a spacing of 1

away where no transistor is desired.

Polysilicon and contacts have a spacing of 3 from other polysilicon or contacts. N-well surrounds PMOS transistors by 6 and avoids NMOS transistors by 6.


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Lambda Based Design Rules followed for various components

(1) N-Well

(2) Diffusion

(3) Polysilicon

4. Contacts


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5. Metal 1

MICROWIND

Microwind3.1 is a new era of creativity in deep submicron CMOS VLSI and IC Design. This is a

complete solution for deep sub micron Transistor level CMOS design and simulation. It is the

industrys most comprehensive package dedicated to microelectronics and nanotechnology; deep-

technology business of ASIC and custom IC design and simulation, as well as the latest in electronic

design automation design. Microwind3.1 is truly integrated EDA software encompassing IC designs

from concept to completion, enabling chip designers to design beyond their imagination.

It tightly integrates mixed-signal implementation with digital implementation, circuit simulation,

transistor-level extraction and verification providing an innovative education initiative to help

individuals to develop the skills needed for design positions in virtually every domain of IC industry

using CMOS VLSI.

WORKING IN MICROWIND PLATFORMBLANK WORK SCREEN


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This display window includes 4 main regions: the main menu, layout display window, the icon

menu, the layer pallete.

Icon Menu options

Pallate

To Select a Design Rule File

The software can handle various technologies. The process parameters are stored in files with the

appendix '.RUL'. The default technology corresponds to a generic 6-metal 0.25m CMOS process.

The default file is CMOS012.RUL.


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To select a new foundry, click on File Select Foundry and choose the appropriate technology in

the list.

The MICROWIND3 software work is based on a lambda grid, not on a micro grid. Consequently,

the same layout may be simulated in any CMOS technology. The value of lambda is half the

minimum polysilicon gate length. Table below gives the correspondence between lambda and

micron for all CMOS technologies.

PROCEDURE

1. Double click on Microwind icon. A window opens up.2. The layout window features a grid, scaled in lambda units. The lambda unit is fixed to half

of the minimum available lithography of the technology. The default technology is CMOS

6-metal layers 0.12m technology, consequently lambda is 0.06m (60nm).

3. The palette is located in the right corner of the screen.4. Choose 1 Lambda, 0.125 m technology. This is done by selecting FileSelect FoundaryMicrowind LiteMicrowind 3design rulesCMOS 025.rul

5. Once this is setthe required layout can be drawn.6. If pallate window is not visible on the right side of the screen. Press pallate icon from icon

menu.

7. The black screen represents p+ substrate.


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6. LAYOUT OF CMOS INEVERTER

AIM:

To set up the layout of CMOS inverter and to plot its transfer and transient characteristics.

CMOS INVERTER:

PROCEDURE:

1. Draw n-diffusion (green) of 2L thickness (min).

2. Add a polysilicon layer (red) of 2L thickness and n+ diffusion (green) with minimum 4L

thickness. Area (min)= 24L2.


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3. Connect metal 1 (blue) on both sides of n-diffusion (forming D & S contact). Each metal surface

should be 32 L2 . 1L n-diffusion should be left as such on either side of polysilicon. Check if the

design criterias are followed using DRC.

4. Select contact and connect on the metals. Contact width should be 2L.Extra metal surrounding

contact must be 2L. Change the width of n+ diffusion and metal accordingly by checking DRC.

5. Now, NMOS is complete. Next PMOS is to be created. For creating this, first a n-well has to be

formed in which polsilicon, p+ diffusion, metals and contacts are to be placed.

6. Place n-well with minimum size of 10L with 144L2. The minimum distance between N-well and

n-diffusion is 6L. And between 2 n-wells are 11L. In this layout, the n-well should be more than

24L.


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7. Draw polysilicon and then p+ diffusion on both sides of poly silicon. nwell around p+ diffusion

should be 6L,all sides. For creating PMOS repeat the same procedure as done in the case of NMOS

except instead of n-diffusion, p-diffusion has to be used.

8. Now, interconnect the gate of both the polysilicon as shown below. This creates a CMOS.


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9. Inter connect drain of NMOS and source of PMOS using Metal1 and connect contact at S of

PMOS or D of NMOS for viewing the output.

10. Check DRC. If there is corrections make them until DRC is satisfied.

11. Connect GROUND(VSS-) at source of NMOS, VDD+ at the substrate of PMOS and drain of

PMOS, clock at the input(gate) and variablet(eye) at the output side. Substrate of PMOS is n+

diffusion, therefore use a n+ diffusion inside n-well then connect it to the source of PMOS using

Metal 1. Overlap the n-diffusion layer with a metal layer and connect VDDto this via a contact.

12. Now, RUN. Check voltage vs time graph and voltage vs voltage graph.


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LAYOUT:


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EXPECTED GRAPHS:

TRANSIENT CHARACTERISTICS

TRANSFER CHARACTERISTICS:

RESULT:


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7. RING OSCILLATOR LAYOUT

AIM:

To obtain the layout of ring oscillator and to plot its waveform.

RING OSCILLATOR:

PROCEDURE:

1. Connect three CMOS inverters in series.

2. Connect output of 3rdinverter to the input of 1stinverter, 1stoutput to 2ndinput and 2ndoutput to

3rdinput using metal1. Metal width should be 3L(min).

3. Supply VDDand VSSfrom one point, so connect all VDDpoints and VSSpoints with metals.

LAYOUT:


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EXPECTED WAVEFORMS:

RESULT:

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