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RTI FPGA Programming Blockset

MicroBlaze Support DS2655 FPGA Base Module

Application Note

1.1 – May 2014

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MicroBlaze Support DS2655 FPGA Base Module - 2014 3

Contents

Contents

About This Document ................................................................ 4 Document Symbols and Conventions ........................................................................................ 4

Overview ...................................................................................... 5

Example of SCALEXIO Processing Unit with DS2655 FPGA Base Module: RTI FPGA Programming Blockset Using MicroBlaze ................................................................................... 6 Software Prerequisites ............................................................................................................................. 7 Constructing the MicroBlaze Core with Xilinx Platform Studio ................................................ 8 Constructing the Simulink FPGA Model for the DS2655 .......................................................... 14 Constructing the Software Component .......................................................................................... 19

Importing Software Projects ....................................................................................................... 21 Constructing the Processor Interface with ConfigurationDesk .............................................. 22 Replacing and Restoring Software in the Bitstream .................................................................. 25 Measured Delays ..................................................................................................................................... 27

4 MicroBlaze Support DS2655 FPGA Base Module - 2014

About This Document

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MicroBlaze Support DS2655 FPGA Base Module - 2014

Overview

This application note describes how to use a MicroBlaze processor block as part of a Simulink FPGA model with the dSPACE RTI FPGA Programming Blockset.


Example of SCALEXIO Processing Unit with DS2655 FPGA Base Module: RTI FPGA Programming Blockset Using MicroBlaze

This section gives a simple example of using the MicroBlaze processor core within the RTI FPGA Programming Blockset. The example application takes an unsigned 32-bit integer input and feeds it into the MicroBlaze via shared memory. The MicroBlaze adds a constant value of 3 to the input and writes the result back via shared memory. Additionally the MicroBlaze is set up with an interrupt controller. The interrupt controller is connected to the “data new” port of the incoming data port and triggers an interrupt service function inside the MicroBlaze which adds the number of interrupts modulo 1000 to the input data multiplied with 1000. The model is composed of two parts: The computation node (CN) model running on the SCALEXIO Processing Unit and the FPGA model (containing the MicroBlaze) running on the DS2655.


Software Prerequisites The workflow described in this document requires the following software installations: dSPACE RCP & HIL RLS2013-B including RTI FPGA Programming Blockset 2.6

or later

Xilinx ISE Design Suite 14.6 or later

Xilinx System Generator 14.6 or later

Xilinx Platform Studio and Embedded Development Kit (EDK)

It is recommended to use Windows 7 as operating system.

The following descriptions and instructions are based on RTI FPGA Programming Bockset 2.6 and Xilinx ISE Design Suite 14.6.


Constructing the MicroBlaze Core with Xilinx Platform Studio

First a MicroBlaze core using Xilinx Platform Studio (XPS) has to be constructed by performing these steps. Where not specified, use default settings and click next. Create a new directory <FPGAModelDir>. Do not use whitespaces in your

paths or project names.

Create a subdirectory XPS.

Launch XPS. Select Create New Project Using Base System Builder.

Project file: <FPGAModelDir>\XPS\system.xmp

Interconnect type: AXI Bus

Create a system for a custom board:

Architecture Kintex 7, device: XC7K160T, package fbg676, speed grade -2, 125 MHz, Reset polarity: Active High, CPU clock: 100MHz

Single MicroBlaze Processor System

Local memory: 64KB

The basic MicroBlaze is now configured and you should see the system assembly view.

Select the Graphical Design View and verify that the clocking was set correctly. Sometimes incorrect clocking is displayed in Xilinx XPS even though it was configured correctly. In this case start over from the beginning. Input CLK of the clock generator should be 125MHz, the output of the clock generator 100MHz.


The MicroBlaze in this configuration is driven by a clock generator. Since the MicroBlaze must run in sync with the Simulink-model, the clock generator needs to be removed as follows: Select the Ports tab in the system assembly view.

Expand all ports. In the Connected Port column, replace all occurrences of the clock generator output clock_generator_0:CLKOUT0 by External Ports - CLK_N. These are by default the ports: axi4lite_0, microblaze_0_dlmb, microblaze_0_ilmb, (BUS_IF) DLMB, (BUS_IF) ILMB, (BUS_IF) M_AXI_DP, (BUS_IF) M_AXI_IP, proc_sys_reset_0, debug_module (BUS_IF) S_AXI

Likewise, all connections to clock_generator_0: LOCKED must be configured as External Port: proc_sys_reset_0_Dcm_locked_pin. The system assembly port view should now look like this:


There are now four external ports:

fpga_0_clk_1_sys_CLK_N and P: The clock pin which will be driven by the FPGA.

fpga_0_rst_1_sys_rst_pin: The MicroBlaze reset line. This will be configured to a constant of 0 later (no reset).

proc_sys_reset_0_Dcm_locked_pin: This will be set to a constant of 1 later.

Clock generators outputs CLKOUT0 and LOCKED are not connected. This should be verified in the Graphical Design View.

In the System Assembly View, select Bus Interfaces. Right-click clock_generator_0 and delete the instance and all its connections. Now the clock generator has been removed, you can add an interrupt controller to the MicroBlaze core. From the IP Catalog, add AXI Interrupt Controller with the default

configuration.


Connect the interrupt controller: In the System Assembly View, select Bus Interfaces.

Connect axi_intc_0 INTERRUPT to microblaze_0 INTERRUPT.

Click the Ports tab. From the filter view, select Show ports: Interrupt Ports to display the interrupt ports.

Right-click the axi_intc_0 Intr port and make it external.

Edit the system.mhs file in XPS by selecting the Project tab:

Replace the line beginning with “PORT axi_intc_0_Intr_pin“ with: PORT axi_intc_0_Intr_pin = axi_intc_0_Intr, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING PORT axi_intc_1_Intr_pin = axi_intc_1_Intr, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING

In the section after “BEGIN axi_intc” replace the line “Port Intr” with PORT Intr = axi_intc_0_Intr & axi_intc_1_Intr

In the section after BEGIN MicroBlaze, add PORT INTERRUPT = microblaze_0_Interrupt

Save the file and click Reload.

The interrupt controller request line is now connected to the MicroBlaze. Two interrupt trigger lines (Intr) are external and can be used from outside to generate IRQs to the MicroBlaze. This should also be verified in the Graphical Design View. Verify that Interrupt Ports are enabled in the filter view beforehand. If any of the interrupt lines is set to 1, an IRQ is sent to the MicroBlaze. On the Ports page, the interrupt controller should now look like this:


You have completed the MicroBlaze configuration. The tool generated a file called system.xmp, which will be used later in the Simulink model. Before developing the software component for the MicroBlaze, the Simulink model must be constructed, since this will change the system.xmp file. It is therefore recommended to make a backup of the whole XPS directory now.


Constructing the Simulink FPGA Model for the DS2655

For the basics of constructing an FPGA interface, refer to the RTI FPGA Programming Blockset documentation. Construct a model according to the following diagram. This is the FPGA model without the MicroBlaze. The MicroBlaze will later be added as a EDK processor block. In MATLAB, change directory to <FPGAModelDir>

General information on shared memory blocks: Shared memories are dual-ported. One single shared memory interface between the MicroBlaze and the surrounding model is represented by two graphical blocks in the Simulink model. One is outside the EDK block and one is underneath the mask of the EDK block. The following diagram shows only the shared memory interfaces outside the EDK block. Both of them are potentially able to read and write, but the TO block is used only for writing to the MicroBlaze, and the FROM block only for reading from the MicroBlaze. The dout port of the TO shared memory is therefore connected to a terminator, since no output is expected from the MicroBlaze here. Likewise, the ports addr, din and we are set to zero, since the MicroBlaze will not expect any inputs from them. Xilinx does not support SLX as model format for the MicroBlaze flow.

You have to use the MDL format.


The different blocks must be configured as follows: FPGA Setup Framework: DS2655 with onboard I/O

Register In 1, Out 1, Out 2 Binary point: 0

Format: Unsigned

Group ID: 0

Convert Output type: Boolean

Delay Latency: 1

Since data is ready one cycle later, the enable port needs to be delayed.

The output of this block enables the subsequent shared memory TO for writing to the MicroBlaze later on.


Shared Memories TO and FROM Depth: 16

Ownership: Locally owned and initialized.

Access protection: Unprotected

Access mode: Read and write

Write mode: Read before write

Latency: 1

Memory access timeout: 0

Output type: Fixed point

Arithmetic type: Unsigned

Number of bits: 32

Binary point: 0

Constant 1, 2 Constant value 0. This is the address for the value written to the shared

memory.



Number of bits: 4

Binary point: 0

Sample period: 8e-9.

Constant 3 Constant value 0. This is the address for the value written to the shared

memory.



Number of bits: 32

Binary point: 0

Sample period: 8e-9

Constant 4,5 Constant value 0. This is the address for the value written to the shared

memory.

Output type: Boolean

Sample period: 8e-9


Now you can add the EDK processor block, which represents the MicroBlaze core. Open the Simulink Library Browser.

From the Xilinx Control Logic blockset, add EDK Processor to the model, resize it larger and double-click to open. Select the different tabs and configure as follows. You must click Apply after each modification.

Configure Processor for: HDL Netlisting

Select the system.xmp file created by XPS in the previous step.

Memory Map: Add all. This adds the previously defined shared memories to the MicroBlaze (visible when “look under mask” is done).

Expose the following ports: fpga_0_rst_1_sys_rst_pin, axi_intc_0_Intr_pin, axi_intc_1_Intr_pin

Disable Dual Clocks.

Disable Co-Debug and leave the Initial Program empty for the moment.

On the Basic page, click Sync and then click OK.

Create Constant 5, 6, 7 Constant values 0, 1 and 0 for 5, 6 and 7



Number of bits: 1

Binary point: 0

Sample period: 8e-9

Connect constant 5 to fpga_0_rst_1_sys_rst_pin no reset

Connect constant 6 to proc_sys_reset_0_Dcm_locked_pin

Connect constant 7 to axi_intc_0_Intr_pin (0 = no interrupt)

Connect Register In 1, Data New to axi_intc_1_Intr_pin (Interrupt request whenever there is new data)

The FPGA model is now complete. Place the FPGA model in a subsystem as follows: Select Edit – All. Right-click and select Create Subsystem.


You can now start the first part of the synthesis. Complete synthesis is not possible because no software component has been developed, but the result of partial synthesis, i.e., sysgen, is required to continue software development, especially the board support package. Open the subsystem.

Open the FPGA Setup block.

On the Parameters page, execute the FPGA build.


Constructing the Software Component In this section we will implement a software component for the system described above, using the Xilinx Software Development Kit (SDK). The program will contain one interrupt service routine, adding the number of calls of the interrupt service function modulo 1000 to the FPGA input multiplied by 1000. The last three decimal digits of the output run in a loop to show that the interrupts function. The other digits represent the original input, demonstrating how data is fed to the MicroBlaze. The program will also contain a main program which receives the FPGA input via shared memory and sends the result back to the FPGA. Create a new directory <FPGAModelDir>/SDK. Start Xilinx Software Development Kit. Create a new hardware platform specification: After starting SDK, close the welcome page.

Menu File: new: other: Xilinx, Hardware Platform Specification

Select a project name, e.g., “MB”.

Target hardware specification: <FPGAModelDir>/sysgen/SDK_Export/hw/system.xml

Now the SDK must be informed about the location of the software drivers provided by the XPS export. Menu Xilinx Tools: Repositories: New

<FPGAModelDir>\sysgen\SDK_Export\sysgen_repos

After the hardware platform specification has been generated, you can create a board support package together with an example application. The board support package contains some simple access functions for the shared memories and for the interrupt controller. Switch the “project build” configuration to release mode. Menu Project: Build Configurations: set active: Release. Create the sample application as follows: Menu File: New, Application Project

Choose a project name, e.g., MB_app.

Click Next.

Application template: Peripheral Tests

The example application has been created. To run it, you must replace the source code. In the project explorer, double-click the testperiph.c file in the MB_app/src folder. Replace the code by the following program. #include <stdio.h>


#include "xparameters.h"

#include "xil_cache.h"

#include "sg_axiiface.h"

#include "xintc.h"

volatile u32 * to_pt = (u32 *) XPAR_SG_AXIIFACE_0_MEMMAP_TO;

volatile u32 * from_pt = (u32 *) XPAR_SG_AXIIFACE_0_MEMMAP_FROM;

u32 counter = 0;

u32 int_counter = 0;

void fpga_int_handler(void * baseaddr_p)

{

int_counter = (int_counter + 1) % 1000;

}

int main()

{

xc_iface_t *iface;

// initialize the software driver, assuming the Pcore

// device ID is 0

XC_CfgInitialize(&iface, &SG_AXIIFACE_ConfigTable[0]);

microblaze_enable_interrupts();

// Register FPGA interrupt routine in the vector table of

// XIntC

XIntc_RegisterHandler(XPAR_AXI_INTC_0_BASEADDR,

XPAR_AXI_INTC_0_SYSTEM_AXI_INTC_0_INTR_PIN_0_INTR,

(XInterruptHandler) fpga_int_handler, (void *)0);

// Start the interrupt controller XIntC

XIntc_MasterEnable(XPAR_AXI_INTC_0_BASEADDR);

XIntc_EnableIntr (XPAR_AXI_INTC_0_BASEADDR,

XPAR_SYSTEM_AXI_INTC_0_INTR_PIN_0_MASK);

while (1)

{

counter = *to_pt * 1000 + int_counter;

*from_pt = counter;

}

return 0;

}

Save the file. The compilation is executed automatically. The application has been compiled to <FPGAModelDir>\SDK\MB_app\Release\MB_app.elf and is ready to use.


Open the EDK block in the FPGA Simulink model.

Select the software tab and browse to the ELF file.

Execute the FPGA build via the FPGA Setup block.

You have generated the FPGA bitstream and custom function code. In the MATLAB window, the location of the generated custom function files should look like this: “Custom function code created: ..\customio_5884EFFC941B08\”

The location will be needed later and referred to as <generated custio>.

Importing Software Projects

If you want to import SDK software projects into your current workspace, select File – Import – General – Existing Projects into Workspace.

Then select the rood directory of the project to be imported.


Constructing the Processor Interface with ConfigurationDesk

To download and run the design, you require a Simulink model for the computation node (CN) and an interface between the SCALEXIO Processing Unit model and the DS2655 FPGA model. For the DS2655, the interface is constructed with ConfigurationDesk, and the CN model is constructed with Simulink. Constructing the Simulink CN-model Open Simulink and construct a model according to this example. Use Model Port Blocks, Simulink Scope and Simulink Constant.

Save the model to <FPGAModelDir> as mb_CN.mdl. Constructing the ConfigurationDesk projects For details on constructing ConfigurationDesk projects, refer to the ConfigurationDesk Real-Time Implementation Guide. Create a subdirectory <FPGAModelDir>/CFD and choose it as the project

location.

Start ConfigurationDesk.

Register your system (SCALEXIO Processing Unit + DS2655).

Select File – Settings and define a location for your custom function files (<cfd_custiodir>).

Copy your custom function files from <generated custio> to <cfd_custiodir>.

Create a new project and an application.

In Add Model Topology, choose the CN model from above (MDL file).

In Add Hardware Topology, choose your registered SCALEXIO Processing Unit.

Leave the default values for other entries.


Add the custom function (your FPGA MicroBlaze model): On the Functions page, select Custom Functions – RTI – FPGA Programming Blockset – <your function name>.

Drag <your function name> to the main area.

On the Model page, right-click the model root node mb_CN

Select Create preconfigured application process.

Select all the ports underneath the root node and drag them to the main area. Connect the model ports to the custom function so that the result looks like this.

Right click the custom function block and assign the registered hardware. Hardware Assignment: Assign Channel Set: DS2655

Click Start Build.

The application should now build and download. To observe results, you need to create a ControlDesk project.

Creating the ControlDesk project Create a subdirectory <FPGAModelDir>/CDS and choose it as the project

location.

Create a new project via File –New –Project & Experiment.

In Add Platform, select your registered SCALEXIO Processing Unit.

In Select Variable Description, select the result generated by ConfigurationDesk above, for example: <FPGAModelDir>\CFD\Project\Application\Build Results\Application.sdf.

Create two displays for the In-Registers and a slider for the constant value (the input). Connect the model variables. The demo application uses some additional task information variables.


Click Go Online and observe the results.

Modify the numerical input with the slider and observe the difference.


Replacing and Restoring Software in the Bitstream If the software component was changed, there is no need to perform the whole FPGA synthesis process again. The FPGA bitstream can be updated with a new ELF file. The original bitstream is backed up and can be restored later, if desired. Updating the bitstream with a new ELF file First a modified software component has to be created. In Xilinx SDK, in the software component’s file testperiph.c, modify the

interrupt service function. Replace counter = *to_pt * 1000 + int_counter; by counter = (*to_pt + 2) * 1000 + int_counter;

Save the file. This automatically compiles and updates the ELF file.

Now the FPGA bitstream can be updated. It is contained in an INI file. After each complete FPGA build, a new INI file is created. The files are named subsystem_<some hex number>.ini. To provide unique file names, the hexadecimal number is different for each FPGA build. Identify the file name of your current build by looking into the INI file directory, e.g., subsystem_4A284D2DC61ADB.ini. The INI files are located in <FPGAModelDir>/<ModelName>_rtiFPGA/ini. The ELF file is located in <FPGAModelDir>/SDK/<ApplName>/Release. Go to the MATLAB prompt.

Enter rtifpga_scriptinterface('ReplaceElfFile', '<ini path>\ <your_inifile>.ini', '<elf path>\MB_app.elf', <cfd_custiodir>)

Where <ini path> and <elf path> are replaced by the specific current locations and <cfd_custiodir> is your ConfigurationDesk custom function directory as selected in section “Constructing the ConfigurationDesk Projects”.

Rebuild and download using ConfigurationDesk.

Observe the changed behavior in ControlDesk.

Restoring the original bitstream When a complete FPGA build is done, the bitstream containing the software component is backed up in the INI file. It can easily be restored: Go to the MATLAB prompt.


Enter rtifpga_scriptinterface('ReplaceElfFile', '<ini path>\ <your_inifile>.ini', ' , 'original'', <cfd_custiodir>), where <ini path> and <elf path> are replaced by the specific current locations. Note that the ELF-file name is ‘original’ here.

Rebuild and download using ConfigurationDesk.

Observe the changed behavior in ControlDesk.


Measured Delays From the software point of view, some delays were measured using a real-world model on the DS2655 FPGA Base Module. For other performance figures, refer to the Xilinx MicroBlaze Guide.

Operation Delay Data from model to MicroBlaze via shared memory 48 ns Data from model to MicroBlaze via shared memory 56 ns Interrupt from model to Microblaze 200 ns

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