microcontroller part 4

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Embedded System

PART 4 (Interrupt)ENG.KEROLES SHENOUDA

1



Interrupt

2


https://www.facebook.com/groups/embedded.system.KS/ https://www.facebook.com/groups/embedded.system.KS/

Interrupt definition in social life 3

Interrupt make you to stop what you are doing and jump to the one who request you

IRQInterrupt

request

youIRQ

you




What is an Interrupt?

An interrupt is a signal (an "interrupt request") generated by some event external to the CPU , which causes the CPU to stop what it is doing (stop executing the code it is currently running) and jump to a separate piece of code designed by the programmer to deal with the event which generated the interrupt request.

4

Task1Task2

Task3Execute each task sequential






5

Task1Task2

Task3 Irq (interrupt request)






6

Task1Task2

Task3

ISR () {…..} interrupt service routine






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Task1Task2

Task3Return to normal operation





8



Interrupt


This interrupt handling code is often called an ISR (interrupt service routine). When the ISR is finished, it returns to the code that was running prior to the interrupt

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Interrupt Service Routine

For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler.

When an interrupt occurs, the microcontroller runs the interrupt service routine.

For every interrupt, there is a fixed location in memory that holds the address of its interrupt service routine, ISR.

The table of memory locations set aside to hold the addresses of ISRs is called as

the Interrupt Vector Table.

10




11CPU

RAM

ROM

Interrupt Controller

UART

CAN

ADC

GPIO

Uart_TX

CAN_TX

Analog_ip

Registers

Controller MUX

Externalinterrupt

IRQ = specific NumberAccording to the SOC Specs

Irq number

D5Toggle Led

.txt(main.c/GPIO.c)

Stack/Heap/Data_Memory




12CPU


RAMROM

Timer

For Example

.text

Main ()




13


RAMROM

Timer

For Example

.text

Main ()

Main () {Timer(init);While (1){;}

}

PC

The PC “Program counter "register will Be indicate to while(1) code

And the CPU will execute the while(1) body forever




14


RAMROM

Timer

For Example

.text

Main ()


}

PC

Once the Counter inside Timer reached to the max and

Make overflow, the timer will generate irq” interrupt request”

To the Interrupt Controller

Irq Number 0




15


RAMROM

Timer

For Example

.text

Main ()


}

PC

The Interrupt Controller willDecide the (is this interrupt masked or not )and

check the priority then generate an interrupt request carry the interrupt Number to the CPU

and wait the ACK from the CPU

Irq number




16


RAMROM

Timer

For Example

.text

Main ()

PC

The CPU will reply by ACK to the Interrupt Controller, then will Jump the Specific Address

for interrupt service routing for Timer (ISR_Timer() prototype) according to(IVT

“Interrupt Vector Table”)on the ROM.

Irq number

This Address on the ROM in “Interrupt Vector” Section, it is a prototype which carry the address

of the definition in RAM.Interrupt Vector

.Interrupt Vector

PC ISR definition




17


RAMROM

Timer

For Example

.text

Main ()

PC

Irq number

Then the CPU will execute the ISR for Timer Overflow action

.Interrupt Vector

.text

PC

ISR definition




18


RAMROM

Timer

For Example

.text

Main ()


}

PC

After the CPU handling the Interrupt the CPU will come back to the last instruction




Interrupt Handling

Code executed by an interrupt is not generally considered part of the main

application. Since this code handles the cases where an interrupt occurs, it is

called an interrupt handler or an interrupt service routine.

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Servicing Interrupts

There are two general ways in which microcontrollers service interrupts, each

with several variations.

20

Vectored Arbitration System Non-Vectored Priority System




Vectored Arbitration System

Some machines reserve a portion of program memory for interrupt vectors.

The location of each particular vector in program memory may vary from

processor to processor but it cannot be changed by the programmer.

The programmer can only change the data at each vector location.

Each interrupt vector contains the address of that interrupt’s service routine.

When the compiler allocates program memory for interrupt handlers/ISR,

it places the appropriate address for the handler/ISR in the appropriate interrupt vector.

To help the compiler you must usually tell it where the interrupt vector for each interrupt is located in program memory

21

ROM

.Interrupt Vector




Non-Vectored Priority System

When an interrupt occurs, the PC branches to a specific address.

At this address the interrupts must be checked sequentially to determine which one has

caused the interrupt.

This scheme can be very slow and there can be a large delay between the time

the interrupt occurs and the time it is serviced. However, the programmer can

set the interrupt priority and non-vectored interrupts are feasible for

microcontrollers with less than five interrupts.

22




Interrupt vector Table

interrupt vector is the memory address of an interrupt handler.The interrupt vector for each interrupt provided by the microcontrollers Vendor and should be found inside its datasheet.

Please note here that the interrupt vectors are apart of the microcontroller's program memory. As such when utilizing interrupts this section of memory should be reserved to store pointers to interrupt handlers and not to store regular programs

The IVT Should contain those informations

23




IVT-Example interrupt vector Table on ATMEGA 32 24




IVT-Example interrupt vector Table National Semiconductor COP8SAA7 25




IVT-Example interrupt vector Table National Semiconductor COP8SAA726




27IVT-Example interrupt vector Table TiVaC “TM4C1234 SOC”




What is the Difference Between

Polling And Interrupt ?

30



Polling vs. Interrupt (example) Video

https://www.youtube.com/watch?v=M3nXI_86uLE

31



https://www.youtube.com/watch?v=M3nXI_86uLE


Polling vs. Interrupt

in interrupts, the input from I/O device can arrive at any moment requesting the CPU to

process it, in polling CPU keeps asking the I/O device whether it needs CPU

processing.

32




Polling33

Constantly reading a memory location, in order receive updates of an input value




Interrupt34




35Polling Vs. Interrupt

Polling Ties down the CPU

while (true)

{

if(PIND.2 == 0)

//do something;

}

Interrupt Efficient CPU use

Has priority

Can be masked

void main( )

{

Do your common task

}

ISR(){ whenever PIND.2 is 0 then do something}




Polling vs. InterruptBASIS FOR COMPARISON INTERRUPT POLLING

Basic Device notify CPU that it needs CPU attention.

CPU constantly checks device status whether it needs CPU's attention.

Mechanism An interrupt is a hardware mechanism. Polling is a Protocol.

Servicing Interrupt handler services the Device. CPU services the device.

Indication Interrupt-request line indicates that device needs servicing.

Comand-ready bit indicates the device needs servicing.

CPU CPU is disturbed only when a device needs servicing, which saves CPU cycles.

CPU has to wait and check whether a device needs servicing which wastes lots of CPU cycles.

Occurrence An interrupt can occur at any time. CPU polls the devices at regular interval.

Efficiency Interrupt becomes inefficient when devices keep on interrupting the CPU repeatedly.(Interrupt Overload)

Can be efficient if events arrive rapidly

Example Let the bell ring then open the door to check who has come.

Constantly keep on opening the door to check whether anybody has come.

36




Instruction Cycle with

Interrupts

37



Instruction Cycle with Interrupts38

interrupts have occurred, indicated by the

presence of an interrupt signal.

If no interrupts are pending,

the processor proceeds to the fetch cycle

and fetches the

next instruction of the program.

If an interrupt is pending, the processor

does Interrupt handling Sequence:




Instruction Cycle State Diagram,

with Interrupts

39




Steps taken in servicing an

interrupt1. The microcontroller completes the execution of the current instruction,

clears the interrupt status bit and stores the address of the next instruction that should have been executed (the content of the PC) on the stack.

2. The interrupt vector of the triggered interrupt is then loaded in the PC and the microcontroller starts execution from that point up until is reaches a RETI instruction.

3. Upon the execution of the RETI instruction the address that was stored on the stack in step 1 is reloaded in the PC .

4. The microcontroller then start executing instructions from that point. That is the point that it left off when the interrupt was triggered.

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Conclusion by hand writing 41




Interrupt ProcessingFULL DETAILS

42



Interrupt Processing1. The device issues an interrupt signal to the processor.

2. The processor finishes execution of the current instruction before respondingto the interrupt

3. The processor tests for an interrupt, determines that there is one, and sends an acknowledgment signal to the device that issued the interrupt. The acknowledgment allows the device to remove its interrupt signal.The processor now needs to prepare to transfer control to the interrupt routine. To begin, it needs to save information needed to resume the current program atthe point of interrupt. The minimum information required is (Switch Context)

(a) the status of the processor, which is contained in a register called the program status word (PSW), and

(b) (b) the location of the next instruction to be executed. These can be pushed onto the system control stack

43




Interrupt Processing

(4) The processor now loads the program counter with the entry location of the interrupt-handling program that will respond to this interrupt. Depending on the computer architecture and operating system design, there may be a single program;

one program for each type of interrupt; or one program for each device and each type of interrupt.

If there is more than one interrupt-handling routine, the

processor must determine which one to invoke. This information may have been included in the original interrupt signal, or the processor may have to issue a request to the device that issued the interrupt to get a response

that contains the needed information.

Once the program counter has been loaded, the processor proceeds to the

next instruction cycle, which begins with an instruction fetch.

44




Interrupt Processing

(5) When interrupt processing is complete, the saved register

values are retrieved from the stack and restored to the registers (Context restore)

(6) The final act is to restore the PSW and program counter values from

the stack. As a result, the next instruction to be executed will be from the previously interrupted program.

45




46

Switch Context Context Restore




What is interrupt

latency?

47



What is interrupt latency?

Interrupt latency refers primarily to the software interrupt handling latencies. In

other words, the amount of time that elapses from the time that an external interrupt arrives at the processor until the time that the interrupt processing begins.

One of the most important aspects of kernel real-time performance is the ability to service an interrupt request (IRQ) within a specified amount of time.

48

Interrupt Latency




Example on Atmga32EXTERNAL INTERRUPT

49



50CPU

RAM

ROM


UART

CAN

ADC

GPIO

Uart_TX

CAN_TX

Analog_ip

Registers

Controller MUX

Externalinterrupt


Irq number

(INT0) PD2




51CPU

RAM

ROM


UART

CAN

ADC

GPIO

Uart_TX

CAN_TX

Analog_ip

Registers

Controller MUX

Externalinterrupt


Irq number

(INT0) PD2

ACK




PA6 (ADC6)

AVCC

XTAL1

(OC1A) PD5

(SCK) PB7

(OC1B) PD4

RESET

VCC

GND

(TXD) PD1

(INT1) PD3

AGND

VCC

PA0 (ADC0)

PC7 (TOSC2)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA7 (ADC7)

PC4 (TDO)

PC3 (TMS)

PC6 (TOSC1)

PC5 (TDI)

PC0 (SCL)

PD7 (OC2)

PC2 (TCK)

PC1 (SDA)

ATmega32

PB0

PB1

(ICP) PD6

(INT2) PB2

(OC0/AIN0) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

1

2

3

4

5

6

7

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Steps in executing an interrupt

0000 0002 0002 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010

0012 0013 0014 0015 0016

Address Code

(INT0) PD2

SP

PC: 000D000E

0002

000F

(RXD) PD0

XTAL2

Stack

.INCLUDE "M32DEF.INC"

.ORG 0 ;location for resetJMP MAIN

.ORG 0x02 ;location for external INT0JMP EX0_ISR

MAIN: LDI R20,HIGH(RAMEND)OUT SPH,R20LDI R20,LOW(RAMEND)OUT SPL,R20SBI DDRC,3 ;PC.3 = outputSBI PORTD,2 ;pull-up activatedLDI R20,1<<INT0 ;Enable INT0OUT GICR,R20SEI ;Set I (Enable Interrupts)LDI R30, 3LDI R31, 4ADD R30, R31

HERE:JMP HERE

EX0_ISR:IN R21,PORTCLDI R22,0x08EOR R21,R22OUT PORTC,R21RETI

000C000B000A000900080007000600050000000400120013001400150000



PA6 (ADC6)

AVCC

XTAL1

(OC1A) PD5

(SCK) PB7

(OC1B) PD4

RESET

VCC

GND

(TXD) PD1

(INT1) PD3

AGND

VCC

PA0 (ADC0)

PC7 (TOSC2)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA7 (ADC7)

PC4 (TDO)

PC3 (TMS)

PC6 (TOSC1)

PC5 (TDI)

PC0 (SCL)

PD7 (OC2)

PC2 (TCK)

PC1 (SDA)

ATmega32

PB0

PB1

(ICP) PD6

(INT2) PB2

(OC0/AIN0) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

1

2

3

4

5

6

7

8

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0000 0002 0002 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010

0012 0013 0014 0015 0016

Address Code

(INT0) PD2

SP

PC: 000D000E

0002

000F

(RXD) PD0

XTAL2

Stack





HERE:JMP HERE


000C000B000A000900080007000600050000000400120013001400150004



PA6 (ADC6)

AVCC

XTAL1

(OC1A) PD5

(SCK) PB7

(OC1B) PD4

RESET

VCC

GND

(TXD) PD1

(INT1) PD3

AGND

VCC

PA0 (ADC0)

PC7 (TOSC2)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA7 (ADC7)

PC4 (TDO)

PC3 (TMS)

PC6 (TOSC1)

PC5 (TDI)

PC0 (SCL)

PD7 (OC2)

PC2 (TCK)

PC1 (SDA)

ATmega32

PB0

PB1

(ICP) PD6

(INT2) PB2

(OC0/AIN0) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

1

2

3

4

5

6

7

8

9

10

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0000 0002 0002 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010

0012 0013 0014 0015 0016

Address Code

(INT0) PD2

SP

PC: 000D000E

0002

000F

(RXD) PD0

XTAL2

Stack





HERE:JMP HERE


000C000B000A00090008000700060005000000040012001300140015000E

Until Reach

to 000E



PA6 (ADC6)

AVCC

XTAL1

(OC1A) PD5

(SCK) PB7

(OC1B) PD4

RESET

VCC

GND

(TXD) PD1

(INT1) PD3

AGND

VCC

PA0 (ADC0)

PC7 (TOSC2)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA7 (ADC7)

PC4 (TDO)

PC3 (TMS)

PC6 (TOSC1)

PC5 (TDI)

PC0 (SCL)

PD7 (OC2)

PC2 (TCK)

PC1 (SDA)

ATmega32

PB0

PB1

(ICP) PD6

(INT2) PB2

(OC0/AIN0) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

1

2

3

4

5

6

7

8

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0000 0002 0002 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010

0012 0013 0014 0015 0016

Address Code

(INT0) PD2

SP

PC: 000D000E

0002

000F

(RXD) PD0

XTAL2

Stack





HERE:JMP HERE


000C000B000A00090008000700060005000000040012001300140015000E

INT request 0 (IRQ0)



PA6 (ADC6)

AVCC

XTAL1

(OC1A) PD5

(SCK) PB7

(OC1B) PD4

RESET

VCC

GND

(TXD) PD1

(INT1) PD3

AGND

VCC

PA0 (ADC0)

PC7 (TOSC2)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA7 (ADC7)

PC4 (TDO)

PC3 (TMS)

PC6 (TOSC1)

PC5 (TDI)

PC0 (SCL)

PD7 (OC2)

PC2 (TCK)

PC1 (SDA)

ATmega32

PB0

PB1

(ICP) PD6

(INT2) PB2

(OC0/AIN0) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

1

2

3

4

5

6

7

8

9

10

11

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0000 0002 0002 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010

0012 0013 0014 0015 0016

Address Code

(INT0) PD2

SP

PC: 000D000E

0002

000F

(RXD) PD0

XTAL2

Stack





HERE:JMP HERE


000C000B000A000900080007000600050000000400120013001400150002

0F

00

Vector Address from IVT “Interrupt Vector

Table”



PA6 (ADC6)

AVCC

XTAL1

(OC1A) PD5

(SCK) PB7

(OC1B) PD4

RESET

VCC

GND

(TXD) PD1

(INT1) PD3

AGND

VCC

PA0 (ADC0)

PC7 (TOSC2)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA7 (ADC7)

PC4 (TDO)

PC3 (TMS)

PC6 (TOSC1)

PC5 (TDI)

PC0 (SCL)

PD7 (OC2)

PC2 (TCK)

PC1 (SDA)

ATmega32

PB0

PB1

(ICP) PD6

(INT2) PB2

(OC0/AIN0) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

1

2

3

4

5

6

7

8

9

10

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0000 0002 0002 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010

0012 0013 0014 0015 0016

Address Code

(INT0) PD2

SP

PC: 000D000E

0002

000F

(RXD) PD0

XTAL2

Stack





HERE:JMP HERE


000C000B000A000900080007000600050000000400120013001400150012

0F

00



PA6 (ADC6)

AVCC

XTAL1

(OC1A) PD5

(SCK) PB7

(OC1B) PD4

RESET

VCC

GND

(TXD) PD1

(INT1) PD3

AGND

VCC

PA0 (ADC0)

PC7 (TOSC2)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA7 (ADC7)

PC4 (TDO)

PC3 (TMS)

PC6 (TOSC1)

PC5 (TDI)

PC0 (SCL)

PD7 (OC2)

PC2 (TCK)

PC1 (SDA)

ATmega32

PB0

PB1

(ICP) PD6

(INT2) PB2

(OC0/AIN0) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

1

2

3

4

5

6

7

8

9

10

11

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13

14

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0000 0002 0002 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010

0012 0013 0014 0015 0016

Address Code

(INT0) PD2

SP

PC: 000D000E

0002

000F

(RXD) PD0

XTAL2

Stack





HERE:JMP HERE


000C000B000A000900080007000600050000000400120013001400150016

0F

00



PA6 (ADC6)

AVCC

XTAL1

(OC1A) PD5

(SCK) PB7

(OC1B) PD4

RESET

VCC

GND

(TXD) PD1

(INT1) PD3

AGND

VCC

PA0 (ADC0)

PC7 (TOSC2)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA7 (ADC7)

PC4 (TDO)

PC3 (TMS)

PC6 (TOSC1)

PC5 (TDI)

PC0 (SCL)

PD7 (OC2)

PC2 (TCK)

PC1 (SDA)

ATmega32

PB0

PB1

(ICP) PD6

(INT2) PB2

(OC0/AIN0) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

1

2

3

4

5

6

7

8

9

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0000 0002 0002 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010

0012 0013 0014 0015 0016

Address Code

(INT0) PD2

SP

PC: 000D000E

0002

000F

(RXD) PD0

XTAL2

Stack





HERE:JMP HERE


000C000B000A000900080007000600050000000400120013001400150016000F



PA6 (ADC6)

AVCC

XTAL1

(OC1A) PD5

(SCK) PB7

(OC1B) PD4

RESET

VCC

GND

(TXD) PD1

(INT1) PD3

AGND

VCC

PA0 (ADC0)

PC7 (TOSC2)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA7 (ADC7)

PC4 (TDO)

PC3 (TMS)

PC6 (TOSC1)

PC5 (TDI)

PC0 (SCL)

PD7 (OC2)

PC2 (TCK)

PC1 (SDA)

ATmega32

PB0

PB1

(ICP) PD6

(INT2) PB2

(OC0/AIN0) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

1

2

3

4

5

6

7

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0000 0002 0002 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010

0012 0013 0014 0015 0016

Address Code

(INT0) PD2

SP

PC: 000D000E

0002

000F

(RXD) PD0

XTAL2

Stack





HERE:JMP HERE


000C000B000A0009000800070006000500000004001200130014001500160010



CPU’s ‘fetch-execute’ cycle

61



CPU’s ‘fetch-execute’ cycle 62

Fetch instruction at IP

Advance IP to next instruction

Decode the fetched instruction

Execute the decoded instruction

Interrupt?

no

Save context

Get INTR ID

Lookup ISR

Execute ISR

yes IRET

User

Program

IP

ld

add

st

mul

ld

sub

bne

add

jmp

…




Sequential interrupt processing

VS

Nested interrupt processing

63



Sequential interrupt processing64




Nested interrupt processing65




Interrupt types

66



Types of Interrupts

Asynchronous / Interrupt Hardware

From external source, such as I/O device

Not related to instruction being executed

Synchronous (also called exceptions)

Processor-detected exceptions:

Faults — correctable; offending instruction is retried

Traps — often for debugging; instruction is not retried

Aborts — major error (hardware failure)

Programmed exceptions:

Requests for kernel intervention (software intr/syscalls)

67




Software Interrupt

A software interrupt is caused either by an exceptional condition or a special instruction in the instruction set which causes an interrupt when it is executed by the processor.

For example, if the processor's arithmetic logic unit runs a command to divide a number by zero, to cause a divide-by-zero exception, thus causing the computer to abandon the calculation or display an error message.

Software interrupt instructions work similar to subroutine calls.

68




Synchronous (also called

exceptions) Faults Instruction would be illegal to execute

Examples:

Writing to a memory segment marked ‘read-only’

Reading from an unavailable memory segment (on disk)

Detected before incrementing the PC

69




Traps

A CPU might have been programmed to automatically switch control to a ‘debugger’ program after it has executed an instruction

That type of situation is known as a ‘trap’

It is activated after incrementing the PC

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Error Exceptions

Most error exceptions — divide by zero, invalid operation, illegal memory reference, etc. — translate directly into signals

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Example Software Interrupt on

Linux Kernel for ‘exceptions” Can be invoked by Linux system-calls

Examples for exceptions Interrupt IDs:

0: divide-overflow fault

6: Undefined Opcode

7: Coprocessor Not Available

11: Segment-Not-Present fault

12: Stack fault

13: General Protection Exception

14: Page-Fault Exception

Linux has a pseudo-file system, /proc, for monitoring (and sometimes changing) kernel behavior

Run

cat /proc/interrupts

to see what’s going on

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$ cat /proc/interrupts

CPU0

0: 865119901 IO-APIC-edge timer

1: 4 IO-APIC-edge keyboard

2: 0 XT-PIC cascade

8: 1 IO-APIC-edge rtc

12: 20 IO-APIC-edge PS/2 Mouse

14: 6532494 IO-APIC-edge ide0

15: 34 IO-APIC-edge ide1

16: 0 IO-APIC-level usb-uhci

19: 0 IO-APIC-level usb-uhci

23: 0 IO-APIC-level ehci-hcd

32: 40 IO-APIC-level ioc0

33: 40 IO-APIC-level ioc1

48: 273306628 IO-APIC-level eth0

NMI: 0

ERR: 0

Columns: IRQ, count, interrupt controller, devices




Asynchronous / Interrupt

Hardware

I/O devices have (unique or shared) Interrupt Request Lines (IRQs)

IRQs are mapped by special hardware to interrupt vectors, and passed to the CPU

This hardware is called a Programmable Interrupt Controller (PIC)

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Hardware Interrupt

A hardware interrupt is an electronic alerting signal sent to the processor from an external device or internal Module, like a disk controller or an external peripheral. For example, when we press a key on the keyboard or move the mouse, they trigger hardware interrupts which cause the processor to read the keystroke or mouse position.

…..…...

…..

…...

Eternal signal can be configured

to be input (external interrupt)

Internal interrupts from Other Modules

Mange the interrupt Masking/priority And send it to the CPU

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Interrupt Controller IC

Responsible for telling the CPU when a specific external device wishes to ‘interrupt’

Needs to tell the CPU which one among several devices is the one needing service

IC translates IRQ to vector

Raises interrupt to CPU

Vector available in register

Waits for ack from CPU

Interrupts can have varying priorities

IC also needs to prioritize multiple requests

Possible to “mask” (disable) interrupts at IC or CPU

75

CPU


ACK IRQ Number

Registers

All Interrupt Signal from (all internal Modules Like UART, CAN, I2C ,etc…) Or from External Interrupt




How to make the Interrupt Reach to

the CPU ? For example

76




Examples On

Interrupt Controllers

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TivaC Cortex-M4

NVIC

“Nested Vectored

Interrupt Controller”

78

NVIC




TivaC-Cortex-M4 NVIC

“Nested Vectored Interrupt Controller”

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Interrupt Latency - Tail Chaining in

NVIC The Tiva C Series NVIC does exactly this. It takes only 12 cycles to PUSH and

POP the processor state. When the NVIC sees a pending ISR during the execution of the current one, it will “tail-chain” the execution using just 6 cycles to complete the process.

80




Cortex-M4® Exception Types81




Where is the vector for SysTick? What

is the standard name for this ISR?

82



SysTick is a Tiemer in ARM (Cortex-M) Family

The System Tick Time (SysTick) generates interrupt requests on a regular basis. This allows an OS to carry out context switching to support multiple tasking

For applications that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an interrupt source for tasks that need to be executed regularly.

83




84

Systick at address 0x003cIn IVT




__Vectors Section For TivaC 85

Systick in __Vector Sectionlocation where the ISR that handles the exception is

located. Vectors are stored in ROM

DCD is an assembler pseudo-op that defines a 32-bit

constant. ROM location 0x0000.0000 has the initial

stack pointer, and location 0x0000.0004 contains the

initial program counter, which is called the reset

vector





On Atmega32

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PROGRAM

ROM

PortsOSC

CPU

Timers

Other

Peripherals

Program

Bus Bus

RAM

I/O

PINS

EEPROM

Interrupt

Unit

SREG

GICR

TIMSK

CNVH ZSTSREG I

IVCE--INT2 IVSEL-INT0GICR INT1

TOIE0TOIE1OCIE1BTICIE1 OCIE0OCIE1ATOIE2TIMSK OCIE2

TOV0TOV1OCF1BICF1 OCF0OCF1ATOV2TIFR OCF2

40 PIN DIP

10

11

1

2

3

4

5

6

7

8

9

12

13

14

15

16

17

18

19

20

(XCK/T0) PB0

(T1) PB1

(INT2/AIN0) PB2

(OC0/AIN1) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

VCC

XTAL2

GND

XTAL1

(RXD) PD0

(TXD) PD1

(INT0) PD2

(INT1) PD3

(OC1B) PD4

(OC1A) PD5

(ICP) PD6

MEGA32

31

30

40

39

38

37

36

35

34

33

32

29

28

27

26

25

24

23

22

21

PA0 (ADC0)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA6 (ADC6)

PA7 (ADC7)

AREF

AGND

PC7 (TOSC2)

AVCC

PC6 (TOSC1)

PC5 (TDI)

PC4 (TDO)

PC3 (TMS)

PC2 (TCK)

PC1 (SDA)

PC0 (SCL)

PD7 (OC2)

87



Programming

External InterruptsATMEGA32

88



89



Edge trigger Vs. Level trigger in external

interruptsSM1 SM0SM2MCUCR SE ISC00ISC01ISC10ISC11

90




91



Edge trigger Vs. Level trigger (Cont.)

- JTRFMCUCSR JTD PORFEXTRFBORFWDRFISC2

92




93



94



95



Interrupt priority

Highest

priority

Lowest

priority

96




Conclusion by hand writingSimple task

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Interrupt Controller_LAB1

Write C Code using the 3 eternal interrupts External Interrupt 0 (INT0) - PD2. >> irq occur when “any logical change”External Interrupt 1 (INT1) - PD3. >> irq occur when “rising edge”External Interrupt 2 (INT2) - PB2. >> irq occur when “Falling edge”

We have also 3 leds (PD5,6,7) (led0,1,2).Each interrupt just make the led 0N for 1 secThe main function is always make all the leds off

98





For example

IRQ0 happen PC jump to ISR for IRQ0

LED 0 ON for 1secReturn to main and all LEDsBeing OFF

99





For example

Press on Bush BottonIRQ0 and still pressing

(rising edge)

The led0 is on For 1 sec

100





For example

The led0 is OFFAfter 1 sec

Still pressing on Push Button

101





For exampleReleased so IRQ0 happen

Again because (Falling edge)

And you already configured IRQ0 to happen if any logical change happen

The led0 is ONfor1 sec

102




Interrupt Controller_LAB1Solution

103




104




What is Interrupt

Overload?

105



What is Interrupt Overload?

Interrupt overload: Condition where external interrupts signaled frequently enough to cause other activities running on the processor to be starved

106




107

Predefined time




108




Hardware Interrupt Schedulate

This Solution maybe Founded in Advanced Interrupt Controller

109




Conclusion DEFINITIONS

110



DEFINITIONS

Interrupt - Hardware-supported asynchronous transfer of control to an

interrupt vector Interrupt Vector - Dedicated location in memory that specifies address execution jumps to

Interrupt Handler - Code that is reachable from an interrupt vector

Interrupt Controller - Peripheral device that manages interrupts for the processor

Pending - Firing condition met and noticed but interrupt handler has not began to execute

Interrupt Latency - Time from interrupt’s firing condition being met and start of execution of interrupt handler

Nested Interrupt - Occurs when one interrupt handler preempts another

111




References

http://techdifferences.com/difference-between-interrupt-and-polling-in-os.html

http://www.bogotobogo.com/Embedded/hardware_interrupt_software_interrupt_latency_irq_vs_fiq.php

Preventing Interrupt Overload Presented by Jiyong Park Seoul National University, Korea 2005. 2. 22. John Regehr, Usit Duogsaa, School of Computing, University.

First Steps Embedded Systems Byte Craft Limited reference

COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE EIGHTH EDITION William Stallings

Getting Started with the Tiva™ TM4C123G LaunchPad Workshop

112



http://techdifferences.com/difference-between-interrupt-and-polling-in-os.html

http://www.bogotobogo.com/Embedded/hardware_interrupt_software_interrupt_latency_irq_vs_fiq.php

http://slideplayer.com/slide/11250061/


References

Tiva™ TM4C123GH6PM Microcontroller DATA SHEET

Interrupts and Exceptions COMS W6998 Spring 2010

THE AVR MICROCONTROLLER. AND EMBEDDED SYSTEMS Using Assembly and C. Muhammad Ali Mazidi.

113




References

https://docs.google.com/viewer?a=v&pid=sites&srcid=ZmtlLnV0bS5teXxyaWR6dWFuLXMtd2Vic2l0ZXxneDo2ODU0NzlkM2JkOTg4MjRk

http://www.avrprojects.net/index.php/avr-projects/sensors/38-humidity-and-temperature-sensor-dht11?showall=&start=1

http://www.cse.wustl.edu/~lu/cse467s/slides/dsp.pdf

http://www.avr-tutorials.com/

Microprocessor: ATmega32 (SEE3223-10) http://ridzuan.fke.utm.my/microprocessor-atmega32-see3223-10

http://circuitdigest.com/article/what-is-the-difference-between-microprocessor-and-microcontroller

AVR Microcontroller and Embedded Systems: Using Assembly and C (Pearson Custom Electronics Technology) 1st Editionhttps://www.amazon.com/AVR-Microcontroller-Embedded-Systems-Electronics/dp/0138003319

114



https://docs.google.com/viewer?a=v&pid=sites&srcid=ZmtlLnV0bS5teXxyaWR6dWFuLXMtd2Vic2l0ZXxneDo2ODU0NzlkM2JkOTg4MjRk

http://www.avrprojects.net/index.php/avr-projects/sensors/38-humidity-and-temperature-sensor-dht11?showall=&start=1

http://www.cse.wustl.edu/~lu/cse467s/slides/dsp.pdf

http://www.avr-tutorials.com/

http://ridzuan.fke.utm.my/microprocessor-atmega32-see3223-10

http://circuitdigest.com/article/what-is-the-difference-between-microprocessor-and-microcontroller

https://www.amazon.com/AVR-Microcontroller-Embedded-Systems-Electronics/dp/0138003319


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microcontroller part 4

Engineering