microcontrollers - university of washington · 2012-10-02 · multiple interrupts with priority and...

Microcontrollersvs Microprocessors

CSE 466 Microcontrollers 2

Microprocessors

Arbitrary computations Arbitrary control structures Arbitrary data structures Specify function at high-level and use compilers and debuggers

Composed of three parts Data-path: data manipulation and storage Control: determines sequence of actions executed in data-path

and interactions to be had with environment Interface: signals seen by the environment of the processor

Instruction execution engine: fetch/execute cycle Flow of control determined by modifications to program counter Instruction classes:

Data: move, arithmetic and logical operations Control: branch, loop, subroutine call Interface: load, store from external memory


Microprocessor basics (cont’d)

Can implement arbitrary state machine with auxiliary data-path Control instructions implement state diagram Registers and ALUs act as data storage and manipulation Interaction with the environment through memory interface How are individual signal wires sensed and controlled?


Microprocessor organization

Controller Inputs: from ALU (conditions), instruction read from memory Outputs: select inputs for registers, ALU operations, read/write to memory

Data-path Register file to hold data Arithmetic logic unit to manipulate data Program counter (to implement relative jumps and increments)

Interface Data to/from memory (address and data registers in data path) Read/write signals to memory (from control)


General-purpose processor

Programmed by user New applications are developed routinely General-purpose

Must handle a wide range of applications

Interacts with environment through memory All devices communicate through memory data DMA operations between disk and I/O devices Dual-ported memory (e.g., display screen) Generally, oblivious to passage of time


Microcontrollers (uC) Executes a single program (or a limited suite) with few parameters Task-specific

Can be optimized for a specific application Interacts with environment in many ways

Direct sensing and control of signal wires Communication protocols to environment and other devices Real-time interactions and constraints Power-saving modes of operation to conserve battery power

Closer to “system on chip”…much more integrated in same die / package Processor core + co-processors + memory Flash for program memory, RAM for data memory, special registers to interface to

outside world ADC, sometimes DAC Parallel I/O ports to sense and control wires

PWM (a simple form of DAC) Timer units to measure time in various ways Communication subsystems to permit direct links to other devices Increasingly, will see radios, MEMS sensors, in package with uC


Microcontrollers (cont’d)

Other features not usually found ingeneral-purpose CPUs Expanded interrupt handling capabilities

Multiple interrupts with priority and selective enable/disable Automatic saving of context before handling interrupt Interrupt vectoring to quickly jump to handlers

More instructions for bit manipulations Support operations on bits (signal wires) rather than just words

Integrated memory and support functions for cheaper system cost Built-in Flash and RAM


CPU MemoryDisplay(with

dual-port video RAM)

DiskI/O

(serial line, keyboard,

mouse)

NetworkInterface

standard interfaces

system bus

all the parts around the processor are usually required

Typical general-purpose architecture

SoundInterface


Microcontroller(CPU+mem+…)

FlashSpecial

I/ODeviceDriver

RAM Custom Logic(now rare)

medium-speedinteractions

high-speedinteractions

low-speedinteractions

standard interfaceany of the parts around the microcontroller are optional

Typical task-specific architecture

GeneralPurpose

I/OA/D-D/A

Con-version

Timers


How does this change things?

Sense and control of environment Processor must be able to “read” and “write” individual wires Controls I/O interfaces directly

Measurement of time Many applications require precise spacing of events in time Reaction times to external stimuli may be constrained

Communication Protocols must be implemented by processor Integrate I/O device or emulate in software Capability of using external device when necessary


ControlFSM

16 16

Z

N

OP

16

ACREG

16loadpath

storepath

Data Memory(16-bit words)

16 16

OP

16

PCIR

16

data

addr

rd wr

Inst Memory(8-bit words)

data

addr

Block diagram of processor (Harvard) Register transfer view of Harvard architecture

Separate busses for instruction memory and data memory Example: PIC


16

Z

N

OP

8

ACREG16

16loadpath

storepath

Data Memory(16-bit words)

16

OP

16

PCIR

16

16

data

addr

rd wr

MARControl

FSM

Block diagram of processor (Princeton) Register transfer view of Princeton / von Neumann architecture

Single unified bus for instructions, data, and I/O Example: MSP430

Memory AddressRegister

The MSP430: Introduction

Microcontrollers 14

MSP430: An Introduction

The MSP430 family Technology Roadmap Typical Applications The MSP430 Documentation MSP430 Architecture MSP430 Devices MSP430 RISC core

CSE 466

Microcontrollers 15

The Family Broad family of TI’s 16-bit microcontrollers

from 1Kbytes ROM, 128 bytes RAM (approx. $1 ) to 256Kbytes ROM, 16Kbytes RAM ( $10)

Many subfamilies MSP430x1xx: Flash/ ROM based MCUs offer 1.8V to 3.6V

operation, up to 60kB, 8MIPs with Basic Clock. MSP430F2xx: 16 MHz. integrated on-chip oscillator,

internal pullup/pull-down resistors MSP430x4xx: 120kB/ Flash/ ROM 8MIPS with FLL + SVS,

integrated LCD controller MSP430x5xx: 25 MIPS, 1.8 to 3.6V, Power Management

Module for optimizing power consumption, 2x memory

CSE 466

Microcontrollers 16

Part numbering convention

CSE 466

F/C41xFx42x0

Fx42xF44x

Perf

orm

ance

Integration

FutureDevelopmentSamplingProduction

Device5xx-Next Gen• 25 MIPS• 32-256 KB • USB-RF

F21x1

2xx-Catalog• 16 MIPS• 1-120KB• 500nA Stand By

F13x-F14x

1xx-Catalog• 8 MIPS• 1-60KB

Fx43x

F20xx

F12xxF/C11xx

MSP430 Roadmap

F543x

F = FlashC = Custom ROM

4xx-LCD • 8/16 MIPS• 4-120KB• LCD Driver

F15x-F16x

F5xx RF

F21x2

F471x7

F23x-F24x

F5xx

F22xx

F261xF241x

CG461x

FG461x

F23x0

F563xUSB

F47x4

Microcontrollers 18

Handheld Measurement Air Flow measurement Alcohol meter Barometer Data loggers Emission/Gas analyser Humidity measurement Temperature

measurement Weight scales

Medical Instruments Blood pressure meter Blood sugar meter Breath measurement EKG system

Home environment Air conditioning Control unit Thermostat Boiler control Shutter control Irrigation system White goods

(Washing machine,..)

Misc Smart card reader Taxi meter Smart Batteries

Utility Metering Gas Meter Water Meter Heat Volume Counter Heat Cost Allocation Electricity Meter Meter reading system (RF)

Sports equipment Altimeter Bike computer Diving watches

Security Glass break sensors Door control Smoke/fire/gas detectors

MSP430 Typical Applications

CSE 466

MSP430 modes of operation


• Active mode (AM)– All clocks are active

• Low-power mode 0 (LPM0)– CPU is disabled– MCLK is disabled

• Low-power mode 1 (LPM1)– DCO's dc-generator is disabled if DCO not used in active mode

• Low-power mode 2 (LPM2)– SMCLK disabled– DCO's dc-generator remains enabled

• Low-power mode 3 (LPM3)– DCO's dc-generator is disabled

• Low-power mode 4 (LPM4)– ACLK is disabled– Crystal oscillator is stopped

Microcontrollers 20

MSP 430 Modular Architecture

CSE 466

JTAG Joint Test Action Group (originally created standard) Now IEEE1149.1 4 or 5 wire debugging / test interface MSP430 uses JTAG as primary development interface & for test

Writing Flash Debugger

JTAG: serial sequence of commands and responses Emulation tool translates ops from host into a sequence of JTAG commands


http://i.cmpnet.com/embedded//2009/0109_Jan%202009/0109esdTI01.gif

TAP: Test Access Port

Good article on JTAG & Spi-Bi-Wirehttp://www.embedded.com/design/prototyping-and-development/4008197/MCU-debug-on-a-pin-count-budget

Spy-Bi-Wire Goal: JTAG functionality with only 2 wires Re-use existing JTAG blocks “Serialized JTAG” SBWTIDO shared with reset pin /RST SBWTCK must be held low for a while to enable /RST


http://i.cmpnet.com/embedded//2009/0109_Jan%202009/0109esdTI03.gif

Embedded Emulation

Real-time in-system debug No application resources used Full speed execution H/W breakpoints Single stepping Complex triggering Trace capability

Easy to use tools Spy Bi-Wire

2-wire debug interface No pin function impact

JTAG

Embedded Emulation Module (EEM) MSP430 implements an embedded emulation module (EEM) accessed and

controlled through JTAG. In general (varies by MSP430 part #), the following features are available: Non−intrusive code execution with real−time breakpoint control Single step, step into and step over functionality Full support of all low-power modes Support for all system frequencies, for all clock sources Up to eight (device dependent) hardware triggers/breakpoints on memory address

bus (MAB) or memory data bus (MDB) Up to two (device dependent) hardware triggers/breakpoints on CPU register write

accesses …


USB Flash Emulation Tool (FET) MSP430 FET: real-time debug and programming tool Supports ALL MSP430 devices

4-wire JTAG 2-wire Spy Bi-Wire

Available with socketed target board Example: MSP-FET430U14 = FET Interface + 14-pin target board

Supported by all MSP430 IDEs

eZ430-F2013 Development Tool

Complete development tool that fits in your pocket Supports MSP430F20xx devices only

MSP430F20xx devices available in DIP

Unrestricted programming and debugging Fast, easy to use operation Includes IAR Kickstart IDE Supported by CCE V2 $20

Microcontrollers 27

Digital I/O

Independently programmable individual I/Os

• Up to 6 ports (P1 – P6)

• Each has 8 I/O pins

• Each pin can be configured as input or output

• P1 and P2 pins can be configured to assert an interrupt request

01234567

P1.

P6.

P2.

Input Register PxIN

Output Register PxOUT

Direction Register PxDIR

Interrupt Flag Register PxIFG

Interrupt Enable Register PxIE

Interrupt Edge Select Register PxIES

Function Select Register PxSEL

P3.

P5.

Port1Port2

Port3

Port6

yes yes

yes no

yes no

yes no

yesyes

yesyes

yesyes

P4.

…

CSE 466

Microcontrollers 28

Watchdog Timer

WDT module performs a controlled system restart after a software problem occurs

• Can serve as an interval timer (generates interrupts)

• WDT Control register is password protected

• Note: Powers-up active

CSE 466

Example 1: msp430x20x3_1.c// MSP430F20xx Demo - Software Toggle P1.0#include <msp430x20x3.h>void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timerP1DIR |= 0x01; // Set P1.0 to output direction

for (;;){

volatile unsigned int i;P1OUT ^= 0x01; // Toggle P1.0 using XORi = 50000; // Delaydo (i--);while (i != 0);

}}


WDTCTL:Watch Dog Timer ConTroL

WDTPW:WDT PassWord

WTDHOLD:WDT Hold

P1DIR:Port 1 DIRection

P1OUT:Port 1 OUTput state

Example 2: msp430x20x3P1_01.c// MSP430F20xx Demo - Software Poll P1.4, Set P1.0 if P1.4 = 1// Desc: Poll P1.4 in a loop, if hi P1.0 is set, if low, P1.0 reset.// ACLK = n/a, MCLK = SMCLK = default DCO#include <msp430x20x3.h>void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timerP1DIR |= 0x01; // Set P1.0 to output directionwhile (1) // Test P1.4{

if ((0x10 & P1IN)) P1OUT |= 0x01;// if P1.4 set, set P1.0else P1OUT &= ~0x01; // else reset

}}


Microcontrollers 31

MSP430 Memory Model

CSE 466

SFR: Special Function Registers

Not presentin F2013

Microcontrollers 32

Memory Organization

CSE 466

End of lecture


Recall from last time

Example 2: msp430x20x3P1_01.c// MSP430F20xx Demo - Software Poll P1.4, Set P1.0 if P1.4 = 1// Desc: Poll P1.4 in a loop, if hi P1.0 is set, if low, P1.0 reset.// ACLK = n/a, MCLK = SMCLK = default DCO#include <msp430x20x3.h>void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timerP1DIR |= 0x01; // Set P1.0 to output directionwhile (1) // Test P1.4{

if ((0x10 & P1IN)) P1OUT |= 0x01;// if P1.4 set, set P1.0else P1OUT &= ~0x01; // else reset

}}


Questions about example 2 Q: Why does (0x10 & P1IN) test P1.4? A: 0x10 is hexadecimal notation for 16:

0x10 = 1*161 + 0*160 = 16 (base 10)Converting hex to binary is easy, that’s why hex is useful in embedded systems: each hex digit maps straight onto 4 bits:

The 1 (high digit) becomes 0001The 0 (low digit) becomes 0000Concatenating, we get0x10 = 00010000b

In the binary representation, bit 4 (counting from 0) is highThis “mask” is how you select only pin 4 of port 1

Note: MSP430 header files define constants “BIT0”, “BIT1”, etc: BIT0 = 00000001b = 1 in base 10 BIT1 = 00000010b = 2 in base 10 BIT2 = 00000100b = 4 in base 10 etc


Question about example 2

Q: Why use this ORing notation P1OUT |= 0x01 to set the low bit of P1, instead of just P1OUT = 0x01?

A: By ORing the value in, we don’t modify any of the other bits of P1…there may be other pieces of code that want other bits of P1 to be in a certain state

Discuss: what’s the analogous technique to CLEAR a single bit, leaving the other bits unchanged?


Microcontrollers 37

MSP 430 Architecture: A Closer Look

CSE 466

F2013-specific peripherals Ports

P1 (8 bit port) and 2 bits of P2 Any pin can function as input or output, and generate an interrupt Individually programmable pull up & pull down resistors for each pin

Clock: the usual, plus VLO (Very Low frequency Oscillator) Timer_A2

Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

USI (MSP430F20x2 and MSP430F20x3) The universal serial interface (USI) module is used for serial data communication

and provides the basic hardware for synchronous communication protocols like SPI and I2C.

SD16_A (MSP430F20x3) The SD16_A module supports 16-bit analog-to-digital conversions. The module

implements a 16-bit sigma-delta core and reference generator. In addition to external analog inputs, internal VCC sense and temperature sensors are also available.CSE 466 Microcontrollers 38

Microcontrollers 39

Basic Clock System

Basic Clock Moduleprovides the clocks for the MSP430 devices

CSE 466 Subsystem Master CLocK

VLO (in MSP430F2xx):4-20kHz

Wake up time DCO frequency


DCO takes constant number of periods to wake up?

Timer_A

TASSEL---Timer A Source SELect SMCLK, ACLK, 2 external sources

ID --- Input divider /1 /2 /4 /8

MC---Mode Control Continuous Up Down Up/Down

TACLR --- Timer A CLeaR TAIE --- Timer A Interrupt Enable TAIFG --- Timer A Interrupt Flag


Timer_A


Also, Continuous mode (which requires a new Compare value to be set inISR)

Timer_A


TARTimer A Register

16 bit counterTASSELTimer A Source SELect

TAIFG Timer A Interrupt FlaG

raised when counter = 0

TACCRnTA Capture Compare Register

Capture: when event occurs, record TAR value in TACCR1

Compare: generate event when TAR=TACCR1

F2013 has “Timer_A2” 2 CCR channels

Circles: signals that can be made external

Microcontrollers 44

Timer_A

Timer_A is a 16-bit timer/counter with multiple capture/compare registers (2 in F2013)

• Capture external signals

• Compare PWM mode

CSE 466

Example 3: msp430x20x3_ta_01.c// MSP430F20xx Demo - Timer_A, Toggle P1.0, CCR0 Cont. Mode ISR, DCO SMCLK// Description: Toggle P1.0 using software and TA_0 ISR. Toggles every// 50000 SMCLK cycles. SMCLK provides clock source for TACLK.// During the TA_0 ISR, P1.0 is toggled and 50000 clock cycles are added to// CCR0. TA_0 ISR is triggered every 50000 cycles. CPU is normally off and// used only during TA_ISR.// ACLK = n/a, MCLK = SMCLK = TACLK = default DCO#include <msp430x20x3.h>void main(void){

WDTCTL = WDTPW + WDTHOLD; // Stop WDTP1DIR |= 0x01; // P1.0 outputCCTL0 = CCIE; // CCR0 interrupt enabledCCR0 = 50000;TACTL = TASSEL_2 + MC_2; // SMCLK, contmode_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt

}// Timer A0 interrupt service routine#pragma vector=TIMERA0_VECTOR__interrupt void Timer_A (void){

P1OUT ^= 0x01; // Toggle P1.0CCR0 += 50000; // Add Offset to CCR0

}


Microcontrollers 46

MSP430 CPU Introduction RISC architecture with 27 instructions and 7 addressing modes. Orthogonal architecture with every instruction usable with every

addressing mode. 16-bit address bus allows direct access and branching throughout

entire memory range; no paging 16-bit data bus allows direct manipulation of word-wide arguments. Constant generator provides six most used immediate values and

reduces code size. Direct memory-to-memory transfers without intermediate register

holding. Word and byte addressing and instruction formats. Compact silicon 30% smaller than an ‘8051 saves power and cost

CSE 466

Microcontrollers 47

MSP430 register properties

Large 16-bit register file eliminates single accumulator bottleneck, reduces fetches to memory.

Full register access including program counter, status registers, and stack pointer.

Single-cycle register operations.

CSE 466

Microcontrollers 48

MSP430 Registers

CSE 466

Microcontrollers 49

Registers: PC (R0)

Each instruction uses an even number of bytes (2, 4, or 6)

PC is word aligned (the LSB is 0)

Format:OP SRC, DST ; NB, a lot of processors use “DST,SRC”

MOV #LABEL,PC ; Branch to address LABELMOV LABEL,PC ; Branch to address contained in LABELMOV @R14,PC ; Branch indirect, indirect R14

CSE 466

Microcontrollers 50

Registers: SP (R1) Stack pointer for return addresses of subroutines and interrupts Stack is in general purpose RAM (unlike e.g. PIC) SP is word aligned (the LSB is 0)

Pushing a single byte on the stack wastes a byte…the byte at the “wasted” location is not modified by the push

Contrast with single-byte register operations, which zero the unused byte

SP points to most recently added word (not to next free word) Starts from top of memory (0x0280 in F2013) In assembly, you must initialize the SP yourself!

Don’t try to jump in to an initialization subroutine to set up the SP…if the SP is not set up before the subroutine call, you won’t return properly from the initialization subroutine!

CSE 466

Microcontrollers 51

Registers: SP (R1)

MOV 2(SP),R6 ; Item I2 –> R6MOV R7,0(SP) ; Overwrite TOS with R7PUSH #0123h ; Put 0123h onto TOSPOP R8 ; R8 = 0123h

CSE 466

TOS: “Top Of Stack”TOS is actually the lowest address in the stack!

Highest RAM address is 0x0280 in F2013

2(SP) means 2+SPExample stack manipulations:

Microcontrollers 52

Registers: SR (R2)

C: SR(0) Carry Z: SR(1) Zero N: SR(2) Negative (==msb of result) GIE: SR(3) Global interrupt enable CPUOff: SR(4) LPM control OSCOff: SR(5) LPM control SCG0: SR(6) System Clock Generator 0…LPM control SCG1: SR(7) System Clock Generator 0…LPM control V: SR(8) signed oVerflow

CSE 466

Example: msp430x20x3_1.asm.cdecls C,LIST, "msp430x20x3.h"

;------------------------------------------------------------------------------.text ; Progam Start

;------------------------------------------------------------------------------RESET mov.w #0280h,SP ; Initialize stackpointerStopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDTSetupP1 bis.b #001h,&P1DIR ; P1.0 output

;Mainloop xor.b #001h,&P1OUT ; Toggle P1.0Wait mov.w #50000,R15 ; Delay to R15L1 dec.w R15 ; Decrement R15

jnz L1 ; Delay over?jmp Mainloop ; Again

;;------------------------------------------------------------------------------; Interrupt Vectors;------------------------------------------------------------------------------

.sect ".reset" ; MSP430 RESET Vector

.short RESET ;

.end


Microcontrollers 54

Status bits

CSE 466

NB: in MSP430, mov operations do not affect status register

Demo interlude, including debugger!


End of lecture


CPE/EE 421/521 Microcomputers 57

Constant Generators

As – source register addressing mode in the instruction word

Constant generator examples

Address Assembled instr Viewed in debugger ; Original user’s asm code 0xF81C: 434F CLR.B R15 ; mov.b #0,R150xF81E: 435F MOV.B #1,R15 ; mov.b #1,R150xF820: 436F MOV.B #2,R15 ; mov.b #2,R150xF822: 407F 0003 MOV.B #0x0003,R15 ; mov.b #3,R150xF826: 426F MOV.B #4,R15 ; mov.b #4,R150xF828: 407F 0080 MOV.B #0x0080,R15 ; mov.b #80h,R150xF82C: 407F 007F MOV.B #0x007f,R15 ; mov.b #7Fh,R150xF830: 430F CLR.W R15 ; mov.w #0,R150xF832: 431F MOV.W #1,R15 ; mov.w #1,R150xF834: 432F MOV.W #2,R15 ; mov.w #2,R150xF836: 403F 0003 MOV.W #0x0003,R15 ; mov.w #3,R150xF83A: 422F MOV.W #4,R15 ; mov.w #4,R150xF83C: 403F 0080 MOV.W #0x0080,R15 ; mov.w #80h,R150xF840: 433F MOV.W #-1,R15 ; mov.w #0xFFFF,R15


Move operations that can use the constant generator assemble to 1 wordMove operations that cannot use the constant generator assemble to 2 words

Microcontrollers 59

CISC / RISC Instruction Set

CSE 466

Good summary of MSP430 instructions: http://cnx.org/content/m23503/latest/

Microcontrollers 60

27 Core RISC Instructions

CSE 466

Notes:- .b or .w: byte or word- add / addc: without/with carry- dadd: decimal add w/ carry (bin. coded decimal math)swpb: swap bytessxt: sign extend (copies sign bit from b7 to b15-b8…for converting signed byte into signed word)

rra: Roll rightrrc: Roll right, through carry

Microcontrollers 61

Emulated Instructions

CSE 466

Microcontrollers 62

51 Total Instructions

CSE 466

Example 2: msp430x20x3_P1_01.asm;*******************************************************************************.cdecls C,LIST, "msp430x20x3.h"

;------------------------------------------------------------------------------.text ; Program Start

;------------------------------------------------------------------------------RESET mov.w #0280h,SP ; Initialize stackpointerStopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDTSetupP1 bis.b #001h,&P1DIR ; P1.0 outputMainloop bit.b #010h,&P1IN ; P1.4 hi/low?

jc ON ; jmp--> P1.4 is set;

OFF bic.b #001h,&P1OUT ; P1.0 = 0 / LED OFFjmp Mainloop ;

ON bis.b #001h,&P1OUT ; P1.0 = 1 / LED ONjmp Mainloop ;

;;------------------------------------------------------------------------------; Interrupt Vectors;------------------------------------------------------------------------------

.sect ".reset" ; MSP430 RESET Vector

.short RESET ;

.end


Microcontrollers 64

Double operand instructions

CSE 466

Microcontrollers 65

Single Operand Instruction

CSE 466

Microcontrollers 66

Jump Instructions

CSE 466

Microcontrollers 67

3 Instruction Formats

CSE 466

Microcontrollers 68

Addressing Modes

CSE 466

Microcontrollers 69

Register Addressing Mode

CSE 466

Microcontrollers 70

Register-Indexed Addressing Mode

CSE 466

Useful for implementing arrays…above, 100h is the base address of the source array, and the contents of R4 are the index of the source array.

Difference between C and MSP430 assembly: in assembly bytes are indexed, even if we’re dealing with an array of words of larger…in C, the index counts the items, whatever size they are

Microcontrollers 71

Symbolic Addressing Mode

CSE 466

Could also be called “PC relative”Gives a relative addressing scheme that can be used to create position-independent code. Less useful in flash-based systems than RAM-based(since moving code is very costly in time and energy for flash).

mov.w LoopCtr, R6 ; load word LoopCtr into R6, symbolic mode becomes mov.w X(PC),R6 ; load word LoopCtr into R6, symbolic modeWhere X = LoopCtr – PC --- calc done by assembler

Microcontrollers 72

Absolute Addressing Mode

CSE 466

mov.b &P1IN,R6 ; load byte P1IN into R6, abs mode becomes mov.b P1IN(SR),R6 ; load byte P1IN into R6, abs mode

SR returns 0 in this case…a kind of constant generator fn

SP-relative

Not claimed as an addressing mode by TI…some other manufacturers call this a distinct addressing mode


mov.w 2(SP),R6 ; most recent word but one from stack

Microcontrollers 74

Register Indirect Addressing Mode

CSE 466

Memory at addr held inR4 is moved into R5

This mode can’t be used for destination addresses, only sourceInstead, need to use indexed addressing for destination:

Microcontrollers 75

Register Indirect Autoincrement Addressing Mode

CSE 466

Inverse operation:mov.w R6,0(R5) ; store word from R6 into addr 0+(R5)=4incd.w R5 ; R5 += 2

Microcontrollers 76

Immediate Addressing Mode

CSE 466

Equivalent tomov.w @PC+,R6 ; load immediate word 1234h into R6DW 1234h ;

MSP430 example peripherals


Microcontrollers 78

Comparator_A (see also Comparator_A+)

Comparator_A is an analog voltage comparator

• Compares analog input voltage to a reference voltage

• Useful for slope analog-to-digital conversions

• Supply voltage supervision, and

• Monitoring of external analog signals.

CSE 466

SAR ADCs


http://www.maximintegrated.com/app-notes/index.mvp/id/1080

ADC10 10 bit ADC SAR (Successive Approximation Register) Fast ~200k samples per sec (ksps) Binary chopping


Microcontrollers 81

ADC12

High-performance 12-bit analog-to-digital converter

• More than 200 Ksamples/sec

• Programmable sample &hold

• 8 external input channels

• Internal storage

CSE 466

Sigma-Delta ADC


SD16_A Sigma-Delta ADC 16 bits of precision Slow Example application: metering


Microcontrollers 84

USART Serial Port

The universal synchronous/ asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module

• UART or SPI (Synchronous Peripheral Interface) modes

• Double-buffered

• Baud-rate generator

CSE 466

USI module

8 or 16 bit shift register that can output data streams HW to ease I2C or SPI communication 3 wire SPI mode support I2C mode support Slave operation in LPM4…no internal clock required


End of lecture


microcontrollers - university of washington · 2012-10-02 · multiple interrupts with priority and...

Documents