microelectronic processes

7/31/2019 Microelectronic Processes

1/39

Preetha Sreekumar Manipal Dubai


2/39


Semiconductor Manufacturing Processes

Design Wafer Preparation

Front-end Processes

Photolithography

Etch

Cleaning

Thin Films

Ion Implantation

Planarization

Test and Assembly

Thin Films

Photo-

lithography

Cleaning

Front-EndProcesses

EtchIon

Implantation

Planarization

Test &Assembly

DesignWafer

Preparation


3/39

Design


Establish Design Rules

Circuit Element Design

Interconnect Routing

Device Simulation

Pattern Preparation

The first operation is the design of the chip. When tens of millions oftransistors are to be built on a square of silicon about the size of a childsfingernail, the placing and interconnections of the transistors must bemeticulously worked out. Each transistor must be designed for its intendedfunction, and groups of transistors are combined to create circuit elementssuch as inverters, adders and decoders. The designer must also take into

account the intended purpose of the chip. A processor chip carries outinstructions in a computer, and a memory chip stores data. The two typesof chips differ somewhat in structure. Because of the complexity oftodayschips, the design work is done by computer, although engineers often printout an enlarged diagram of a chips structure to examine it in detail.


4/39

Wafer Preparation

Polysilicon Refining

Crystal Pulling

Wafer Slicing & Polishing Epitaxial Silicon Deposition


Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIon

Implantation

Planarization

Test &Assembly

DesignWafer

Preparation


5/39

Wafer Preparation

The base material for building an integrated circuit is asilicon crystal. Silicon, the second most abundant elementon the earth after oxygen, is the principal ingredient ofbeach sand. Silicon is a natural semiconductor, whichmeans that it can be altered to be either an insulator orconductor.

To make wafers from sand, the silicon must be refined andpurified. The refined silicon is melted, trace amounts of

impurities are added, then crystallized to form boules.Silicon boules are sliced into wafers and polished. A layerof epitaxial silicon (epi) is then deposited onto the polishedsilicon wafers.



6/39


Chemical Reactions Silicon Refining: SiO2 + 2 C Si + 2 CO

Silicon Purification: Si + 3 HCl HSiCl3 + H2

Silicon Deposition: HSiCl3 + H2 Si + 3 HCl



7/39


To make a silicon wafer, raw silicon is refined from quartz rockby reacting it with carbon to form small, randomly oriented

crystals of pure silicon, called polysilicon. Raw silicon is reacted with hydrochloric acid to form

trichlorsilane or TCS. TCS is mixed with hydrogen gas in areaction furnace to form polycrystalline silicon which is allowedto grow on the surface of heated tantalum wicks.

The polycrystalline silicon is refined by dissolving the tantalumwicks in hydrofluoric acid and fused to produce polysiliconingots.

Because polycrystalline silicon, also known as polysilicon, hasrandomly oriented crystals, it does not have the electrical

characteristics necessary to fabricate semiconductor devices.Polysilicon must first be transformed into single crystal siliconusing a process called Crystal Pulling.



8/39

Crystal Pulling

Process Conditions

Flow Rate: 20 to 50 liters/min

Time: 18 to 24 hours

Temperature: >1,300 degrees C

Pressure: 20 Torr


Quartz Tube

Rotating Chuck

Seed Crystal

Growing Crystal(boule)

RF or ResistanceHeating Coils

Molten Silicon(Melt)

Crucible


9/39

Silicon Crystal Growing The most commonly used technique for silicon crystal growing is the

Czochralski process where a silicon seed is slowly drawn from a crucible ofmolten silicon to produce a cylindrical ingot 100 to 300 mm in diameter and

up to a meter in length. Crushed, high-purity polycrystalline silicon is dopedwith elements like arsenic, boron, phosphorous or antimony and melted at atemperature greater than 1300 C in a quartz crucible surrounded by an inertgas atmosphere of high-purity argon. The melt is cooled to a precisetemperature, then a seed of single crystal silicon is placed into the melt andslowly rotated as it is pulled out. The surface tension between the seed and

the molten silicon causes a small amount of the liquid to rise with the seedand cool into a single crystalline ingot with the same orientation as the seed.The ingot diameter is determined by controlling temperature and extractionspeed. To minimize contamination of the silicon, the process takes place in aninert gas atmosphere at a pressure of 20 Torr.

Crystal pullers are installed on large concrete foundations (sometimes aslarge as an 8 foot cube) to control vibration, allow proper crystal orientation,

and prevent defects. Most ingots produced today are 200mm (8") in diameter, but silicon

suppliers are switching to ingots that are 300mm (12") in diameter.



10/39

Wafer Slicing & Polishing


silicon wafer

p+ silicon substrate


11/39

Wafer Slicing & Polishing

Ingot Characterization

Single crystal silicon ingots are characterized by theorientation of their silicon crystals. Before the ingot is cut intowafers, the orientation of the crystal is marked by grinding aflat or notch along the silicon ingot.

Wafer Slicing

After characterization, wafer manufacturers slice the ingotinto individual wafers with a precision thin-bladed sawdesigned to minimize waste (called kerf) but rigid enough tocut flatly.

Wafer Polishing

Wafers are typically polished to a high degree of flatnesson one side. However, 300 mm wafers may be polished onboth sides to improve photolithography resolution.



12/39

Sorenson

12

Epitaxial Silicon Deposition

GasInput Lamp

Module

Quartz

Lamps

Wafers

Susceptor

Exhaust

Chemical Reactions

Silicon Deposition: HSiCl3 + H2 Si + 3 HClProcess Conditions

Flow Rates: 5 to 50 liters/min

Temperature: 900 to 1,100 degrees C.

Pressure: 100 Torr to Atmospheric

silicon wafer

p- silicon epi layer



13/39

Epitaxial growth


Epitaxial Growth is the deposition of a layer on a substrate which matches thecrystalline order of the substrate

Homoepitaxy - Growth of a layer of the same material as the substrate eg. Sion Si

Heteroepitaxy - Growth of a layer of a different material than the substrateeg. GaAs on Si

Epitaxial growth is useful for applications that place stringent demands on a

deposited layer:

High purity

Low defect density

Abrupt interfaces

Controlled doping profiles High repeatability and uniformity

Safe, efficient operation


14/39

Epitaxial Silicon Deposition

Silicon manufacturers use a process called epitaxial silicon growth togrow a layer of single crystal silicon from vapor onto a single crystalsilicon substrate at high temperatures.

EPI layers are important for assuring device isolation and avoidingjunction leakage in CMOS devices. The technology is moving frombatch to single wafer processing in order to provide better process

control and to achieve lower cost of ownership. The epitaxialdeposition uses a chlorinated silane reacting with hydrogen attemperatures of 900 to 1100 C. Among the challenges in thetechnology is lowering the deposition temperature to below 900 Cfor defect reduction. This will require reducing contaminants, such asmoisture or oxygen, in the reactor and finding new chemistries to

increase the deposition rate. In the future more wafers will have an epitaxy layer to improve silicon

performance. Starting at 0.18 m, DRAM manufacturers are likely touse epitaxy. This will roughly double the percentage of wafersprocessed with epitaxy.



15/39

General Scheme Epitaxial Growth


16/39

Front end ProcessesFront-End Processes

The Front-End of the line, often referred to as FEOL, describes the processes used to

fabricate device structures from the starting silicon material through theconstruction of complete transistor structures. Thermal oxidation, silicon nitridedeposition, polysilicon deposition and annealing operations are included in thefront-end of the line processes.

Thermal Oxidation

The thermal oxidation of silicon uses oxygen in high temperature furnaces at

atmospheric pressures. Furnace temperatures are in excess of 1,100 C and theprocess can take as log as 24 hours for thick oxides.

Polysilicon Deposition

Performed in Low Pressure (LP) CVD reactors, amorphous and poly silicon arethermally deposited from silane. The technology has migrated from horizontalfurnaces to vertical furnaces to provide improved film uniformity, reduceparticulate contamination, and improve grain structure uniformity, leading to better

consistency in etch and conductance.Silicon Nitride Deposition

Silicon nitride is deposited in LPCVD furnaces similar to those used for polysilicondeposition.



17/39

Front-End Processes

Thermal Oxidation Silicon dioxide alloyed with phosphorus pentoxide ("P-

glass") can be used to smooth out uneven surfaces

Silicon Nitride Deposition Low Pressure Chemical Vapor Deposition (LPCVD) Silicon

nitride is often used as an insulator and chemical barrier inmanufacturing ICs

Polysilicon Deposition Low Pressure Chemical Vapor Deposition (LPCVD)

used for improved film uniformity

Annealing


18/39

Sorenson

18

Front-End Processes

* High proportion of the total product use

Polysilicon

H2N2

SiH4*AsH3

B2H6

PH3

Exhaust ViaVacuum Pumpsand Scrubber

3 ZoneTemperatureControl

Gas Inlet

Vertical LPCVD Furnace

Quartz TubeChemical Reactions

Thermal Oxidation: Si + O2 SiO2

Nitride Deposition: 3 SiH4 + 4 NH3 Si3N4 + 12 H2

Polysilicon Deposition: SiH4 Si + 2 H2Process Conditions (Silicon Nitride LPCVD)

Flow Rates: 10 - 300 sccm

Temperature: 600 degrees C.

Pressure: 100 mTorr

silicon dioxide (oxide)

p- silicon epi layer


Nitride

NH3 *H2SiCl2 *

N2

SiH4 *

SiCl4

Oxidation

ArN2H2O

Cl2

H2

HCl *

O2 *Dichloroethene *

Annealing

ArHe

H2N2


19/39

Photolithography

Historically, lithography is a type of printingtechnology that is based on the chemicalrepellence of oil and water.

Photo-litho-graphy: latin: light-stone-writingSteps involved

Spin on the photoresist to the surface of the wafer

Produces a thin uniform layer of photoresist on the wafer surface.

Expose to UV light

Wash with developer solution



20/39

Photoresist

Photoresist is an organic polymer which

changes its chemical structure when exposed to

ultraviolet light.

It contains a light-sensitive substance whoseproperties allow image transfer onto a printed

circuit board.

There are two types of photoresist: positive andnegative



21/39

Photoresist Coating Process


Photoresist or resist is a photo-sensitive material

applied to the wafer in a liquid state in smallquantities. The wafer is spun at 3000 rpm which

spreads the puddle into a uniform layer

typically around 2 m thick.

Most semiconductor processes today use a

positive resist where exposed portions are

removed leaving a positive image of the mask

pattern on the surface of the wafer.

Photoresists are specially formulated to trade-

off sensitivity to short-wavelength light and

chemical erosion resistance during etch

processes. Photoresists must also have very lowmetal content.

There are many specialty chemicals used in the photolithography process including materials

that promote adhesion of the photoresist to the silicon surface, materials that remove the bead

of photoresist that forms at the edge of the wafer during spin application and materials that

enhance the photosensitivity of the resist, inhibit corrosion, or thin the photoresist.


22/39

Photolithography

Exposure to UV light

makes it more soluble

in the developer

Exposed resist iswashed away by

developer so that the

unexposed substrate

remains

Results in an exactcopy of the original

design

Exposure to UV light

causes the resist to

polymerize, and thus

be more difficult to

dissolve

Developer removes the

unexposed resist

This is like a

photographic negativeof the pattern


23/39

Mask Alignment and Exposure

Photomask is a square glass plate with a

patterned emulsion of metal film on one side

After alignment, the photoresist is exposed to

UV light Three primary exposure methods: contact,

proximity, and projection



24/39

Exposure Methods



25/39

Exposure Processes


The image of the chip is projected through a mask and exposes a

photo-active emulsion. Semiconductor device manufacturersexpose wafers using a tool called a stepper. A stepper exposes a

photoresist coated wafer to single wavelength UV light passing

through a reticle which contains the image of a single device layer.

The term stepper comes from the step-and-repeat action of

moving the wafer on its x and y axes to align the reticle with eachindividual device position.

UV light is used because modern semiconductor device features

are so small that the actual wavelength of the exposing light is a

limiting factor. Steppers are extremely high-precision devices andcan cost upwards of $5 million each and are very sensitive to

vibration and temperature variation. A typical stepper will print a

single process layer on about 12 wafers per hour.


26/39

Ion Implantation Ion Implantation is different from other semiconductor

processes because it does not create a new layer on thewafer. Instead, ion implantation changes the electricalcharacteristics of precise areas within an existing layer on thewafer.

A process in which energetic, charged atoms or molecules aredirectly introduced into a substrate.

Acceleration energies range between 10-200 KeV. (Today alsoup to several MeV)

Primarily used to add dopant ions into the surface of siliconwafers.

Goal : to introduce a desired atomic species, with a specifiedquantity (dose), into the required depth, with lateral

selectivity.


27/39

Advantages of ion implantation


28/39

Ion Implantation - Overview

-Initially, doping was performed in a manner similar to thin film deposition via CVD,

-This approach was soon found to lack the flexibility and control required by CMOS processing,

Ion implantation quickly gained popularity for the introduction of dopant atoms.

-Modern ion implanters were originally developed from

particle accelerator technology,

-Their energy range spans 100eV to several MeV ( a few

nms to several microns in depth range),

-The implantation is always followed by a thermal

activation (600-1100oC).

0-200keV

Plasma

Source

Gas

AnalyzingMagnet Wafer

RelativeBeamScan


29/39

Ion implantation- Equipment - II

Schematic diagram of an ion implantation system.


30/39

Playing billiards with atoms and electrons

Ion impact leads to cascades of

recoil atoms and electrons

Atomic cascades act as a nano-blender changing crystal structureand mixing atoms

Electron cascades cause chemicalchanges (radiolysis)

Foreign ion comes to rest undersurface of materialionimplantation doping. Changes

chemical and electronic behaviour


31/39


32/39

Etching



33/39


The semiconductor industry typically employs a technique called

plasma etching to precisely transfer micro-images printed in

photoresist into semiconductor process films. This is done by

placing wafers into a vacuum chamber which is filled with anetch gas. A strong Radio Frequency or RF electromagnetic field

is applied to the wafer. The RF field tears the molecules of etch

gas apart into chemically reactive ions. The charged ions are

accelerated toward the wafer surface by the electromagnetic field

and form a microscopic chemical and physical sandblasting

action which removes the exposed material.

Plasma etching selectively removes portions of semiconductor

layers to leave microstructures on a device. The process must

precisely eliminate the material left exposed by the photoresistpattern and avoid undercutting the sides of the remaining circuit

elements.


34/39

Cluster Tool for Etching


EtchChambers

Cluster ToolConfiguration

TransferChamber

Loadlock

Wafers

RIE Chamber

TransferChamber

Gas Inlet

Exhaust

RF Power

Wafer


35/39

Cleaning

Thin Films

Photo-lithography

Cleaning

Front-EndProcesses

EtchIon

Implantation

Planarization

Test &Assembly

DesignWafer

Preparation

Critical Cleaning

Photoresist Strips

Pre-DepositionCleans

Cleaning


36/39

CleaningIn semiconductor processes, everything starts with a clean.The term cleaning is somewhat a misnomer. Experts in thisfield usually refer to this process as wafer surfacepreparation because wafers are not just cleaned but havetheir surfaces left in a precise chemical state that allows thenext process step to be properly performed.

There are three major types of cleans used: Critical cleans,photoresist strips, and pre-deposition cleans.

Critical cleans are done for front-end processes and use strongacids (before metalization layers, which are sensitive to aciddamage, are present). Photoresist strips are also done withstrong acids during the front-end processes but must be donewith solvents after the metalization process steps. Pre-deposition cleans are also done with solvents, however theseprocesses are shifting to dry cleaning technologies.



37/39

Planarization

Oxide Planarization

Metal Planarization

This process enables multiple layers of

semiconductor metallization to be deposited,

allowing denser interconnection layers.


Ch i l M h i l Pl i ti


38/39

Chemical Mechanical Planarization

(CMP)

Oxide Planarization

Chemical Mechanical Polish (CMP) provides planarity forthe oxide dielectric used at the metallization level.Advanced development is in the area of copper and

aluminum planarization. The chemistry of the slurry, thenature of the pad, and the mechanics of the tool are allcritical to achieving global planarization over a 300 mmwafer.

Metal PlanarizationChemical Mechanical Polish (CMP) provides planarity forthe tungsten plug used at the metallization level.



39/39

Test and Assembly

Test & Assembly

Test and assembly operation are performed out

of the cleanroom wafer fab. In these

operations, chips are tested, put into packages,

then retested.

P th S k M i l D b i

microelectronic processes

Documents