microelectronics & vlsi at iit bombay: academic programmes

Indian Institute of Technology Bombay

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Microelectronics & VLSI at IIT Microelectronics & VLSI at IIT Bombay:Bombay:

Academic ProgrammesAcademic Programmes

J. Vasi

Department of Electrical Engineering

Indian Institute of Technology, Bombay

2003


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OverviewOverview• The Microelectronics Program is a part of EE Department

at IIT Bombay

• Microelectronics includes VLSI Design

• Links with the CS&E and ME&MS Departments

• Started in 1986; one of the oldest programs in the country

• Main thrust in silicon CMOS design, VLSI CAD, CMOS technology and devices, MEMS

• Group consists of 12 core faculty in EE Department, plus several others in related Departments

Academia Industry Meet 2003, Electrical Engineering Department


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FacultyFaculty

• P. R. Apte• A. N. Chandorkar• M. P. Desai• S. Duttagupta• R. Lal• S. Mahapatra• B. Gadepally (Adjunct)

• H. Narayanan • R. Parekhji (adjunct) • M. B. Patil• V. Ramgopal Rao• D. K. Sharma• J. Vasi• R. Pinto



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Associated FacultyAssociated Faculty

• A. Karandikar Elec. Engg.• D. Manjunath Elec. Engg.• S. S. S. P. Rao Comp. Sci. & Engg.• S. Chakrabarty Comp. Sci. & Engg.• M. Sohoni Comp. Sci. & Engg.• S. Patkar Maths• R. O. Dusane Met. Eng. & Mat. Sci.• R. Srinivasa Met. Eng. & Mat. Sci.• A. Contractor Chemistry



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Teaching ProgramsTeaching Programs

• Ph.D. (graduating ~ 3-4 / year)

• M.Tech. with specialization in Microelectronics (~ 35 / year)

• Dual Degree with specialization in Microelectronics (~ 18 / year)

• B.Tech. (~ 55 / year, ~ 15 / year with projects in Micro-electronics)



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Highlights of the Ph.D. ProgramHighlights of the Ph.D. Program

• About 15 Ph.D. students at any time

• Institute scholarship, industry fellowship or sponsored project assistantship

• Typical duration 3 – 5 years

• Industry fellowships from Intel, Siemens, GE

• Most full-time, some part-time



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Some Recent and Ongoing Some Recent and Ongoing Ph. D. ThesesPh. D. Theses

• S. Vaidya: Neutron radiation effects in MOS systems

• J. Meckie: Asynchronous design issues

• G. Trivedi: Parallel algorithms for VLSI optimization

• N. Mahapatra: High-k dielectrics for 100 nm CMOS

• A. Shastry: Microcapillary electrophoresis on silicon

• C.A. Betty: Capacitive immunosensor on porous Si

• B. Anand: Digital design with dynamic threshold CMOS

• D. Nair: Flash memory design and reliability

• D.V.Kumar: Look-up table approach for CMOS circuits



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Highlights of the M.Tech. ProgramHighlights of the M.Tech. Program• 2 year program with specialization

“Microelectronics”

• Emphasis on both Devices and VLSI Design

• Attracts the top students in the country (GATE percentile > 99%)

• 35 students admitted every year, including 20 TCS scholars

• 18-month-long M.Tech. project

• Placement in Indian and international semiconductor and design companies



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Structure of the M.Tech. Structure of the M.Tech. Microelectronics ProgramMicroelectronics Program

Semester I

• Physical Electronics• VLSI Technology• VLSI Design• VLSI Design Lab• M.Tech. Seminar• Elective I (one of the following)1. Foundations of VLSI CAD2. Hardware Description languages3. DSP and Applications

Semester II

• Microelectronics Lab • M.Tech. Project: Stage I• Electives II, III, IV (3 out of the

following)1. System Design2. Physics of Transistors3. Analog CMOS design4. MEMS Technology and design5. Embedded Systems6. Hardware test and verification7. Simulation of circuits and devices



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Structure of the M.Tech. Structure of the M.Tech. Microelectronics ProgramMicroelectronics Program

Semester III

• M.Tech. Project : Stage II• Elective V (one out of the

following)1. Foundations of VLSI CAD2. Hardware description Languages3. DSP and Applications4. Special topics in Microelectronics5. RF chip design6. Elective from other departments

Semester IV

• M. Tech. Project : Stage III



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Highlights of the Dual Degree (DD) Highlights of the Dual Degree (DD) ProgramProgram

• 5 year program with specialization “Microelectronics”• Students receive both B.Tech. and M.Tech. degrees at the end of 5

years• Entry through JEE, 3rd most popular branch at IIT Bombay after

B.Tech. (CS&E) and B.Tech. (EE)• Emphasis on both Devices and VLSI Design• 15 students admitted every year• Highlight is emphasis on independent study with 18- month-long

DD project• Placement in Indian and international semiconductor and design

companies as well as for Ph.D.• First DD batch admitted in 1996 – 7th batch admitted in 2002



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Structure of the Dual Degree Structure of the Dual Degree ProgramProgram

• I year and II year semesters are identical to the B.Tech. (EE) programme

• From III year onwards, M.Tech. level courses are introduced

• Many “independent-study” courses like DD Project, DD Seminar, Miniproject, Lab Techniques, Research Seminar, etc.

• DD Project starts in 8th semester, and continues through the 10th semester (18 months), including 2 summer sesions



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Areas of R & D and Student ProjectsAreas of R & D and Student Projects

• VLSI modeling and simulation• VLSI design (digital, analog, mixed-mode)• VLSI CAD tool development• Interaction between VLSI technology and design• Silicon CMOS physics and technology• MEMS• Organic LED’s for display applications• Flexible solar cells• Flash memory: Characterization Analysis,

Reliability Study, Device Scaling.



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FacilitiesFacilities

• Class 1000 Clean Room• Excellent characterization facility• SEM; photoluminescence• VLSI design workstations• Simulation workstations• Intel Microelectronics Lab• TCS VLSI Design Lab• Wadhwani Electronics Laboratory



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CollaborationsCollaborations• Industry sponsorship of Ph.D., M.Tech. and DD

students: TCS, Intel, TII, Sasken, Analog, Cypress, Siemens, GE, IME, etc.

• Research Projects with Indian industry: BEL, ITI, Sasken, TII, Cypress, ControlNet, etc

• Research Projects with international industry: Intel, Motorola, GE, Siemens, National, IME, Agere, Hitachi, IBM

• Government Agencies: DST, ISRO, NPSM (National Programme on Smart Materials), MHRD, NRB



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University CollaborationsUniversity Collaborations

• Collaborations with other IITs, Universities of Bombay, Pune

• Collaborations with International universities like– UCLA, UCSB, Yale University (USA)– Hong Kong University of Science & Tech. (HK)– Delft University (The Netherlands)– University of Bundeswehr (Germany)– Griffith University (Australia)– NTU, NUS (Singapore)



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ConclusionsConclusions

• Most active Microelectronics & VLSI group in India• Major teaching programs at all levels • 110 – 120 graduate students resident in

Microelectronics and VLSI group at any time• 35 M.Tech, 18 DD and 3 Ph.D. students graduating

every year• Excellent teaching & research facilities• Student project sponsorships from Indian &

international industry



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ContactsContacts• Microelectronics Group

Department of Electrical EngineeringIndian Institute of Technology, BombayPowaiMumbai 400076 India

• Phone: +91-22-2572-4482• Fax: +91-22-2572-3707• email: [email protected]• website: www.iitb.ac.in/~microel/



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SEQUEL: ASEQUEL: A S Solver for circuit olver for circuit EQEQuations uations with with UUser-defined ser-defined ELELementsements

Prof. Mahesh B. PatilProf. Mahesh B. Patil

www.ee.ittb.ac.in/faculty/mbp/sequel1.htmlwww.ee.ittb.ac.in/faculty/mbp/sequel1.html


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• Allows user-defined elements

• DC, transient, small-signal, noise

• Mixed-signal simulation

• Electrothermal simulation

• Sensitivity analysis (exact)

• Switched capacitor circuits

• Efficient “steady-state waveform” computation

• Perfectly “general” elements are possible

(mechanical, thermal etc)

SEQUEL: FeaturesSEQUEL: Features

Continued



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• DST (Circuit Simulation using the LUT

approach)

• PEPS group at IIT Bombay

• IISc Bangalore (Power electronics text book)

• Department of BME, IIT Bombay

• Intel (study of NQS effects in MOS transistors)

• IME (Circuit simulation using experimentally

extracted tables)

Collaboration based on SEQUELCollaboration based on SEQUELAcademia Industry Meet 2003, Electrical Engineering Department


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Fast Circuit Simulators at IIT BombayFast Circuit Simulators at IIT Bombay

Prof. H.NarayananProf. H.Narayanan

[email protected]@ee.iitb.ac.in


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BREMICS (1986, 87, 90) for analog simulation of networks arising out of digital circuits (MOS transistors, resistors, capacitors)

• could handle 1000 nodes, 2000 edges. For the restricted class much faster (5 to 10 times) than SPICE on PCs.

• BITSIM (1991-92) general purpose (SPICE like) simulator based on conjugate gradient method for solution of linear equations and the hybrid analysis for writing equations. Could handle 3000-4000 nodes, 8000 edges originally on SUN, now on Pentiums. Work done through several B.Tech and M.Tech. projects and through a research engineer

(Dr. Subir Roy)



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Currently “Large Circuit Simulations” by Parallelization is actively pursued

The innermost subroutine of a general purpose simulator is a DC circuit analyzer (voltage sources, current sources, resistors, controlled sources)

We parallelize this by the “Multiport Decomposition Method”

Our simulator can currently solve

700,000 nodes, 1.4 million edges dc circuit in about 5 minutes using 5 processors (Pentium IV ‘s) connected through a 100 MBPS link


25Indian Institute of Technology Bombay

Application of large dc circuit analyzerpplication of large dc circuit analyzer

100,000 RC

Elements

1000RC

Elements

Few terminals

Same terminal

behaviour

Same terminal

behaviour

1) The Multi port Reduction Problem

arises while modelling “short circuits” in chips at high frequency Continued



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we have constructed a few such reduction algorithms andwe have constructed a few such reduction algorithms andimplemented them. e.g. SARN reduces RC circuit with implemented them. e.g. SARN reduces RC circuit with 100,000 nodes 200,000 edges 50 terminals in ½ hour to 1000 100,000 nodes 200,000 edges 50 terminals in ½ hour to 1000 node circuit with 50 terminalsnode circuit with 50 terminals..

2) Solving a large Combinational optimization problems a) Network flow problems

b) Minimum cost flow problems

Both of these can be posed as nonlinear static circuit analysisproblems

Innermost subroutine is a DC analyzer.

Continued



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3) Parallelizing large Sparse linear equations The equations are made to appear like those

of a dc circuit and then given to the dc analyzer to solve by “Multi port Decomposition”.


V. Ramgopal [email protected]

Mixed Signal CMOS Device Design Mixed Signal CMOS Device Design and Optimization for Bulk and and Optimization for Bulk and

SOI TechnologiesSOI Technologies


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OutlineOutline

Scaling CMOS-Analog Performance Device Engineering-Bulk&SOI Process Development-Bulk&SOI LAC-Bulk Analog Performance LAC-SOI Analog Performance

Floating Body Effects-Channel Engineering Circuit Implications-LAC Technologies Hot Carrier Reliability



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ANALOG AND RF DESIGNANALOG AND RF DESIGNProf. D. K. SharmaProf. D. K. Sharma

• Data Converters (DKS/ANC/MPD)

• Low Voltage/Low Power Design (ANC/DKS)

• RF Transmitters and Receivers (ANC/DKS)

• PLL and DLL circuits (ANC)

• Broadband Communications related circuits (ANC/DKS)

• Modeling and Simulation for RF, Analog (JV/MBP)


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