AIAA 98-3923Microfabricated Ion Accelerator Grid Design Issues:

Electric Breakdown Characteristics ofSilicon Dioxide Insulator Material

Juergen Mueller*, David Pyle", Indrani Chakraborty+, Ronald Ruiz*, William Tang++,and Russell Lawton*

Jet Propulsion LaboratoryCalifornia Institute of Technology

Pasadena, CA 91109

Low-temperature (LTO) chemical vapor deposited (CVD) silicon dioxide was investigated foruse as an insulator material in microfabricated ion engine accelerator grids. Both substrate(bulk) as well as surface breakdown experiments were performed. Oxide thicknesses forsubstrate breakdown tests ranged between 1 jim and 3.9 um. Surface breakdowns wereperformed over gap distances ranging between 5 um and 600 |im. Substrate breakdownstrengths up to 600-700 V/p.m were measured, allowing for maximum stand-off voltages o f2500 V. A slight decrease in breakdown field strength for larger thicknesses was observed.Temperature effects on substrate breakdown field strengths do exist, however, are small .Only a 15% drop in breakdown field strength was noted at 400 C vs. strengths measured atroom temperature. Surface breakdown field strengths ranged as high as 140 V/|im , leading t oa stand-off capability of 700 V over a 5 |im oxide film. Tests were performed to study theinfluence of silicon oxide surface morphology on the surface breakdown strength and nonewas found.

I. INTRODUCTION

Background and Motivation

There currently exists a strong interest withinthe aerospace community in micropropulsion devicescapable of delivering very small thrust values and lowimpulse bits having engine sizes and masses orders ofmagnitude smaller than available with currenttechnologies'. Within the National Aeronautics and SpaceAdministration (NASA), the reason for this interest canbe found both in the drive to explore the feasibility ofmicrospacecraft designs2, typically viewed as spacecrafthaving wet masses on the order of 10-20 kg and less, aswell as the need for fine attitude control of largerspacecraft, such as those envisioned for spaceinterferometry missions3.

Whereas some micro-thruster devices will beused predominantly in pulsed operational modes for

'Advanced Propulsion Technology Group. Senior MemberAIAA." Academic Part-Time, University of Texas.*MEMS Group, Micro Devices Laboratory** Group Supervisor, MEMS Group, Micro DevicesLaboratory."Failure Analysis Group

attitude control purposes, others may require a morecontinuous mode of operation, as for primary propulsionapplications on future envisioned microspacecraft, forexample, or for continuous disturbance torquecompensation and drag make up on larger spacecraft. Suchtasks may best be accomplished using high specificimpulse (Iso) devices. In addition, many of NASA'senvisioned future missions will require large delta-vincrements. Such is the case for many of the plannedmissions to small bodies (comets, asteroids) and anymicrospacecraft to be used on such a mission will thusrequire according propulsive capabilities. In the case formicrospacecraft in particular, where spacecraft wet masshas to be kept low, the use of high Isp propulsion devicesmay be a necessity to keep required propellant massessmall.

Currently among the most mature high-Isppropulsion technologies is ion propulsion. Presentlyavailable devices, however, a relatively large, with someof the smallest operational inert gas engines rangingaround 10-cm in beam diameter, and requiring powerlevels on the order of several hundreds of watts'. Thus,there exists a need to further miniaturize this technologyto make it more suitable for the aforementionedapplications.

Copyright © 1998 by the American Institute of Aeronautics and Astronautics, Inc. No copyright is asserted in the United Statesunder Title 17, U.S. Tax Code. The U.S. Government has a royalty-free license to exercise all rights under the copyright claimedherein for governmental purposes. All other rights are reserved by the copyright owner

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At the Jet Propulsion Laboratory (JPL) there iscurrently underway an experimental study to investigatethe feasibility of reducing ion engine sizes dramaticallybelow current state-of-the-art technology1-4. The currentfocus of this program is to target engine diameters in the2-3 cm range and thrust levels in the sub-mN range. Inorder to arrive at a functional ion engine system of thissmall a size, several feasibility issues will need to beinvestigated and overcome. Among these are thesustainability and efficient operation of high surface-to-volume ratio plasma discharges, the replacement ofhollow-cathode technologies with lower-power-consuming and easier to miniaturize cathode systems,such as cold cathode technology5, miniature acceleratorgrid system fabrication and operation4, as well as thefeasibility of fabrication and operation of miniaturizedpower conditioning units and feed system components6.

Scope of this Study

Current focus at JPL in regard to micro ionengine technologies has been on cold cathodedevelopment5 and micro-machined ion accelerator gridstudies4, representing two key components in a micro-ionengine, and each presenting unique feasibility issues. Thecurrent paper presents a continuation of the ion enginegrid studies. Different fabrication techniques, either moreconventional machining approaches or microfabrication(MEMS - Microelectromechanical Systems) techniques,are being explored. The advantage of using MEMSfabrication techniques lies in their ability to fabricatedevices with extremely small dimensions to very tighttolerances. In particular for ion accelerator grid systemswhich require the placement of a multitude of holes (orslots7) in precise relative position to each other to ensureproper grid aperture alignment and beam extraction, theseadvantages weigh heavily in favor of this technique.

On the other hand, MEMS-fabrication ofaccelerator grids opens up a host of fabrication andoperation-related issues. Foremost among them is theselection of appropriate grid materials, suiting bothmicrofabrication as well as grid operation needs. Inparticular the grid insulator material, isolating the screenand accelerator voltages from each other, will have to beable to stand off voltages on the order of 1.3 kV or moreover distances on the order of a few micrometer if currentgrid voltages, and engine specific impulses, are to bemaintained, as is desirable.

It is the scope of this study to investigate thefeasibility of silicon dioxide as a grid insulator materialfor use in microfabricated grids and determine its

implications on grid design. Silicon oxide was chosensince it exhibits good insulating characteristics and isalready widely used in the microfabrication field. In orderto study the suitability of silicon oxide for thisapplication, both bulk electric breakdown characteristics,as well as electric breakdown characteristics along itssurface need to be studied. This is evident from inspectingFig. 1. As can be seen, both modes of electric breakdown,substrate (or bulk) and surface, are possible in a typicalgrid design. The latter may occur along the walls of gridapertures. Two experiments were conducted usingspecially designed silicon oxide breakdown test chips tosystematically study both modes of electric breakdown,and will be described in detail below.

II. PREVIOUS RELATED RESEARCH

It may seem surprising at first that a detailedstudy of breakdown behavior of oxide films is necessarysince a substantial amount of research has already beenperformed in this area over the past several decades.However, a closer examination of the available literaturereveals that results obtainable from past research may notbe directly applicable to the problem studied here.

Most previous research work on breakdowncharacteristics has been focused on studying the electricbreakdown of gate oxides in MOSFET applications.These gate oxides are typically very thin, less than onetenth of a micron thick, and the required minimumbreakdown voltages range into the tens of volts, and thusare significantly lower than the kV-voltage rangeconsidered for grid applications. One particular type ofoxide considered most frequently for gate oxideapplications is thermal oxide. This oxide layer is createdby directly oxidizing the silicon surface in an oxygenfurnace (dry oxide), sometimes aided by the addition ofsteam (wet oxide) to increase film growth rates8.

Accel Grid (-) Surface SubstrateBreakdown Breakdown

~\ \

Screen Grid (+) Insulator Grid Aperture

Fig. 1: Anticipated Grid Breakdown Modes

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Studies on breakdown strengths of thermaloxides have been performed by Osburn and Ormond9' '",Osburn and Weitzmann", Klein12, Chou and Eldridge13,Soden14, Fritzsche15, Worthing16 and Yang et al.17.Typically two types of breakdowns were observed by allresearchers: the so called primary and intrinsic, or final,breakdown. Primary breakdowns range fromapproximately 200 V/|j,m to as high as 1000 V/p.m,whereas final breakdowns follow a more sharply peakeddistribution ranging between approximately 800 - 1000V/(im9. In some cases, final breakdown strengths as highas 1400 - 1500 V/|j.m have been observed for extremelythin oxides10. Primary breakdowns are thought to betriggered by thermal instabilities along defects in theoxide12. As resistance is locally increased, conductivitieslocally decrease and the resulting increase in current addsJoule heat, leading to a further decrease in conductivity,and so on, until breakdown occurs. Using very thinelectrodes (less than 0.3 |J.m in the case of Osburn's andOrmond's experiment10) the electrode will be destroyedthrough evaporation of electrode material near thebreakdown location, thus representing a "self-healing"breakdown since no electrical contact can be maintainedbetween the two electrodes due to the loss of thismaterial. This allows all defect related breakdown sites tobe eliminated until the intrinsic, or final, breakdown isreached. This breakdown strength thus corresponds to thedielectric strength of ideal, defect-free oxide material.Different theories evolve around this final breakdown andboth thermal breakdown12, similar to the process thoughtto govern defect-triggered breakdowns, as well aselectronic breakdowns10 due to electron avalanches havebeen proposed.

Whereas the final breakdown strength is ofinterest for the fundamental research of oxide breakdown,for practical applications the primary breakdown strengthis the more important one. Chou and Eldridge13 havesucceeded in fabricating virtually defect free thermaloxides and eliminated primary breakdowns, resulting infinal breakdown strengths of 600-700 V/\im and up to1000 V/|am for thermal oxide coated withphosphorsilicate glass, filling pits in the oxides whichwere believed to have triggered breakdowns.

While it thus appears possible to achieve ratherhigh electric breakdown strengths using carefully preparedthermal oxides, absolute voltages that can be stood offwith these oxides may, however, be rather limited. Thisis largely due to the fact that thermal oxides are typicallygrown only up to thicknesses of around 1 ^m, possiblysomewhat larger, but less than 2 |0.m. The reason for thislimitation can be found in the thermal oxidation process.The surface is oxidized directly, i.e. no oxide layer is

deposited onto the silicon surface, and the oxide layerinstead grows partly into the silicon, using the substratesilicon to form the oxide8. Since new oxygen arriving atthe surface now has to penetrate an increasingly thickeroxide layer to form an oxidation reaction with theunderlying silicon, diffusion limitations will eventuallyoccur, resulting in increasingly larger process times untilthe process becomes impractical. Therefore, even usingChou's and Eldridge's13 values for defect-free oxides, theobtainable voltages that can be stood off for oxides beingless than 2 |im thick may thus be somewhat marginalassuming that voltage of 1.3 kV will be required for gridapplications and an adequate additional margin of safetywill have to be maintained.

If, as was the case in most of the experimentsconducted, much lower voltage primary breakdownsoccur, stand-off voltages would be insufficient for ionengine grid applications. The process of "self-healing"breakdowns, while appropriate in fundamental researchexperiments, would not be suitable for operational ionengine grids either since the massive erosion of thinelectrode material would lead to grid destruction whichcould severely affect beam extraction. In addition, thermaloxides will need to be grown directly on silicon surfaces,thus limiting the choice of substrate materials to silicononly. Although silicon can be doped to render itelectrically conductive, other considerations, such as theall-important sputter yield considerations in view of ionengine grid lifetimes, may make this too limited a choice.

Other oxides that have been investigated in thepast are RF-sputter deposited oxides. These oxides can begrown to much larger thicknesses (several microns) sincethe silicon surface is coated with externally supplied,sputter-eroded silicon oxide material. Limitations withrespect to thickness arise eventually as thick oxidesdevelop intrinsic compressive stresses which may lead todelamination of oxide from its substrate material. Pratt18

performed dielectric strength measurements on RF-sputterdeposited oxides, however, given the targeted applicationsin the electronics industry, focused only on very thinoxides. Measured dielectric strengths ranged from 1000V/nm at 0.07 (am to about 220 V/|im at 0.7 |0.m. Thistrend of decreasing electric breakdown field strength isnoteworthy and has also been noted for thermal oxides.While breakdown voltages typically still increase withincreasing oxide thickness, the trend towards lowerelectric breakdown field strengths for thicker oxides limitsthe voltage stand-off capability. In the case of Pratt'sexperiment, the breakdown voltage at 0.7 jam can thus becalculated to about 150 V.

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Klein and Gafni19 reported electric breakdownfield strengths for vapor-deposited oxide films on glassslides, fabricated by evaporation of silicon monoxide inan oxygen atmosphere. Silicon dioxide and siliconmonoxide layers were created. The silicon dioxide layerswere up to 0.49 |J.m thick and yielded breakdownstrengths of 490 V/(im, or about 250V voltage stand-offcapability. Silicon monoxide layers of up to 5 |J,m weredeposited and resulted in electric breakdown field strengthsof 192 V/|o.m, thus yielding a voltage stand-off capabilityof just under 1000 V. Silicon monoxide breakdown fieldstrengths were found to be less than those for silicondioxide for comparable oxide thicknesses. Again, as in thecase of thermal and sputter-deposited oxides, a trendtowards lower breakdown field strengths with increasingoxide thickness could be noted.

The survey of the literature thus demonstratedthe need for a more targeted investigation of thick oxidescapable of delivering stand-off voltages comparable totypical grid voltages with acceptable margins of safety.Chemical vapor deposited (CVD) oxides are known toproduce good electric insulation and can be deposited atthicknesses up to about 5 \im. However, more detailed,additional information was required especially concerningbreakdown characteristics of thick oxide films, surfacebreakdown data, as well as temperature dependence of thebreakdown strength of these oxides since grid operatingtemperatures may range between 300 - 400C.

Therefore, a systematic study of breakdownstrengths of LTO-CVD oxides was initiated. Preliminaryresults were reported in an earlier paper4. Those tests wereconducted with a limited amount of test chips and thusprovided only a very preliminary data base. Althoughtests in Ref. 4 were initially only targeted to providesubstrate, or bulk, electric breakdown field strengths, andtests were therefore conducted in atmosphere forsimplicity, unintended, parasitic electric breakdownsalong the surface were also noted during thoseexperiments. Surface electric breakdown field strengths atthe gap distances encountered (about 200 |J.m) were low,ranging only around 2V/|im. This necessitated a furtherdevelopment of this experiment. First, test chips intendedfor the measurement of substrate breakdowns had to beredesigned to eliminate the, in this case, parasitic surfacebreakdowns, and a more systematic examination ofsurface breakdowns had to be initiated. The latter testswere to be conducted under vacuum conditions toeliminate any gas breakdown or surface contaminationeffects. The following section will describe this new setof experiments in detail.

III. DESCRIPTION OF EXPERIMENT

The experiments (substrate, or bulk, and surfacebreakdown) were conducted with two types of test chips.A total of about 160 chips has been tested at the time ofthis writing, with additional experiments still being inprogress. About 80 substrate and 80 surface breakdowntests have been performed so far. The chip type used forsubstrate breakdown is shown in Fig. 2. Each chip isabout 1 x 1 cm2 in size. It consists of a silicon substratewafer (400 firn thick) onto which a thin layer (0.3 |j,m) ofdoped polysilicon is deposited (about 22 £}/Dresistivity). Next a layer of LTO oxide, using a lowpressure CVD (LPCVD) silane/oxygen process, isdeposited up to a thickness of 3.9 (im at around 450C.Poly and oxide deposition was performed at theUniversity of Berkeley. Some chips tested were poly andoxide-deposited at the University of California/LosAngeles (UCLA) earlier using a similar process, yieldingoxide thicknesses of a maximum of 2.7 M.m. The lattertype of chips was also used in previous tests reported inRef. 4.

Depending on the desired oxide thickness, theoxide layer is etched back. Next, a via is etched into theoxide to provide access to the polysilicon layer, whichwill form one of the two electrodes. Finally, a 0.25 |imthick aluminum layer is deposited onto the chip, patternedand etched to form the second electrode as well as a heatercoil. This (square-shaped) heater coil can be seen in Fig. 3and is used to heat the chip for breakdown testing atelevated temperatures. Temperatures up to 400 C havebeen achieved with this design at power levels of about11 W (160V, 0.07 mA). Small variations in heater coilperformance were found from chip to chip.

The substrate breakdown tests were performedunder atmospheric conditions by placing the test chipsinto a specially designed quartz fixture, which in turn wasplaced underneath an IR camera (see Fig. 4). The IRcamera was used for temperature measurements and alsowas able to record arcing on the chip at ambienttemperature. The IR image was recorded on video tape for

Al Contact Pad SiCX Heater Coil

Si-Substrate DopedPolysilicon

Fig. 2: Schematic of Substrate Breakdown Chip

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Al Contact Pads Heater Coil

Fig. 3: View of Substrate Breakdown Test-Chip

Fig. 4: Substrate Breakdown Test Set-up

later test evaluation. The chip was contacted via a probestation featuring four adjustable probe tips. Two tipsserved as high-voltage leads while the remaining two wereused to contact the heater coil. Unfortunately the range ofthe probe tips was not large enough to test entire wafers.Therefore, wafers had to be diced into individual chips andthe chips were tested one by one.

The design of the surface breakdown test chipvaried slightly from the one of the substrate breakdownchips. The surface breakdown chip design is shownschematically in Fig. 5. The chip is of the same size asthe substrate breakdown chip and very similar inappearance to the chip in Fig. 3, however, featuringsmaller contact pad areas. In the case of the surfacebreakdown test chip, no doped polysilicon layer wasdeposited onto the silicon substrate, instead LTO oxide(same process as described above) was deposited directlyonto the substrate wafer. Following was an aluminumdeposition (same thickness as above), and pattern andetching of the aluminum. Aluminum pads were placedbetween 100 Jim and 600 (im apart, in 100 |im

Si-Substrate DopedPolysilicon

Fig. 5: Schematic of Surface Breakdown Chip

increments. Later in the course of the experiment it wasfound that testing of molybdenum contact pads wasconsidered desirable, and accordingly chips featuringcontact pads made from this material were fabricated. Padson that set of chips were separated by 5, 10, 20, 100,200, and 300 |im, respectively.

In order to simplify the fabrication process, thesurface breakdown test chips also featured a 3.9 fim thickoxide which allowed the wafers to be fabricated in thesame production run as the wafers bound for substratebreakdown chip fabrication. In the course of the tests itwas noted that the thick oxide had suffered localizedsurface delaminations in the shape circular, droplet shapedbubbles due to the high intrinsic stresses in the thickoxide. Since it was uncertain how these delaminationswould affect surface breakdown strengths, another set ofsurface breakdown chips featuring a 2 Jim thick oxidelayer, free of surface delaminations, was also fabricated,and tests were performed with both set of chips todetermine the effect of surface morphology on surfacebreakdown characteristics.

The surface breakdown chips were mounted intoa different probe station, also featuring four probe tips,that could be attached to a Scanning Electron Microscope(SEM) vacuum stage (see Fig. 6). Pressures as low as 1 x

Fig. 6: Experimental Set-up for Surface Breakdown

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10"6 Torr could be obtained, although the majority of testswas performed at 3 x 10"5 Torr, since this pressure levelcould be reached rather quickly using the existingpumping facilities. The vacuum stage of the SEM wasturbomolecular pumped.

Both breakdown experiments, substrate andsurface, were conducted using a portable DC Hypot deviceby Associated Research, Inc (Model 5220A). This deviceis capable of delivering up to 15 kV at currents of 2 mAor less. Voltages were recorded with a separate voltmeter(Simpson 260 Series 4). Currents were registered on thescale provided with the Hypot device. This current scalewas calibrated and known to be accurate within 3-5%.Prior to breakdown of the chips, however, it was notedthat most of the current registered (in the |iA range) wasflowing through the voltmeter, as current levels wereseverely influenced by voltmeter settings. Duringbreakdown, however, currents typically ranged as high as0.5 mA and voltmeter effects were negligible bycomparison.

All chips were cleaned inside themicrofabrication cleanroom facilities after dicing in anacetone ultrasonic bath for 10 minutes to removecontaminants and mainly remaining photoresist traces,followed by an isopropyl alcohol rinse to removeremaining acetone residues, followed in turn by a dry andwere finally subjected to an oxygen plasma etch at 200 Wfor 10 minutes to remove remaining organic residue. Thechips were then sealed inside plastic trays. The chips wereleft sealed inside those trays until the moment of usage,at which time they were subjected to the laboratoryenvironment either for the duration of the test (substratebreakdown), or, in the case of the surface breakdown tests,for the duration it took to install one chip onto the probestation and pump down the system, typically a fewminutes.

IV. SUBSTRATE BREAKDOWN TESTS

Oxide Thickness Dependence

Determining breakdown field strength withrespect to oxide thickness is crucial in the evaluation ofLTO oxides for use in ion accelerator grids. As was seenin Section II, electric breakdown field strengths typicallyvary with oxide thickness, and simple extrapolation of abreakdown field strength obtained for one oxide thicknessto a much different thickness may not be appropriate.Chips with oxide thicknesses of 1, 1.5, 2, 2.7, and 3.9|j.m were tested. The breakdown field strengths vs.thickness are plotted in Fig. 7. As can be seen, for thethicknesses studied here a small downward trend in

E

> 800

600-

Breakdown Field Strength vs. Oxide ThickneLTO Oxide

1.0 1.5 2.0 2.5Oxide Thickness (&i

3.0 3.5 4.0

Fig.7: Electric Breakdown Field Strength vs. LTO OxideThickness

breakdown field strength can be noted with increasingthickness. Breakdown field strengths range betweenapproximately 600 - 750 V/\im at 1 |im oxide thicknessto around 600 - 650 V/(j,m at 3.9 |o.m. Two data pointssignificantly below those values can be found for two 3.9Urn chips. These values may likely be due to oxidedefects. The curve fit shown in Fig. 7 excludes these twodata points. Breakdown voltages can thus be foundbetween 600 - 750 V at 1 |o.m oxide thickness,approaching 2000 V at 2.7 |J,m thickness, and reachingvalues as high as 2500 V at 3.9 (0,m oxide thickness.Thus it can be estimated that LTO oxide thicknesses of Jjam or greater are fully sufficient to stand off typical gridoperating voltages, as far as substrate breakdown isconcerned. Later it will be shown that for the associatedsurface breakdown for this thickness a differentconclusion may have to be drawn.

The data obtained in this study for LTO CVDoxide were compared with data obtained for differentoxides from the previously reviewed literature (seeSection II). Breakdown field strengths for various oxidesat different thicknesses are compared in Fig. 8. Asmentioned already in Section II, breakdown field strengthsmuch larger than the ones obtained in this study havebeen recorded in almost every case found in the literature,however, at much lower oxide thicknesses. This increasein breakdown field strength with decreasing oxidethickness appears to become more pronounced withthinner oxides in all cases, independent of the oxideconsidered, although numerical values vary from oxide tooxide. Thermal oxide breakdown strengths are particularlyremarkable, which is precisely the reason for theirextensive use as gate oxides in MOSFET applications. Itshould be noted, however, that the values listed in Fig. 8for thermal oxide, taken from Ref. 10, are theaforementioned intrinsic, or final breakdown values, and

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Breakdown Field Strength vs. Oxide Thicknessfor Various Oxide Types

Solid Symbols are Averaged Values

• Vapor-Deposilad Oxide on Glass, Klein and Gafni• Thermal Oxide. Osburn and OrmondA RF Sputter-Deposited Oxide, PrattO CVD (LTD) Oxide. This Study

Oxide Thickness (u.m)

Fig. 8: Breakdown Field Strengths for Various Oxides vs.Oxide Thickness

primary breakdown values due to oxide defects aretypically significantly lower.

The value of this investigation becomes evidentwhen plotting the obtained breakdown voltages vs. oxidethickness, as shown in Fig. 9. Due to the availability ofthicker LTO oxides, achievable breakdown voltages aremuch higher for LTO oxides than for any other oxideconsidered in this comparison. Even if breakdownvoltages for thermal oxides were to be extrapolated intothe 1 - 2 (im thickness range (roughly the maximumobtainable thermal oxide thickness), obtainablebreakdown voltages would be marginal for accelerator gridapplications, and LTO oxides, due to their largerachievable thicknesses, will still outperform thermaloxides, as well as all other oxides considered. Theseresults displayed in Fig. 9 thus very clearly validate theapproach taken in this study.

1000-

>

:100.

10.

Breakdown Voltage vs. Oxide Thicknessfor Various Oxides

Solid Symbols are Averaged Values

• Vapor-Deposited Oxide on Glass. Klein and Gafni• Thermal Oxide, Osbum and OrmondA RF Sputter Deposted Oxide, Pratto CVD (LTO) Oxide. This Study

! i a'IS'1 1 5 S SUii I ! i t ! S f S 'I0.01 0.1 1

Oxide Thickness (urn)

Fig. 9: Breakdown Voltages vs. Oxide Thickness forVarious Oxides

Temperature Dependence

In Fig. 10 electric breakdown field strengths fora 1 |im thick LTO oxide at various temperatures areshown. Temperatures were varied from ambient (23 C) toas high as 400 C. Typical grid temperatures forconventional (macro-sized) grids range between 300 - 400C. As can be seen, breakdown field strengths decreaseslightly with temperature. At ambient, breakdown fieldstrengths range around 600 - 750 V/(im (and breakdownvoltages accordingly around 600 - 750 V for a 1 \im thickoxide sample). At 400 C, the breakdown strength hasfallen off to 500 - 650 V/|J.m, corresponding to abreakdown voltage range of 500 - 650 V. Thiscorresponds to drop in breakdown strength and voltage ofabout 15%.

Attempts were made to repeat measurements atthe more relevant oxide thicknesses of 2.7 .̂m and 3.9(im, respectively. However, since these tests wereperformed under atmospheric conditions for reasons ofsimplicity and in order to have access to the IR camera,heavy arcing was noted on and above the chip surface.Arcing was noted between different locations on the chip,between probe tips and the chip, as well as between probetips. The arcing was found to be definitely morepronounced at higher temperatures and may have been dueto Paschen breakdown. Since in the case of the 1 (imsample required breakdown voltages are low, theseproblems were not encountered. Furthermore, the drop inbreakdown field strength, at least for the smaller oxidethicknesses, is so low, and the margins with respect tobreakdown strengths for ion engine grid applications forthe larger thicknesses so great, that temperature effects arecurrently not being considered a serious impediment toproper grid function with respect to substrate breakdown.

1200-

5-1000 •:

Z 800-

600 J

400 J

Breakdown Field Strength vs. Temperature1.0 urn LTO Oxide Thickness

O

o

100 200Temperature (C)

300 400

Fig. 10: Electric Breakdown Field Strength vs.Temperature for 1 jim LTO Oxide

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Visual Post-Test Inspection of Test Samples

Electron microscope scans were taken of varioustest samples after the breakdown tests to determine theirfailure mechanisms. Figure 11 shows a typical oxidebreakdown. It is located at the edge of the aluminumcontact pad area, still recognizable in the lower part of thephotograph, although heavily eroded in the immediatevicinity of the breakdown. Note the relatively large sizeof this breakdown, extending approximately 30 \im indiameter. Oxide thickness in this case was 2.7 Jim.Electric breakdown occurred at 1800 V. The oxide used inthis case was of the batch provided by UCLA.

Breakdown at the contact pad edges and contactpad corners by far outnumbered breakdowns at other padlocations. Similar observations were made by Soden14

during his investigation of the dielectric strength ofthermal oxides. Soden attributed this fact to the lack ofdefects in the oxides. If defects would have triggered abreakdown, one would expect the breakdown sites to bedistributed more randomly. The fact that breakdownsinstead occur predominantly on contact pad edges andcorners are an indication that these may be intrinsicbreakdowns, triggered by the higher electric field strengthin these regions. Small inhomogenities on the contactpad surface or slight variations in the oxide thickness maytrigger breakdown at one particular location along thecontact pad edge versus another. Given the high numberof breakdowns on contact pad edges leads us to believethat the oxides were mostly free of defects.

Figure 12 shows a side-on view of thebreakdown shown in Fig. 11, clearly indicating that theoxide layer, visible as the lightly colored layer just abovethe darker colored silicon substrate, has been penetrated(the polysilicon layer, being only 0.3 Jim thick, is hardlyvisible on the photograph and appears as a very thin blackline just between the silicon substrate and the oxide in theoriginal). As can be seen, besides destroying the oxidelayer, substantial damage has also been done to thesilicon substrate located directly below the breakdownarea, likely due to the excessive Joule heat duringbreakdown. Although no temperature measurements onthe arc were performed in this study, Klein12, inperforming spectroscopic temperature measurements onthe breakdown arc, determined arc temperatures on theorder of 3900 - 4500 K for thermal oxide breakdowns. Ifsimilar temperatures were to occur in LTO breakdowns aswell, these values would certainly be sufficient to meltthe silicon substrate, having a melting temperature ofabout 1400 C.

Fig. 11: Electric Breakdown at Aluminum Contact PadEdge

Fig. 12: Side View of Breakdown shown in Fig. 11

Figure 13 shows a spectral (X-ray fluorescence)analysis of the distribution of elements surrounding thebreakdown shown in Figs. 11 and 12. Three picturesegments show the distribution of silicon (top right),aluminum (bottom left) and oxygen (indicative of siliconoxide, bottom right) as seen from a top view positionsimilar to the one shown in Fig. 11. As can be seen byinspecting the top right segment, silicon is clearly visiblethrough the gap in the oxide layer, which shows up as adark ring shaped structure in the oxygen scan in thebottom right segment, indicating the lack of oxide here.This, together with the visual evidence presented in Fig.12, also gives a clear indication that a break-through tothe underlying silicon/polysilicon layers has indeed takenplace. Also visible in these scans is the heavy erosion ofthe aluminum contact pad (located in the lower half of thepicture segments). While some aluminum traces can stillbe found in this area (see lower left picture segment), thesilicon oxide, onto which the aluminum contact pad was

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Fig. 13: Spectral (X-Ray Fluorescence) Analysis ofBreakdown shown in Fig. 11.

deposited, is clearly visible in this area now as well (seelower right picture segment).

In the case shown Figs. 11-13, as in allbreakdown cases recorded during this set of experiments, apermanent short was noted after breakdown. Voltagestypically collapsed to values ranging around a few tens ofvolts or less (after having been as high as several hundredor even thousands of volts just prior to the breakdown)and currents in excess of 0.5 mA were measured (currentvalues prior to breakdown on the order of a few micro-Amps to possible the low 20 (J.A range were registered,but were found to be dependent on the volt-meter setting.It is thus believed that a substantial fraction of thiscurrent went through the meter, rather than through thesample). The short is likely caused by the severedisturbances noted in the breakdown area, as seen in Fig.12, mixing elements of the various chip layers, thusproviding electrical contact.

Figure 14 shows another breakdown of a chipfeaturing 2.7 \im thick oxide, with the breakdown alsooccurring at 1800 V, as in the case of the chip depicted inFigs. 11 through 13. This chip was fabricated using theoxide provided by Berkeley. A peculiar meandering patterncan be noted on the chip surface in areas that have seenheavy aluminum pad erosion. The sequence of events, asdocumented by the IR camera and recorded on tape, was asfollows: Breakdown first occurred at a contact pad edgelocation in the top left corner of the pad area. The probetip contacted the pad area in the location shown. Afterbreakdown at the contact pad edge, the aluminum paderoded outward from the initial breakdown location, withthe eroded aluminum pad edge recessing until it reachedthe probe tip location. At this point the erosion processstopped. The voltage dropped from 1800V prior to

Fig. 14: Propagating Breakdown Pattern showing "Tree-shaped" Conductive Channel Formations

breakdown (at small pA current values believed to beconducted largely through the volt meter), to about 500-600 V and about 0.5 mA during the surface erosion/arcingprocess, and finally collapsing to the aforementioned fewto few tens of Volts at currents of about 0.5 mA,shorting the circuit. Current and voltage values, exceptfor the initial breakdown voltage of course, were foundtypical for most chips, except for the ones using thethinnest oxides (1 (J.m).

At first glance, the meandering erosion patternseems to point to a pure surface breakdown phenomenonas a result of arcing between the - after the initialbreakdown at the pad edge - exposed grounded polysiliconlayer and the aluminum pad edge which is held at highvoltage and which typically evaporates around the initialbreakdown area as a result of excessive Joule heat. Thesurface arcing between the breakdown area and thealuminum layer then continues to generate heat whichcauses the aluminum layer to ablate further until theprobe location is reached, representing the minimum pathof resistance to the high-voltage supply. A more detailedstudy, however, reveals a more intricate process.

Figures 15 through 17 show a detailed view ofthe initial breakdown area and the staring point of themeandering "tree" pattern that was observed on the chipsurface. Figures 16 and 17 were obtained by dicing thechip along one of the "branches" of the "tree" pattern. InFig. 16, the initial breakdown can be seen, revealing asimilar structure as the breakdown shown in Fig. 12.Again, a penetration of the oxide layer combined with asignificant disturbance of the various layers of the chip(aluminum, oxide, polysilicon and silicon substrate) canbe observed, leading to the observed short. Just to theright of the initial breakdown area seen in Fig. 16,

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Fig. 15: Close-up of Initial Breakdown Location inFig. 14.

Fig. 16: Side-View of Initial Breakdown Area shown inFig. 15

i'Seeiiadarv. Brtaktlovms

Si Substrate

ee 034 l e . e k v xa .aek"aJFig. 17: Side-View of Conductive Channel Segment,located to the right of Formation shown in Fig. 16.

however, along one of the surface breakdown "treebranches", additional penetrations of the oxide and cavitiesformed inside the silicon substrate can be noted. Thispattern continues if one were to progress further to theright of the location shown in Fig. 16, as seen in Fig.17. Clearly, a large penetration of the oxide can be notedin the right half of the picture. Additional cavities appearto be sealed by the oxide layer, however, it should benoted that dicing further into the chip may have revealedthese cavities to be "open" as well, thus quite possiblyrepresenting oxide penetrations as well. Thus, theprocess forming the meandering "tree" pattern on thesurface of this chip is clearly not a sole surfacephenomenon, but involves subsurface events as well.

Similar erosion patterns have previously beenobserved by Klein12 during breakdown tests performed onthermal oxides. Klein termed these types of breakdowns"propagating breakdowns" and offered an explanation fortheir occurrence. According to Klein12, the breakdownstarts at a single location, as observed in our experimentsalso. Due to the Joule heat produced by this initialbreakdown conductivity of the insulator material may beslightly lowered in the vicinity of the initial breakdownlocation, causing another breakdown to occur in an areaimmediately surrounding the initial breakdown location.The process now continues, causing the "tree branch"pattern to form. Since, as was noted in this study, acurrent of approximately 0.5 mA is constantly flowingbetween the two electrodes during this erosion process, a(however minute) voltage drop is expected to occur alongthe uneroded aluminum pad area, extending from a highvalue at the location of the contacting probe tip to a lowvalue in the proximity of the eroded pad edge. Thus, apreferential direction is given for subsequent breakdownsto occur (towards higher voltage values) until one of the"tree branches" finally connects with the probe tiplocation.

It should be noted that the observed surfaceerosion process could have been stopped anytime after theinitial breakdown and the low voltage short would stillhave been observed, as was demonstrated in various testruns. Thus, although dramatic in appearance, andrevealing interesting characteristics of the breakdownprocess, this surface erosion process is ratherinconsequential regarding assessing oxide performance asan insulator material since the damage (shorting of theoxide) has already been done just after the initialbreakdown.

Another interesting breakdown pattern can beobserved in Figures 18 through 21. Figures 18 and 19show a chip featuring an oxide thickness of 1 |lm after a

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Multiple Breakdowns Al

Si Substrate

C H I P #59 ; ; : ; ; • , : : : : ; : : : ; . ; : ; • ; : : - j80 ass 10. e k v x s a 0'Fig. 18: Example of Multiple Breakdown Locations for

Thin Oxides (1 (im).

•̂ ^^^^ •̂̂ •̂ ••••̂ •̂ ••••••̂ •l̂ MaiHIMIBMI

Fig. 19: Close-up of Breakdown in Fig. 18.

00 059 i 0 , f8k V X I 0 0 30gijJtt tFig. 20: Multiple Breakdowns for 1 |im Oxide. Note

preferred Breakdown Locations on Aluminum Pad Edgeand Corner.

Fig. 21: Close up of Corner Breakdown and NeighboringBreakdowns of Fig. 20.

750 V breakdown. As can be seen, multiple breakdownlocations can be recognized distributed over an area thatwas again located close to the contact pad edge. Severalbreakdowns had again occurred very near to this edge. InFigs. 20 and 21 another breakdown of a 1 |im oxide chipis shown. This chip broke down at 750V also, however,this test was performed at 205 C (all previous chipsdiscussed in this section were tested at ambienttemperature, about 23 C). Again, multiple breakdownlocations can be noted, many of them close to or on thecontact pad area edge, with one breakdown occurring atone corner of the pad (see Fig. 21). All breakdowns againpenetrate the silicon oxide layer deep into the siliconsubstrate and causing the already previously noted severedisturbance of the chip material in this area, again leadingto a permanent short after breakdown. Current and voltagecharacteristics for the shorts in 1 |J.m chips were around0.3 - 0.4 mA and with voltages ranging mostly around0.15 V to about 12 V, with one value being as high as150V. The breakdown patterns shown in Figs. 18 and 20did not occur instantaneously, but required time todevelop, with arcing starting near the edge or corner of thecontact pad, and then progressing inward towards theprobe tip location. In the case of the chip shown in Fig.18, this process stopped on its own after reaching thestate depicted in the figure. Current and voltagecharacteristics for these chips during this arcing processwere around 0.3 mA and 400 V, and thus, as for the caseof the shorts, slightly lower than in the case of thickeroxides.

Again, this type of breakdown pattern has beenobserved before by Klein12 in his study of dielectricstrengths of thermal oxides and was attributed by Klein to

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the same thermally triggered breakdown process asdescribed above. However, the different appearances of thetwo classes of propagating breakdown patterns shown inFigs. 14 and 18 and 20, respectively, warrant a closerexamination. One obvious difference between the chipsexhibiting these different propagating breakdownbehaviors is the much smaller oxide thickness (1 |J.m vs.2.7 \im) in the case of the chips shown in Figs. 18-21vs. the chip shown in Fig. 14. Several tests wereperformed to examine how breakdown patterns forintermediate oxide thicknesses would appear. The resultsof one of these tests is shown in Fig. 22. The breakdownpattern exhibited on this chip appears to be somewhat ofa cross between the two classes identified above: Whilemultiple, separated breakdowns did occur near the edge,almost all of these breakdowns show rudimentary "tree"growth emanating from the breakdown locations.

We believe an explanation for this behavior maybe found in the different thermal conduction processes inchips of different oxide thicknesses. Silicon dioxide is apoor thermal conductor when compared to silicon, thethermal conductivity being 1.4 W/mK in the case ofoxide versus about 150 W/mK for silicon. Given that thedestruction found underneath the initial breakdownlocations involves the silicon substrate, heat conductionaway from the initial breakdown site can occur boththrough the oxide as well as through the silicon. Someportion of the heat will be conducted radially outwarddirectly through the oxide layer, while another portionwill be conducted through the silicon and, from positionsradially further outward from the initial breakdownlocation, maybe directed partially back into the oxidelayer as this layer is being heated from the underlyingsilicon substrate. For thinner oxides a larger fraction ofheat may thus be received faster at locations further awayfrom the original breakdown location by conductionthrough the silicon substrate, which in turn could lead tobreakdowns further away from the initial breakdown site.Since those locations closer to the high-voltage probe tipwill carry the majority of the current as it seeks its pathof lowest resistance, the current passing through theoriginal breakdown site may subside and no additionalbreakdowns in its immediate neighborhood, as shown inFig. 16, may occur. The ultimate location of theindividual breakdowns, apart from the temperature profile,may then be determined by small variations in oxidethickness or inhomogenities on the contact metal surface.Since again a current is constantly flowing between thetwo electrodes (polysilicon and aluminum), as observed inthese experiments, a voltage drop will again extend fromthe high-voltage probe tip location on the aluminum padto its eroded edge and thus again provide a preferential

Fig. 22: Multiple Breakdowns for Chip featuring 1.5 |imOxide. Note Fewer Breakdowns and Start of Channel

Formations.

direction for further breakdowns, until the position of thehigh-voltage probe tip has been reached.

As in the case of the previously discussed classof breakdowns, it can be stopped immediately after initialbreakdown by turning off the voltage. Since a short hasalready occurred, any further damage observed on the oxidesurface is inconsequential as far as the insulating abilityof the oxide is concerned.

V. SURFACE BREAKDOWN TESTS

Dependence on Gap Distance

As was noted in the Introduction and indicated inFig. 1, in an ion engine accelerator grid arcing may alsooccur along the insulator oxide surface. Previous testsperformed by the authors under atmospheric conditions4

had led to parasitic surface breakdowns when performingsubstrate breakdown tests. The resulting surfacebreakdown voltages were a troublesome 2V/|lm over gapdistances of about 200 to 300 p.m. Surface breakdownfield strengths that low, if applied over a 5 micron thickoxide layer (corresponding to roughly the maximum LTOoxide thickness that can be deposited), would be whollyinsufficient for ion engine grid applications. Thus, a morethorough investigation of surface breakdowns along LTOoxide surfaces was conducted. These tests were performedin a vacuum system, as outlined in Section HI. Unlessotherwise notes, breakdown tests were performed at avacuum pressure of 3 x 10"5 Torr.

Given the low measured breakdown field strengthin earlier experiments4, initial tests were performed withcontact pads separated by a gap distance of 100,200, 300,

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400, 500, and 600 |0.m in order to be able to adjustvoltages delivered by the high-voltage power supplyaccurately enough. Results obtained from these tests areshown in Fig. 23. As can be seen, surface breakdownelectric field strengths range from around 20 V/pm at a100 |im gap distance to as little as 3-4 V/\im at a 600|0.m gap distance between the aluminum pads. At valuesbetween 200 - 300 |im, electric breakdown field strengthsare around 10 V/|im, thus clearly higher than forbreakdown under atmospheric conditions.

Even these increased breakdown field strengths,however, were still too low for ion engine gridapplications. Suspicions were raised that the use ofaluminum, which has a tendency to form hillocks on itssurface, may have led to decreased voltage stand-offcapability as a result of these surface roughnesses20.Aluminum had been used in the design of these test chipsbecause of it being readily available in our cleanroomfacilities, ease of use in the microfabrication process, pastexpansive experience with its use as a MEMS material,as well as good sticking abilities. In addition, Osburn andOrmond10, in performing experiments aimed atdetermining substrate breakdown field strengths forthermal oxides, had tested various electrode materials,including aluminum and molybdenum, and had found nodifference in breakdown behavior.

To resolve remaining doubts and uncertainties,however, chips using molybdenum contact pads werefabricated. In addition, due to the noted slight increase inbreakdown field strength for the chips using aluminumpads, the mask design for the molybdenum chips waschanged and now, in addition to gap distances of 100,200, and 300 urn, included gap distances of 5, 10, and 20\im to perform tests at these lower gap distances as well.The obtained data are also plotted in Fig. 23 (opensquares) and represent the steeply inclined part of thecurve. Two remarkable findings are to be noted: First, intesting molybdenum chips at a 100 (im gap distance, itwas noted that there is no apparent difference in surfacebreakdown field strength when compared with chipsfeaturing aluminum contact pads. Data for the 100 |j,mgap distance for both types of contact pads almost overlapidentically at around 20 V/fim. These results obtained forsurface breakdown experiments on LTO oxides thusmirrors experiences gained with substrate breakdowns forthermal oxides.

Secondly, when decreasing the gap distancefurther, a remarkable increase in breakdown field strengthcan be noted. At least three measurements were taken foreach gap, with results repeating each other withcomparably little scatter in data. This increase in surface

Surface Breakdown Electric Field Strengths vs. Gap Distancefor Aluminum and Molybdenum Contact Pads

200 300 400Contact Pad Gap Distance (}im)

500

Fig. 23: Surface Breakdown Electric Field Strengths forLTO Oxide using Aluminum and Molybdenum Contact

Pads vs. Pad Gap Distance

breakdown field strength towards lower gap distances thusmirrors a similar behavior found for substrate, or bulk,breakdown of many other oxides (compare with Fig. 8).Note that two separate curve fits were used, one for themolybdenum data, another for the aluminum data, yetboth curves appear to match very well.

This increase in electric breakdown field strengthis encouraging, however, still not quite sufficient for ionengine accelerator grid use, as can be seen by inspectingFig. 24. For gap distances of 5 Jim, representing theapproximate maximum LTO oxide thickness that can bedeposited, breakdown voltages remain at around 700 V.Consequently, new approaches are being explored. A newset of surface breakdown test chips was fabricatedfeaturing an oxide undercut extending below the(molybdenum) contact pad (see Fig. 25). This undercut is

6000 J

5000 •

,,4000

o>3000

Surface Breakdown Voltages vs Gap Distancefor Aluminum and Molybdenum Contact Pads

o Aluminum Contact PadD Molybdenum Contact Pad

300 600Contact Pad Gap Distance rjim)

Fig. 24: Surface Breakdown Voltages for LTO Oxidesusing Aluminum and Molybdenum Contact Pads vs. Pad

Gap Distance

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Fig. 25: Photo of Attempt to Achieve Oxide Undercut ofMolybdenum Pad.

hoped to accomplish (1) an increased breakdown surfacepath, thus increasing surface breakdown voltages, inactual grid applications and (2) eliminate the sharp 90°edge of the pad in direct contact with the oxide, thushopefully decreasing local field strengths and thereforedelaying the onset of breakdown to larger voltages. Thischip design was obviously influenced by cold cathodedesigns. Using similar designs, Spindt20 has reportedbreakdown voltages of up to 250 V/jiim and more.Currently, tests with these types of chips are still inprogress. The first set of chips using the described layoutdid not perform according to expectations. Measuredbreakdown voltages were about half the value of fieldstrengths obtained for molybdenum chips not featuring anundercut. During fabrication of the chip featuring theundercut, however, it was noted that the etchant used toremove the oxide also seemed to attack the molybdenumcontact pad to some degree. This could have led to aroughening of the molybdenum surface, which couldaccount for the lower than expected breakdown fieldstrengths observed with this set of chips. Fabricationprocess optimization is continuing.

Paschen Breakdown Considerations

As process development for the fabrication ofchips featuring oxide undercuts is continuing, additionalexperiments were performed to eliminate other potentialmechanisms that might have influenced obtained results.One experiment was conducted to determine the influenceany remaining rest gases in the vacuum system mighthave had on the measurements, if any. In Fig. 26,breakdown voltages are plotted versus the product of gaspressure inside the vacuum system and gap distance.Using this representation, if arcing through the rest gaswould have been present, a Paschen-type curve should

2400

baooo

£ 1800 )

1200-i

Breakdown Voltage vs. Product ol Pressure and Gap Distance100 um Constant Gap Distance

Aluminum Contact Pads

8 1 " " ••"'{ ' ' " 'i""l I S f S S I10'7 10''Pressure'Gap Distance (pd) (Torr cm)

Fig. 26: Breakdown Voltages for Constant Gap Distanceat Various Background Pressures

have resulted. All measurements were performed at a gapdistance of 100 |J.m and pressure was varied by takingmeasurements at various stages during the pump downprocess. This allowed for measurements at pressuresranging between 10"4 Torr to as low as 10'6 Torr.Accordingly, pressure/gap distance products are extremelylow, ranging between 10"8 Torr cm to 2 x 10"6 Torr cm.Typically, these values would indicate a position far toothe left of the minimum of the Paschen curve forcommonly used gases that could have been present in thechamber (nitrogen, oxygen, water vapor traces). At thesevalues, if a Paschen breakdown would have been present,breakdown voltages should have been much higher thanobserved and should have decreased dramatically towardslarger pressure/gap product values. In inspecting Fig. 26,however, it is clear that this is not the case. No particulartrend is visible among the data points and only the usualscatter of the data, as observed for measurements taken atconstant pressure and gap distance as well (see Fig. 24),can be noted. Thus, it was concluded that the surfacebreakdowns observed were likely true surface effects.

Influence of Surface Morphology

During early surface breakdown measurements,chips fabricated from wafers featuring a thick 3.9 ^imoxide were used for reasons explained in Section III. Inthe course of these experiments it was discovered thatdroplet-shaped surface features were present all over thechip, and thus in the gap area as well (see Figs. 27 and28). Feature sizes ranged between 3 |im (Fig. 27) and lessthan 1 \im (Fig. 28) in diameter. Naturally, it was fearedthat these features could have had an influence on theobtained data and be at least partly responsible for the lowsurface breakdown strengths. It was quickly determined,through a combination of X-ray fluorescence spectral

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Fig. 27: Example of Stress-Induced Surface Delamination(approx. 3 |im dia.) on Oxide.

Fig. 28: Example of Stress-Induced Surface Delamination(less than 1 (O.m dia.) on Oxide.

surface densities in the gap area were calculated. Thesedensities are believed to be accurate within less than 10%or so, since counting this great a multitude of featureslead to miscounts, in particular since in some cases chipshad already been tested and debris resulting fromaluminum pad erosion had to be discerned from surfacedelaminations. However, this accuracy is believed to besufficient, considering that a very wide range of surfacedelamination densities, ranging from zero to as high as4000/mm2 were obtained.

Figure 29 shows the results for three gapdistances: 100, 200 and 300 (im. No particular trend ofbreakdown field strength with respect to delaminationdensity can be observed for either of the gap distances.The scatter in breakdown field data appears somewhat lesspronounced for lower delamination densities, butdifferences remain small. There definitely appears to be notrend towards lower breakdown field strengths at higherdelamination densities. As a matter of fact, as can be seenfor the data obtained for the 100 (j,m gap, the breakdownvalue obtained for the largest delamination surface densityis larger than all other data obtained.

Therefore, it was concluded that surfacemorphology of the type observed in Figs. 27 and 28 didnot affect breakdown strengths. This is an importantfind, in particular with respect to ion engine acceleratorgrid applications, were sputter erosion may lead to surfaceroughening. However, it should be pointed out that theparticular surface features encountered here have relativelysmooth shapes and comparably large radii of curvaturecompared with the intrinsic silicon oxide surfaceroughness as observed in Figs. 27 and 28.

analysis, as well as various standard cleaning techniques,that the surface features were not contaminations resultingfrom organic residue, photoresist, or else, but, instead,were stress delaminations caused by the large intrinsicstresses in the thick LTO layer. Consequently, wafersfeaturing thinner oxides (2 |J.m) were fabricated and usedin subsequent tests.

However, using these chips, an unexpectedopportunity presented itself to study the influence oxidesurface morphology might have on surface breakdowncharacteristics. Chips of the original 3.9 |4.m LTO batch,chips fabricated by UCLA using a 2.7 \im oxidefeaturing fewer delaminations, as well as the latestBerkeley batch using 2 (im oxide having no detectabledelaminations, were tested and data obtained werecompared. All surface delaminations inside the gap areawere counted under an optical microscope and average

30-

I2°J<D

CO

I15

E

I 10-

£m 5

0 -

Breakdown Field Strength vs. Density of Surface DelaminationsPressure: 3x10 Torr

o 100 nm GapV 200 tim Gap* 300 pmGap

1000 2000 3000 4000Avg. Density of Surface Delaminations (I/mm2)

Fig. 29: Breakdown Field Strength vs. SurfaceDelamination Density

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Visual Post-Test Inspection of Test Samples

All surface breakdown test samples appeared verysimilar after breakdown. Examples of two chips imagedafter breakdown are shown in Figs. 30 and 31. Both chipsfeatured aluminum contact pads and a gap distance of 100|4.m. Arcing occurred preferentially at the corners of thepad area, but also at straight edge sections. Depending onthe intensity of the arcing, usually well correlated withthe magnitude of the breakdown voltage, isolated burnmarks, as in Fig. 30 (breakdown at 2100V, or 21V/^m),or extensive erosion along the entire pad edge, as in Fig.31 (breakdown at 3200V or 32 V/|^m), can be observed.Damage is typically more intensive on the negative pad(shown in the left of both Figures) than on the positivepad. It is not certain what the cause for this behavior is,

however, electron field emission from microscopic tipsalong the negative pad edge may have lead to localheating and thus increased erosion. An example of an(uneroded) aluminum contact pad edge can be seen in Fig.32. Tips protruding from the edge are small (approx. lessthan a few tenths of microns, representing state-of-the-artmicrofabrication/patterning technology), however, aresharply pointed. Finally, Fig. 33 shows the erodednegative pad area of a molybdenum pad. Molybdenumthickness was about 0.05 (im and thus the damage wasmore severe.

Fig.30: Example of Contact Pad Damage after SurfaceArc Breakdown (Arcing Voltage was 2100 V, Gap

lOOjim)

Fig.32: Close-up of Aluminum Pad Edge

Fig. 31: Example of Contact Pad damage after SurfaceArc Breakdown (Arcing Voltage was 3200 V, Gap

100 (im)

Fig. 33: Post-Test Scan of Molybdenum SurfaceBreakdown Chip

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VI. CONCLUSIONS AND GRID DESIGNIMPLICATIONS

Microfabricated ion accelerator grids are beingconsidered for micro-ion engines due to the unrivaledprecision with which these components could be builtusing MEMS fabrication techniques. In particular forgrids, requiring a multitude of closely spaced apertureswithin tight tolerances to provide for proper grid holealignment and beam extraction, these considerationsweigh heavily in view of the small overall dimensions tobe encountered for micro-ion engines. However,fabrication of these grids will require the use of newmaterials, typically not used in the fabrication ofconventional grids.

Among the material properties to be studied isthe dielectric strength of grid insulator materials. One ofthe most popular insulator material used in the MEMSarea is silicon dioxide. Most work in the past however,was focused on the evaluation of thin thermal oxides foruse as gate oxides in MOSFETs. While these oxidesshow excellent electric breakdown field strengths for thinlayers, thermal oxide, due to its growth process, cantypically only be grown up to thicknesses not exceeding2 (im. Over these thicknesses, the total voltage that canbe stood off is marginal with respect to ion engine gridapplications. On the other hand, CVD deposited LTOoxide can be deposited up to thicknesses of possibly 5|im. However, many details of the dielectric properties ofLTO oxides, in particular for very thick films, and atelevated temperatures, were not known. Thus, a thoroughinvestigation of these properties was initiated. Results ofthis evaluation remain mixed at this point of theinvestigation.

On the one hand, substrate, or bulk, electricbreakdown properties of LTO oxide are excellent.Voltages as high as 2500 V could be stood off over oxidethicknesses of 3.9 |J.m, providing more than sufficientmargins of safety for grid applications. In addition, thereare strong indications that the oxides used show little tono defects that could lead to premature electric breakdown,as breakdowns usually occurred near contact pad edges,rather than being randomly distributed, as would beexpected if a random distribution of defects would havecaused breakdowns to occur. No adverse temperatureeffects with respect to breakdown strengths were noted forLTO oxides either. Although a small drop in breakdownstrength was measured for a 1 urn thick oxide sample,decreases in breakdown strength are small (approximately15%) when increasing temperatures from ambient to 400C. Breakdown voltages obtained compare very favorablyto corresponding literature data found for other oxides,

such as thermal and sputter deposited oxides. In the caseof thermal oxides this is mainly due to the comparativleylarger LTO oxide thicknesses that can be deposited.

On the other hand, surface breakdown propertiesstill appear inappropriate. Although it was discovered thatsurface breakdown electric field strengths increasesignificantly with smaller gap distances, reaching amaximum of 140 V/|im for 5 |0,m, obtainable voltagesover these distances remain relatively small (i.e. 700 V).

New grid/insulator geometries are therefore beingexplored, based on past research on cold cathodes. Sincebreakdowns tended to occur predominantly along contactpad edges and near corners, it is evident that the fieldconcentration at these locations does play a major role inoxide breakdowns. Chips with oxide undercuts, extendingunderneath the contact pad edges have been fabricated.Similar electrode/insulator configurations featuring oxideundercuts have been used in cold cathode arrays in the pastand shown good breakdown characteristics, up to 250V/|am. In addition, the oxide undercut would lengthen thedistance between electrodes when traveling along theoxide surface, thus providing additional margin inbreakdown voltages. Initial results obtained in this studywith this type of chip, however, were not tooencouraging, likely due to processing difficulties in thefabrication of these chips as a result of oxide etchantspotentially attacking the molybdenum pads. Further workwill be performed in this area.

VII. ACKNOWLEDGEMENTS

The authors would like to thank Ms. EuniceKoo and Mr. James Bustillo of the MicrofabricationLaboratories at the University of Berkeley, as well as Mr.Kevin Tsing of the University of California/Los Angeles(UCLA) for performing the polysilicon and oxide growthprocessing steps for the wafers used in the experiment.

The research described in this paper was carriedout by the Jet Propulsion Laboratory, California Instituteof Technology, under a contract with the NationalAeronautics and Space Administration.

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