microprocessor i - lecture 06draelshafee.net/fall2019/microprocessor-i---lecture-06.pdf · 80286...

Lecture (06)

By:

Dr. Ahmed ElShafee

Dr. Ahmed ElShafee, ACU : Fall 2019, Microprocessors 11

The Flag Register

• A (Auxiliary) [half carry]

• C (carry): [result exceeds the size of distination]

• O (overflow): [something went wrong]

• P (Parity) [even number of ones]

• S (sign): [MSB =1]

• Z (zero): [==0]

NT

14

IOP1

13

IOP0

12

O

11

D

10

I

9

T

8

S

7

Z

6

A

4

P

2

C

0

VIF

19

AC

18

VM

17

RF

1631

ID

21

VIP

20

8088/8086

80286

80386

80486

Pentium

Carry Flag

• 1. The carry flag is set if the addition of two numbers causes a carry out of the most significant (leftmost) bits added.

• 1111 + 0001 = 0000 (carry flag is turned on)

• 2. The carry (borrow) flag is also set if the subtraction of two numbers requires a borrow into the most significant (leftmost) bits subtracted.

• 0000 ‐ 0001 = 1111 (carry flag is turned on) Otherwise, the carry flag is turned off (zero).


Overflow Flag

• 1. If the sum of two numbers with the sign bits off yields a result number with the sign bit on, the "overflow" flag is turned on.

0100 + 0100 = 1000 (overflow flag is turned on)

• 2. If the sum of two numbers with the sign bits on yields a result number with the sign bit off, the "overflow" flag is turned on.

1000 + 1000 = 0000

(overflow flag is turned on) Otherwise, the overflow flag is turned off.



Arithmetic and Logic Instructions• Addition: (Flags affected: A,C,O,P,S,Z)

– ADD AL,BL ; AL AL + BL , BL unchanged

• Register addressing mode

– ADD CX,DI ; CX CX + DI , DI unchanged


– ADD AH,45H ; AH AH + 45H

• Immediate addressing mode

– ADD [BX],AL ; [BX] [BX] + AL

• Register indirect addressing mode

– ADD CX,[BX] ; CX CX + [BX]

– ADD AL,CX ; INVALID


Add with Carry: (Flags affected: A,C,O,P,S,Z)

– ADC AH,BH ; AH AH + BH + Carry


– ADC AX,CX ; AX AX + CX + Carry


– ADC AL,[BX+SI] ; AL AL + [BX+SI] + Carry



Subtraction: (Flags affected: A,C,O,P,S,Z)

– SUB AL,BL ; AL AL - BL ;BL unchanged


– SUB CX,DI ; CX CX - DI ;DI unchanged


– SUB AH,45H ; AH AH - 45H

• Immediate addressing mode

– SUB BL,ARRAY ; BL BL - [ARRAY]

• Direct Addressing mode

– SUB [BX],AL ; [BX] [BX] – AL


– SUB AL,CX ; INVALIDDr. Ahmed ElShafee, ACU : Fall 2019, Microprocessors 18

Subtract with Borrow: (Flags affected: A,C,O,P,S,Z)

– SBB AH,BH ; AH AH - BH – Carry


– SBB AX,CX ; AX AX - CX – Carry


– SBB AL,[BX+SI] ; AL AL - [BX+SI] – Carry



Increment: (Flags affected: A,O,P,S,Z)

– INC AL ; AL AL + 1

– INC SP ; SP SP + 1

– INC COUNT1 ; [COUNT1] [COUNT1] + 1

– INC BYTE PTR[BX] ; [BX] [BX] + 1

– INC WORD PTR[BX] ; [BX] [BX] + 1


Example 01

•


org 100h jmp start db 0feh,00hstart:mov bx,0102hINC BYTE PTR[BX] INC BYTE PTR[BX]

ret

org 100h jmp start db 0feh,00hstart:mov bx,0102hINC BYTE PTR[BX] INC WORD PTR[BX]

ret



Decrement: (Flags affected: A,O,P,S,Z)

– DEC AL ; AL AL - 1

– DEC SP ; SP SP - 1

– DEC COUNT1 ; [COUNT1] [COUNT1] - 1

– DEC BYTE PTR[BX] ; [BX] [BX] - 1

– DEC WORD PTR[BX] ; [BX] [BX] - 1


Example 02

•


org 100h jmp start db 001h,00hstart:mov bx,0102hdec BYTE PTR[BX] dec BYTE PTR[BX]

ret

org 100h jmp start db 01h,00hstart:mov bx,0102hdec BYTE PTR[BX] dec WORD PTR[BX]

ret



Example 03

• What will be the values of the carry, overflow, sign and zero flags after the execution of each of the following instructions:

– MOV DX,0

– DEC DX

– MOV AX,720H

– SUB AX, 0E6H

– MOV DX,0

– DEC DX



• Instruction AX DX Flags

H L H L C Z S OMOV DX,0

DEC DX

MOV AX,720H

SUB AX, 0E6H


• Instruction AX DX Flags

H L H L C Z S OMOV DX,0 00 00 0 0 0 0DEC DX FF FF 0 0 1 0

MOV AX,720H 07 20 ‐ ‐ ‐ ‐SUB AX, 0E6H 06 3A 0 0 0 0

Example 04

MOV AX,847AH

SUB CX,CX

MOV BX,5CE8H

ADD AL,BH

ADC AH,BL

MOV CL,AL

ADD CH,BL

MOV SI,0108H

SUB BL,[SI]

SBB BH,[SI+4]

ADD AL,[010CH]

MOV AX,[0106H]

INC AL

DEC BX

ADD CX,[SI+4]


Fill up the trace table given below.

CS:0108H 02CS:0106H E8CS:0107H 5CCs:010CH 8ACS:010DH C8

•


InstructionAX BX CX SI Flags

H L H L H L C Z S OMOV AX,847AHSUB CX,CXMOV BX,5CE8HADD AL,BHADC AH,BLMOV CL,ALADD CH,BLMOV SI,0108HSUB BL,[SI] (02)

SBB BH,[SI+4] (8A)

ADD AL,[010CH](8A)

MOV AX,[0106H] (5CE8)

INC ALDEC BXADD CX,[SI+4]

•


InstructionAX BX CX SI Flags

H L H L H L C Z S OMOV AX,847AH 84 7A ‐ ‐ ‐ ‐SUB CX,CX 00 00 0 1 0 0MOV BX,5CE8H 5C E8 ‐ ‐ ‐ ‐ADD AL,BH D6 0 0 1 1ADC AH,BL 6C 1 0 0 1MOV CL,AL D6 ‐ ‐ ‐ ‐ADD CH,BL E8 0 0 1 0MOV SI,0108H 0108 ‐ ‐ ‐ ‐SUB BL,[SI] (02) E6 0 0 1 0SBB BH,[SI+4] (8A) D2 1 0 1 1ADD AL,[010CH](8A)

60 1 0 1 1

MOV AX,[0106H] (5CE8)

5C E8 ‐ ‐ ‐ ‐

INC AL E9 ‐ 0 1 0DEC BX D2 E5 ‐ 0 1 0ADD CX,[SI+4] (C88A) B1 60 1 0 1 0


Thanks,..


microprocessor i - lecture 06draelshafee.net/fall2019/microprocessor-i---lecture-06.pdf · 80286...

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