MICROPROCESSORS AND MICRO CONTROLLERS

PRE-FINAL SOLUTIONS

1. a. why the memory is segmented in 8086 processor. Explain overlapping and non overlapping segments.

The need of memory segmentation is explained below:

The 8086 has a 20 bit address bus , but let us remember that we have not seen any 20 bit

registers so far . .It is understandable that the general purpose registers are used as 16 bit

or 8 bit registers ,as this is the way data is organized. But we see that all the address

registers also are 16 bit . An ingenuous idea called segmentation has been used to take

care of this situation. A segment is just an area in memory . Thus the total memory size

can be considered to be divided into segments of various sizes . The idea of dividing

memory this way is called segmentation

In memory ,data is stored as bytes. Each byte has a specific address. With 20 address lines ,the

memory that can be addressed is 220 bytes. This will amount to 1,048,576 bytes (1 Megabyte).

Thus the 8086 can access a physical memory with addresses ranging from 00000H to FFFFFH

.A 20 bit physical address is to be placed on the address bus to access any location in memory.

Memory as a whole is considered to have four different types of segments

labeled as data, code ,stack and extra. One idea of segmentation is to keep data and code

separately . Thus the code segment contains code only . Data is stored in the data

segment ,and the extra segment is just another type of data segment used in a special way.

The stack segment is an area of memory which functions and is accessed differently

from the other three segments

1. The BIU (Bus Interfacing Unit) contains four special purpose registers called as

segment registers. These are Code Segment (CS) register, Stack Segment (SS) register,

Extra Segment (ES) register and Data Segment (DS) register.

2. All these are 16 bit registers.

3. The number of address lines in 8086 is 20. So the 8086 BIU will send out a 20 bit

address in order to access one of the 1,048,576 or 1MB memory locations.

4. But it is interesting to note that the 8086 does not work the whole 1MB memory at any

given time. However it works with only four 64 KB segments within the whole 1 MB

memory.

5. The four segment registers actually contain the upper 16 bits of the starting addresses

of the four memory segments of 64 KB each with which the 8086 is working at that

instant of time.

6. A segment is a logical unit of memory that may be up to 64 kilo bytes long.

7. Each segment is made up of memory contiguous memory locations. It is independent,

separately addressable unit.

8. Starting addresses will always be changing. They are not fixed.

9. Figure shows one of the possible ways to position the four 64 KB segments within the

1 MB memory space of 8086.

1. There is no restriction on the locations of these segments in the memory. These

segments can be separate from each other or they can overlap.

2. In the users program there can be many segments but 8086 can deal with only four of

them at any given time because it has only four segment registers.

3. Whenever the segment orientation is to be changed, the base addresses have to be

changed and load the upper 16 bits into the corresponding segment registers.

4. Segment registers are very useful for large programming tasks that require isolation of

program code from the data code or isolation of module data from the stack

information etc.

5. Segmentation builds relocatable and re-entrant programs easily. In many cases the task

of relocating a program simply requires moving the program code and then adjusting

the code segment register to point to the base of the new code area.

Advantages of memory segmentation:

1. Segmentation provides a powerful memory management mechanism.

2. It allows programmers to partition their programs into modules that operate

independently of one another.

3. Segments allow two processes to easily share data.

4. It allows to extend the address ability of a processor i.e. segmentation allows the use of

16 bit registers to give an addressing capability of 1 MB. Without segmentation, it

would require 20 bit registers.

5. Segmentation makes it possible to separate the memory areas for stack, code and data.

The maximum size of any segment can grow upto only 64 KB. However, on one hand the use of fixed segment areas for code, data and its stack helps in better utilizing the memory for large program, but if the segment is underutilized for reason of less amount of data, code or stack data then it leads to wastage of memory. So to overcome this problem, a concept of having multiple and overlapping segments was conceived. This permits us to fill the unutilized part of a segment to be overlapped with another code, data or stack segment. This new and overlapping segment can start at an address within 16 bytes boundary of the end of previous segment. This is shown in figure

The use of the segment registers and hence the segmentation in 8086 offers many advantages: Manipulation of the address contained in segment register and the effective address, permit the memory size to be 1MB.

It allows the size of the program or data to be more than 64 KB by utilizing multiple code or data segments as shown in figure.

The above benefit allows you to keep the separate area of memory for code and data etc.

Calculation of Physical Address: As the EA so formed by adding the index registers, base registers and the displacement is 16 bit, but the physical address that is to be put on the address bus is 20 bit. The extra 4 bits are obtained by appending 4 zeros on the right of segment registers and adding with the effective address (EA) as shown below:

1.b. with neat pin diagram explain 8086 Microprocessor.

It is a 16-bit μp.

•8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).

•It can support up to 64K I/O ports.

•It provides 14, 16 -bit registers.

•It has multiplexed address and data bus AD0- AD15 and A16 – A19.

•It requires single phase clock with 33% duty cycle to provide internal timing.

•8086 is designed to operate in two modes, Minimum and Maximum.

•It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up

instruction execution.

•It requires +5V power supply.

•A 40 pin dual in line package

The following signal descriptions are common for both modes.

•AD15-AD0: These are the time multiplexed memory I/O address and data lines.

• Address remains on the lines during T1 state, while the data is available on the data bus during

T2, T3, Tw and T4.

•These lines are active high and float to a tristate during interrupt acknowledge and local bus

hold acknowledge cycles.

•A19/S6,A18/S5,A17/S4,A16/S3: These are the time multiplexed address and status lines.

•During T1 these are the most significant address lines for memory operations.

•During I/O operations, these lines are low. During memory or I/O operations, status information

is available on those lines for T2,T3,Tw and T4.

•The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.

•The S4 and S3 combinedly indicate which segment register is presently being used for memory

accesses as in below fig.

•These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is

always low.

•The address bit are separated from the status bit using latches controlled by the ALE signal..

BHE/S7: The bus high enable is used to indicate the transfer of data over the higher order ( D15-

D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to

derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read,

write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of

data bus. The status information is available during T2, T3 and T4. The signal is active low and

tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledges cycle

READY: This is the acknowledgement from the slow device or memory that they have

completed the data transfer. The signal made available by the devices is synchronized by the

8284A clock generator to provide ready input to the 8086. the signal is active high.

•INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles

of each instruction to determine the availability of the request. If any interrupt request is pending,

the processor enters the interrupt acknowledge cycle.

•This can be internally masked by resulting the interrupt enable flag. This signal is active high

and internally synchronized.

•TESTThis input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will

continue, else the processor remains in an idle state. The input is synchronized internally during

each clock cycle on leading edge of clock.

•CLK- Clock Input: The clock input provides the basic timing for processor operation and bus

control activity. Its an asymmetric square wave with 33% duty cycle.

•MN/MX: The logic level at this pin decides whether the processor is to operate in either

minimum or maximum mode.

•The following pin functions are for the minimum mode operation of 8086.

•M/IO – Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When

it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the

CPU is having a memory operation. This line becomes active high in the previous T4 and

remains active till final T4 of the current cycle. It is tristated during local bus “hold acknowledge

“.

•INTAInterrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge

cycles. i.e. when it goes low, the processor has accepted the interrupt.

•ALE – Address Latch Enable: This output signal indicates the availability of the valid address

on the address/data lines, and is connected to latch enable input of latches. This signal is active

high and is never tristated.

•DT/R – Data Transmit/Receive: This output is used to decide the direction of data flow

through the transreceivers (bidirectional buffers). When the processor sends out data, this signal

is high and when the processor is receiving data, this signal is low.

•DEN – Data Enable: This signal indicates the availability of valid data over the address/data

lines. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from the

multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is

tristated during ‘ hold acknowledge’ cycle.

•HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to the processor

that another master is requesting the bus access.

•The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA

pin, in the middle of the next clock cycle after completing the current bus cycle.•At the same

time, the processor floats the local bus and control lines. When the processor detects the HOLD

line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be

externally synchronized.

LOCKThis output pin indicates that other system bus master will be prevented from gaining the

system bus, while the LOCK signal is low.

•The LOCK signal is activated by the ‘LOCK’ prefix instruction and remains active until the

completion of the next instruction. When the CPU is executing a critical instruction which

requires the system bus, the LOCK prefix instruction ensures that other processors connected in

the system will not gain the control of the bus.

•The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which

may be connected to an external bus controller.

•QS1, QS0 – Queue Status: These lines give information about the status of the code-prefetch

queue. These are active during the CLK cycle after while the queue operation is performed.

RQ/0GT,RQ/1GT – Request/Grant: These pins are used by the other local bus master in

maximum mode, to force the processor to release the local bus at the end of the processor current

bus cycle.

•Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.

•RQ/GT pins have internal pull-up resistors and may be left unconnected

5 a) Differences Between SRAM and DRAM

1. SRAM is an on-chip memory whose access time is small while DRAM is an off-

chip memory which has a large access time. Therefore SRAM is faster than DRAM.

2. DRAM is available in larger storage capacity while SRAM is of smaller size.

3. SRAM is expensive whereas DRAM is cheap.

4. The cache memory is an application of SRAM. In contrast, DRAM is used in main

memory.

5. DRAM is highly dense. As against, SRAM is rarer.

6. The construction of SRAM is complex due to the usage of a large number of transistors.

On the contrary, DRAM is simple to design and implement.

7. In SRAM a single block of memory requires six transistors while in DRAM the required

number of the transistor for a single block of memory is just one.

8. DRAM is named as dynamic, because it uses capacitor which produces leakage

current due to the dielectric used inside the capacitor to separate the conductive plates is

not a perfect insulator hence require power refresh circuitry. On the other hand, there is no

issue of charge leakage in the SRAM.

9. Power consumption is higher in DRAM than SRAM. SRAM operates on the principle of

changing the direction of current through switches whereas DRAM works on holding the

charges.

2. Calculate the memory address the following instructions will access. Also explain

the addressing modes that are used by each instruction.

i. MOV CX,[1234] In this direct addressing mode a 16-bit memory address (offset) is directly

specified in the instruction as a part of it.

Memory Address=10*DS+1234

ii.MOV AX,[2222H]

In this direct addressing mode a 16-bit memory address (offset) is directly

specified in the instruction as a part of it.

Memory Address=10*DS+2222

iii.MOV DX,[BP+DI]

This instruction is register base indexed addressing mode. The 20 bit physical address of the

instruction is calculated by adding the addresses of Base pointer and index regiser into

segment address and is given by

PA=10*DS+[BP]+[DI]

Iv. MOV DX,[BP+SI+200h]

This is an direct base indexed addressing mode and 20 bit physical address is

calculated as follows

PA=10*DS+[BP]+[SI]+200H

V.MOV DX,[BP+DI+01H]

This is an direct base indexed addressing mode and 20 bit physical address is

calculated as follows

PA=10*DS+[BP]+[DI]+01H

VI. MOV AX,1234H

This is an immediate addressing mode. 16 bit immediate is directly added to 16

register. The 20 bit physical address is calculated as follows

PA=10*DS+1234H

VII.MOV DX,[BX+04]

This is an register relative addressing mode. The 20 bit physical address ic

calculated by

PA=10*DS+[BX]+01H

3. Explain in details the i.Modes of operation ii.Bit set reset mode iii. Mode set

control words of 8255 programmable peripheral interface

Modes of Operation of 8255 • These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset

mode (BSR).

• In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode

only port C (PC0-PC7) can be used to set or reset its individual port bits.

• Under the I/O mode of operation, further there are three modes of operation of

8255, so as to support different types of applications, mode 0, mode 1 and mode2

.

BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending

on D0 of the control word. The bit to be set or reset is selected by bit select flags

D3, D2 and D1 of the CWR as given in table.

•I/O Modes :

a) Mode 0 (Basic I/O mode): This mode is also called as basic input/output mode.

This mode provides simple input and output capabilities using each of the three ports. Data can be simply read from and written to the input and output ports respectively, after

appropriate initialisation.

4.

5.

4. a. Interface stepper motor to the 8086 microprocessor system and write an

ALP in 8086 to rotate it by 180 degrees.

DATA SEGMENT PORTA EQU 0C800H PORTB EQU 0C801H PORTC EQU 0C802H CWR EQU 0C803H PHA EQU 077H PHB EQU 0BBH PHC EQU 0DDH PHD EQU 0EEH DATA ENDS CODE SEGMENT ASSUME CS: CODE, DS: DATA START: MOV AX, DATA MOV DS, AX MOV DX, CWR MOV AL, 80H OUT DX, AL AGAIN: MOV AL, PHA CALL STEP MOV AL, PHB CALL STEP MOV AL, PHC CALL STEP

MOV AL, PHD CALL STEP MOV BL, 0FFH X: MOV CX, 0FFFFH X1: LOOP X1 DEC BL JNZ X MOV AH, 0BH INT 21H OR AL, AL JZ AGAIN MOV AH, 4CH INT 21H STEP PROC NEAR MOV DX, PORTC 19 OUT DX, AL MOV BL, 60H K1: MOV CX, 0FFFFH K2: LOOP K2 DEC BL JNZ K1 RET STEP ENDP CODE ENDS

END START

4.b. explain the architecture of 8253 programmable interval timer.

The use of dedicated hardware for generating delays and generating waveforms of required

frequencies and pulse widths has solved the above problems.

The chip 8253 is a programmable timer chip used for timing applications. Another chip 8254 is

also available ,which is the same as 8253 ,except that is capable of being operated at higher

frequencies .In fact ,8254 is a superset of 8253 and all programs written for 8253 can be used for

8254.Both these timer chips provide three independent 16 bit timers ,but 8253 can handle clock

inputs of only up to 2.6 MHz ,while 8254 can be used up to 10 MHz. Both chips are available as

24 pin DIP, and the pin diagram is as shown of 8253/8254 in Fig 10-1.In the IBM PC , the 8253

was used initially ,but now in the PC-AT ,the timer chip used is the 8254 which is pin compatible

with 8253. _

Functional block diagram of 8253 /8254 _

5.A.

SRAM vs DRAM

There are two types of Random Access Memory or RAM, each has its

own advantages and disadvantages compared to the other. SRAM

(Static RAM) and DRAM (Dynamic RAM) holds data but in a different

ways. DRAM requires the data to be refreshed periodically in order to

retain the data. SRAM does not need to be refreshed as the transistors

inside would continue to hold the data as long as the power supply is

not cut off. This behavior leads to a few advantages, not the least of

which is the much faster speed that data can be written and read.

The additional circuitry and timing needed to introduce the refresh

creates some complications that makes DRAM memory slower and

less desirable than SRAM. One complication is the much higher power

used by DRAM memory, this difference is very significant in battery

powered devices. SRAM modules are also much simpler compared to

DRAM, which makes it easier for most people to create an interface to

access the memory. This makes it easier to work with for hobbyists

and even for prototyping.

Structurally, SRAM needs a lot more transistors in order to store a

certain amount of memory. A DRAM module only needs a transistor

and a capacitor for every bit of data where SRAM needs 6 transistors.

Because the number of transistors in a memory module determine its

capacity, a DRAM module can have almost 6 times more capacity with

a similar transistor count to an SRAM module. This ultimately boils

down to price, which is what most buyers are really concerned with.

Because of its lower price, DRAM has become the mainstream in

computer main memory despite being slower and more power hungry

compared to SRAM. SRAM memory is still used in a lot of devices

where speed is more crucial than capacity. The most prominent use of

SRAM is in the cache memory of processors where speed is very

essential, and the low power consumption translates to less heat that

needs to be dissipated. Even hard drives, optical drives, and other

devices that needs cache memory or buffers use SRAM modules.

5 b)

In I/O data transfer, data is transferred by using microprocessor. The microprocessor will read

data from I/O device and then will write data to memory.

In this case, there are two operations for single data transfer. If the data is less then

microprocessor will not waste its time transferring data from I/O to memory or back.

But suppose data is huge then the transfer rate from I/O to memory or back will slow

down because of microprocessor intervention.

In such case, to speed up the process of transferring the data, I/O should have direct

access to memory.

It can have Direct Memory Access (DMA) but under supervision. The device which

supervises data transfer is named as DMA controller.

DRQ0−DRQ3

These are the four individual channel DMA request inputs, which are used by the peripheral

devices for using DMA services. When the fixed priority mode is selected, then DRQ0 has the

highest priority and DRQ3 has the lowest priority among them.

DACKo − DACK3

These are the active-low DMA acknowledge lines, which updates the requesting peripheral

about the status of their request by the CPU. These lines can also act as strobe lines for the

requesting devices.

Do − D7

These are bidirectional, data lines which are used to interface the system bus with the internal

data bus of DMA controller. In the Slave mode, it carries command words to 8257 and status

word from 8257. In the master mode, these lines are used to send higher byte of the generated

address to the latch. This address is further latched using ADSTB signal.

IOR

It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal

registers of 8257 in the Slave mode. In the master mode, it is used to read data from the

peripheral devices during a memory write cycle.

IOW

It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to

the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal count

register. In the master mode, it is used to load the data to the peripheral devices during DMA

memory read cycle.

CLK

It is a clock frequency signal which is required for the internal operation of 8257.

RESET

This signal is used to RESET the DMA controller by disabling all the DMA channels.

Ao - A3

These are the four least significant address lines. In the slave mode, they act as an input, which

selects one of the registers to be read or written. In the master mode, they are the four least

significant memory address output lines generated by 8257.

CS

It is an active-low chip select line. In the Slave mode, it enables the read/write operations

to/from 8257. In the master mode, it disables the read/write operations to/from 8257.

A4 - A7

These are the higher nibble of the lower byte address generated by DMA in the master mode.

READY

It is an active-high asynchronous input signal, which makes DMA ready by inserting wait

states.

HRQ

This signal is used to receive the hold request signal from the output device. In the slave mode,

it is connected with a DRQ input line 8257. In Master mode, it is connected with HOLD input

of the CPU.

HLDA

It is the hold acknowledgement signal which indicates the DMA controller that the bus has been

granted to the requesting peripheral by the CPU when it is set to 1.

MEMR

It is the low memory read signal, which is used to read the data from the addressed memory

locations during DMA read cycles.

MEMW

It is the active-low three state signal which is used to write the data to the addressed memory

location during DMA write operation.

ADST

This signal is used to convert the higher byte of the memory address generated by the DMA

controller into the latches.

AEN

This signal is used to disable the address bus/data bus.

TC

It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral

devices.

MARK

The mark will be activated after each 128 cycles or integral multiples of it from the beginning.

It indicates the current DMA cycle is the 128th cycle since the previous MARK output to the

selected peripheral device.

Vcc

It is the power signal which is required for the operation of the circuit.

The sequence of DMA transfer is as follows:

Microprocessor initializes the DMAC (DMA controller) by giving the starting address

and the number of bytes to be transferred.

An I/O device requests the DMAC to perform DMA transfer through the DREQ line.

The DMAC in turn sends a request signal to the microprocessor through the HOLD line.

The microprocessor finishes the current machine cycle and releases the system bus (gets

disconnected from it). It also acknowledges receiving the HOLD signal through the

HLDA line.

The DMAC acquires control of the system bus. The DMAC sends the DACK signal to

the I/O peripheral and the DMA transfer begins.

After every byte is transferred, the address register is incremented (or decremented) and

the count register is decremented.

This continues till the count reaches zero (Terminal count). Now the DMA transfer is

completed.

At the end of the transfer, the system bus is released by the DMAC by making HOLD =

0. Thus microprocessor takes control of the system bus and continues its operation.

DMA Controller: Data Transfer Modes

The DMA controller functions as a bus master and bus slave. It performs data transfer

operations. DMA controlled input/output is further divided into the following categories:

1. Burst or Block Transfer DMA-

o It is the fastest DMA mode.

o In this mode, two or more data bytes are transferred continuously.

o The microprocessor is disconnected from the system bus during DMA transfer i.e.

the microprocessor cannot execute its own program during this transfer.

o N number of DMA cycles are added into the machine cycles of the

microprocessor where N is number of bytes to be transferred.

o In this mode, the DMA controller sends HOLD signal to the microprocessor and

waits for HLDA signal.

o After receiving HLDA signal, the DMA controller gains control of the system bus

and execute a DMA cycle to transfer one byte.

o After transferring one byte, it increments memory address, decrements counter

and transfers next byte.

o In this way, it transfers all data bytes between memory and I/O devices. After

transferring all data bytes, the DMA controller disables HOLD signal and enters

in to slave mode.

2. Cycle Steal or Single Byte Transfer DMA-

o In cycle steal transfer only one byte of data is transferred at a time.

o This type of DMA is slower than burst DMA.

o In this mode, only one DMA cycle is added between two machine cycles of the

microprocessor, hence the instruction execution speed of the microprocessor is

reduced slightly.

o In this mode the DMA controller sends HOLD signal to the microprocessor and

waits for HLDA signal.

o After receiving HLDA signal, the DMA controller gains control of the system bus

and execute only one DMA cycle.

o After transferring one byte, it disables HOLD signal and enters into slave mode.

o The microprocessor then gains control of the system bus and executes next

machine cycle. If the count is not zero and next data is available then the DMA

controller sends HOLD signal to the microprocessor and transfers next byte of

data block.

3. Transparent or Hidden DMA Transfer-

o The microprocessor executes some states during which it floats the address and

data buses.

o During these states, the microprocessor is isolated from the system bus.

o The DMA controller transfers data between memory and I/O devices during these

states. This operation is transparent to microprocessor.

o This is the slowest DMA transfer. In this mode, the instruction execution speed of

microprocessor is not reduced. But the transparent DMA requires logic to detect

the states when the microprocessor is floating the buses.

6. A memory system is to be designed for an 8086 processor based system with two

chips of 16K*8 EPROM and two chips of 32K*8 RAM. Select the suitable memory

map based on 8086 microprocessor architectures.

7 a) Synchronous data transfer: sender and receiver use the same clock signal

supports high data transfer rate

needs clock signal between the sender and the receiver

requires master/slave configuration

Asynchronous data transfer: sender provides a synchronization signal to the receiver before

starting the transfer of each message

does not need clock signal between the sender and the receiver

slower data transfer rate

There are many serial data transfer protocols. The protocols for serial data transfer can be

grouped into two types: synchronous and asynchronous. For synchronous data transfer, both the

sender and receiver access the data according to the same clock. Therefore, a special line for the

clock signal is required. A master (or one of the senders) should provide the clock signal to all

the receivers in the synchronous data transfer.

For asynchronous data transfer, there is no common clock signal between the sender and

receivers. Therefore, the sender and the receiver first need to agree on a data transfer speed. This

speed usually does not change after the data transfer starts. Both the sender and receiver set up

their own internal circuits to make sure that the data accessing is follows that agreement.

However, just like some watches run faster than others, computer clocks also differ in accuracy.

Although the difference is very small, it can accumulate fast and eventually cause errors in data

transfer. This problem is solved by adding synchronization bits at the front, middle or end of the

data. Since the synchronization is done periodically, the receiver can correct the clock

accumulation error. The synchronization information may be added to every byte of data or to

every frame of data. Sending these extra synchronization bits may account for up to 50% data

transfer overhead and hence slows down the actual data transfer rate.

7 b) It is possible to use either of the two methods.

There are special IC chips for serial data communication

UART: universal asynchronous receiver transmitter

USART: universal Synchronous/Asynchronous Receiver/Transmitter

COM port in the original IBM PC uses 8250 UART

INTEL has USART 8251

National Semiconductor’s improved version of 8250A is 16450.

16450, 16550, 16552 (dual 16550)

Data Transmission

– simplex

– half duplex

– full duplex

1 Block Diagram of 8251

2 Control Words

There are two types of control word.

ü Mode instruction (setting of function)

ü Command (setting of operation)

1) Mode Instruction

Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait

for write" at either internal reset or external reset. That is, the writing of a control word after

resetting will be recognized as a "mode instruction."

Items set by mode instruction are as follows:

ü Synchronous/asynchronous mode

ü Stop bit length (asynchronous mode)

ü Character length

ü Parity bit

ü Baud rate factor (asynchronous mode)

ü Internal/external synchronization (synchronous mode)

ü Number of synchronous characters (Synchronous mode)

The bit configuration of mode instruction is shown in Figures 3.8 and 3.9. In the case of

synchronous mode, it is necessary to write one-or two byte sync characters. If sync

characters were written, a function will be set because the writing of sync characters

constitutes part of mode instruction.

•

•

2) Command

Command is used for setting the operation of the 8251. It is possible to write

a command whenever necessary after writing a mode instruction and sync

characters.

Items to be set by command are as follows:

Transmit Enable/Disable

Receive Enable/Disable

DTR, RTS Output of data.

Resetting of error flag.

Sending to break characters

Internal resetting

Hunt mode (synchronous mode)

•

It is possible to see the internal status of the 8251 by reading a status word.

•

8 a)

RS232 to TTL interface converter can be a standard RS232C serial interface data: sending TXD

and a receiving RXD signals into TTL/COMS compatibility level. TTL level is 0-5V, no external

power supply, the internal use of the unique "RS232 charge pump circuit", don't need to initialize

the RS232 serial port can be obtained with zero delay, power supply; automatic control data flow

direction of I/O circuit is unique, and without any handshake signals (RTS, DTR), so as to ensure

the RS232 written in full duplex mode under the program without change can perform well in

TTL mode, to ensure that suitable for the existing software and hardware interface.

II. Performance parameters

Interface characteristics:

EIA/TIA interface compatible with RS232C,

TTL/COMS standard

Electrical interface: RS232 end DB9 pass connector, TTL terminal DB9 Needle connector

Working mode: Full duplex asynchronous

Transmission media twisted pair or belt shielding

Transmission speed: 300-115.2Kbps Size: 63 x 34 x 18 mm

The environment: -40 ℃ - 85 ℃

Relative humidity: 5% - 95%

Transmission distance: 5 meter

8 b)

We know that parallel ports are typically used to connect a PC to a printer and are rarely used for

other connections. A parallel port sends and receives data eight bits at a time over eight separate

wires or lines. This allows data to be transferred very quickly. However, the setup looks more

bulky because of the number of individual wires it must contain. But, in the case of a serial

communication, as stated earlier, a serial port sends and receives data, one bit at a time over one

wire. While it takes eight times as long to transfer each byte of data this way, only a few wires

are required. Although this is slower than parallel communication, which allows the transmission

of an entire byte at once, it is simpler and can be used over longer distances. So, at first sight it

would seem that a serial link must be inferior to a parallel one, because it can transmit less data

on each clock tick. However, it is often the case that, in modern technology, serial links can be

clocked considerably faster than parallel links, and achieves a higher data rate. Even in shorter

distance communications, serial computer buses are becoming more common because of a

tipping point where the disadvantages of parallel busses (clock skew, interconnect density)

outweigh their advantage of simplicity. The serial port on your PC is a full-duplex device

meaning that it can send and receive data at the same time. In order to be able to do this, it uses

separate lines for transmitting and receivingdata. From the above discussion we could understand

that serial communications have many advantages over parallel one like: Requires fewer

interconnecting cables and hence occupies less space. "Cross talk" is less of an issue, because

there are fewer conductors compared to that of parallel communication cables. Many IC s and

peripheral devices have serial interfaces.Clock skew between different channels is not an issue.

Cheaper to implement.Clock skew: Clock skew is a phenomenon in synchronous circuits in

which the clock signal sent from the clock circuit arrives at different components at different

times, which can be caused by many things, like: Wire-interconnect length.Temperature

variations.Variation in intermediate devices capacitive coupling Material imperfections

SERIAL DATA TRANSMISSION MODES

When data is transmitted between two pieces of equipment, three communication modes of

operation can be used.

Simplex: In a simple connection, data is transmitted in one direction only. For example, from a

computer to printer that cannot send status signals back to the computer.

Half-duplex: In a half-duplex connection, two-way transfer of data is possible, but only in one

direction at a time.

Full duplex: In a full-duplex configuration, both ends can send and receive data simultaneously,

which technique is common in our PCs.

There are two ways to synchronize the two ends of the communication.

1. Synchronous data transmission

2. Asynchronous data transmission

Synchronous Data Transmission The synchronous signaling methods use two different signals. A

pulse on one signal line indicates when another bit of information is ready on the other signal

line. In synchronous transmission, the stream of data to be transferred is encoded and sent on one

line, and a periodic pulse of voltage which is often called the "clock" is put on another line, that

tells the receiver about the beginning and the ending of each bit.

Advantages:

The only advantage of synchronous data transfer is the Lower overhead and thus, greater

throughput, compared to asynchronous one.

Disadvantages:

Slightly more complex

Hardware is more expensive

Asynchronous data transmission

The asynchronous signaling methods use only one signal. The receiver uses transitions on that

signal to figure out the transmitter bit rate (known as auto baud) and timing. A pulse from the

local clock indicates when another bit is ready. That means synchronous transmissions use an

external clock, while asynchronous transmissions are use special signals along the transmission

medium. Asynchronous communication is the commonly prevailing communication method in

the personal computer industry, due to the reason that it is easier to implement and has the

unique advantage that bytes can be sent whenever they are ready, a no need to wait for blocks of

data to accumulate.

Advantages:

Simple and doesn't require much synchronization on both communication sides.

The timing is not as critical as for synchronous transmission; therefore hardware can be made

cheaper. Set-up is very fast, so well suited for applications where messages are generated at

irregular intervals, for example data entry from the keyboard.

Disadvantages: One of the main disadvantages of asynchronous technique is the large relative

overhead, where a high proportion of the transmitted bits are uniquely for control purposes and

thus carry no useful information.

9 a) Advantages of optoisolators :

Opto isolators transfer data at incredibly high speeds. They are relatively small, inexpensive to

produce, and effective at limiting voltage levels across multiple circuits. Opto isolators can make

electrical devices safer, less prone to damage, and more efficient by removing all interference,

including electrical interference that lightning strikes create, power surges, alternating pulses,

and electrostatic discharge.

Advantages of EM relay :

1. They are quick acting and can be reset fast.

2. They are simple in construction.

3. They are reliable.

4. The values can be easily set. No special programming device is required.

5. People can be trained on these relays easily.

9 b). Peripheral Control Registers

PCON (Power Control)

The PCON or Power Control register, as the name suggests is used to control the 8051

Microcontroller’s Power Modes and is located at 87H of the SFR Memory Space. Using two bits

in the PCON Register, the microcontroller can be set to Idle Mode and Power Down Mode.

During Idle Mode, the Microcontroller will stop the Clock Signal to the ALU (CPU) but it is

given to other peripherals like Timer, Serial, Interrupts, etc. In order to terminate the Idle Mode,

you have to use an Interrupt or Hardware Reset.

In the Power Down Mode, the oscillator will be stopped and the power will be reduced to 2V. To

terminate the Power Down Mode, you have to use the Hardware Reset.

Apart from these two, the PCON Register can also be used for few additional purposes. The

SMOD Bit in the PCON Register is used to control the Baud Rate of the Serial Port.

There are two general purpose Flag Bits in the PCON Register, which can be used by the

programmer during execution.

SCON (Serial Control)

The Serial Control or SCON SFR is used to control the 8051 Microcontroller’s Serial Port. It is

located as an address of 98H. Using SCON, you can control the Operation Modes of the Serial

Port, Baud Rate of the Serial Port and Send or Receive Data using Serial Port.

SCON Register also consists of bits that are automatically SET when a byte of data is transmitted

or received.

Serial Port Mode Control Bits

SM0 SM1 Mode Description Baud Rate

0 0 0

8-Bit Synchronous Shift Register

Mode

Fixed Baud Rate

( Frequency of oscillator / 12)

0 1 1

8-bit Standard UART

mode

Variable Baud Rate (Can be set by Timer

1)

1 0 2 9-bit Multiprocessor Comm. mode

Fixed Baud Rate

( Frequency of oscillator / 32 or Frequency

of oscillator / 64

1 1 3 9-bit Multiprocessor Comm. mode

Variable Baud Rate (Can be set by Timer

1)

TCON (Timer Control)

Timer Control or TCON Register is used to start or stop the Timers of 8051 Microcontroller. It

also contains bits to indicate if the Timers has overflowed. The TCON SFR also consists of

Interrupt related bits.

TMOD (Timer Mode)

The TMOD or Timer Mode register or SFR is used to set the Operating Modes of the Timers T0

and T1. The lower four bits are used to configure Timer0 and the higher four bits are used to

configure Timer1.

10. a) Types of Instructions in 8051 Microcontroller Instruction Set

Before seeing the types of instructions, let us see the structure of the 8051 Microcontroller

Instruction. An 8051 Instruction consists of an Opcode (short of Operation – Code) followed by

Operand(s) of size Zero Byte, One Byte or Two Bytes.

The Op-Code part of the instruction contains the Mnemonic, which specifies the type of

operation to be performed. All Mnemonics or the Opcode part of the instruction are of One Byte

size.

Coming to the Operand part of the instruction, it defines the data being processed by the

instructions. The operand can be any of the following:

No Operand

Data value

I/O Port

Memory Location

CPU register

There can multiple operands and the format of instruction is as follows:

MNEMONIC DESTINATION OPERAND, SOURCE OPERAND

A simple instruction consists of just the opcode. Other instructions may include one or more

operands. Instruction can be one-byte instruction, which contains only opcode, or two-byte

instructions, where the second byte is the operand or three byte instructions, where the operand

makes up the second and third byte.

Based on the operation they perform, all the instructions in the 8051 Microcontroller Instruction

Set are divided into five groups. They are:

Data Transfer Instructions

Arithmetic Instructions

Logical Instructions

Boolean or Bit Manipulation Instructions

Program Branching Instructions

Data Transfer Instructions

The Data Transfer Instructions are associated with transfer with data between registers or

external program memory or external data memory. The Mnemonics associated with Data

Transfer are given below.

MOV

MOVC

MOVX

PUSH

POP

XCH

XCHD

The following table lists out all the possible data transfer instruction along with other details like

addressing mode, size occupied and number machine cycles it takes.

Arithmetic Instructions

Using Arithmetic Instructions, you can perform addition, subtraction, multiplication and

division. The arithmetic instructions also include increment by one, decrement by one and a

special instruction called Decimal Adjust Accumulator.

The Mnemonics associated with the Arithmetic Instructions of the 8051 Microcontroller

Instruction Set are:

ADD

ADDC

SUBB

INC

DEC

MUL

DIV

DA A

The arithmetic instructions has no knowledge about the data format i.e. signed, unsigned, ASCII,

BCD, etc. Also, the operations performed by the arithmetic instructions affect flags like carry,

overflow, zero, etc. in the PSW Register.

All the possible Mnemonics associated with Arithmetic Instructions are mentioned in the

following table.

Logical Instructions

The next group of instructions are the Logical Instructions, which perform logical operations like

AND, OR, XOR, NOT, Rotate, Clear and Swap. Logical Instruction are performed on Bytes of

data on a bit-by-bit basis.

Mnemonics associated with Logical Instructions are as follows:

ANL

ORL

XRL

CLR

CPL

RL

RLC

RR

RRC

SWAP

The following table shows all the possible Mnemonics of the Logical Instructions.

Boolean or Bit Manipulation Instructions

As the name suggests, Boolean or Bit Manipulation Instructions will deal with bit variables. We

know that there is a special bit-addressable area in the RAM and some of the Special Function

Registers (SFRs) are also bit addressable.

The Mnemonics corresponding to the Boolean or Bit Manipulation instructions are:

CLR

SETB

MOV

JC

JNC

JB

JNB

JBC

ANL

ORL

CPL

These instructions can perform set, clear, and, or, complement etc. at bit level. All the possible

mnemonics of the Boolean Instructions are specified in the following table.

Program Branching Instructions

The last group of instructions in the 8051 Microcontroller Instruction Set are the Program

Branching Instructions. These instructions control the flow of program logic. The mnemonics of

the Program Branching Instructions are as follows.

LJMP

AJMP

SJMP

JZ

JNZ

CJNE

DJNZ

NOP

LCALL

ACALL

RET

RETI

JMP

All these instructions, except the NOP (No Operation) affect the Program Counter (PC) in one

way or other. Some of these instructions has decision making capability before transferring

control to other part of the program.

The following table shows all the mnemonics with respect to the program branching

instructions.

10. b) An ARM processor is one of a family of CPUs based on the RISC (reduced instruction set

computer) architecture developed by Advanced RISC Machines (ARM).

ARM makes 32-bit and 64-bit RISC multi-core processors. RISC processors are designed to

perform a smaller number of types of computer instructions so that they can operate at a higher

speed, performing more millions of instructions per second (MIPS). By stripping out unneeded

instructions and optimizing pathways, RISC processors provide outstanding performance at a

fraction of the power demand of CISC (complex instruction set computing) devices.

ARM processors are extensively used in consumer electronic devices such

as smartphones, tablets, multimedia players and other mobile devices, such as wearables.

Because of their reduced instruction set, they require fewer transistors, which enables a smaller

die size for the integrated circuitry (IC). The ARM processor’s smaller size, reduced complexity

and lower power consumption makes them suitable for increasingly miniaturized devices.

ARM processor features include:

Load/store architecture.

An orthogonal instruction set.

Mostly single-cycle execution.

Enhanced power-saving design.

64 and 32-bit execution states for scalable high performance.

Hardware virtualization support.

The simplified design of ARM processors enables more efficient multi-core processing and

easier coding for developers. While they don't have the same raw compute throughput as the

products of x86 market leader Intel, ARM processors sometimes exceed the performance of Intel

processors for applications that exist on both architectures.

Advantages of optoisolators :

Opto isolators transfer data at incredibly high speeds. They are relatively small, inexpensive to produce, and effective at limiting voltage levels across multiple circuits. Opto isolators can make electrical devices safer, less prone to damage, and more efficient by removing all interference, including electrical interference that lightning strikes create, power surges, alternating pulses, and electrostatic discharge.

Advantages of EM relay :

6. They are quick acting and can be reset fast. 7. They are simple in construction. 8. They are reliable. 9. The values can be easily set. No special programming device is required. 10. People can be trained on these relays easily.