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EE 3610 Digital Systems Suketu Naik
1
Midterm Exam
Review
EE 3610: Digital Systems
EE 3610 Digital Systems Suketu Naik
2
Combinational
Logic
EE 3610 Digital Systems Suketu Naik
3Low Level Modules: Gates
Functions: done in class
EE 3610 Digital Systems Suketu Naik
4Boolean Algebra Combinational Logic (text, p4):
Unity Operators: A + 0 = A A · 1 = A
Complement: A + A = 1 A · A = 0
Commutativity: A + B = B + A A · B = B · A
Associativity: A + (B + C)= (A + B) + C A · (BC) = (AB) · C
Distributed Law: A · (B + C) = AB + AC
A + BC= (A + B) · (A + C)
Important: A + A = A A · A = A A · B + A · B = A
Note: A B = AB + AB
DeMorgan’s: (A + B + …)’ = A’·B’··· (ABC)’ = A’+B’+…
+
EE 3610 Digital Systems Suketu Naik
5Types of Digital System
Full Adder (done in class)
ADDER
X Co
YS
Truth Table
Outputs
Simplification
Ci
EE 3610 Digital Systems Suketu Naik
6Karnough Maps
Simplification can be difficult; use K-Map
Full Adder using K-Map
More Examples with K-Maps
Variable Entered Map (for large number of
variables)
EE 3610 Digital Systems Suketu Naik
7Implementation of Logic Gates
Logic Devices: NAND, NOR
EE 3610 Digital Systems Suketu Naik
8Implementation of Logic Gates
NAND Gate
A B Vout
0 0 1
0 1 1
1 0 1
1 1 0
EE 3610 Digital Systems Suketu Naik
9
Sequential
Logic
EE 3610 Digital Systems Suketu Naik
10Introduction
Combinational LogicMathematical function: single input has a single and unique output
Same inputs produce same outputs
Sequential LogicOutput depends on current and past inputs
Same inputs can yield different outputs, depending on memory
EE 3610 Digital Systems Suketu Naik
11SR Latch (Set-Reset Latch)
With NOR Gates
1) Active HIGH
2) S=1, R=1 is metastable
(invalid)
3) S=0, R=0: latch, no
change
4) Asynchronous
device
Red =1
Black=0
SR Circuit SR Truth Table NOR Truth Table
EE 3610 Digital Systems Suketu Naik
12Master-Slave D Latch: D Flip-Flop (FF)
Master and Slave D Latches
Clock
D QD Q
Q
D flip-flop symbol
Timing Diagram
Clock
D
Qm
(Qm)
Qs
(Qs)
What happens to Qs (output
of the FF) in relation to D
(input to the FF)?
While Clock (Enable) stays
high, Qs will follow D after
some delay; while clock stays
low, Qs will remember its
previous state and will not
respond to any changes in D
until the clock goes high again
EE 3610 Digital Systems Suketu Naik
13Essence of D Flip Flop
D Flip-Flop(Synchronous 1-bit memory)
Timing Diagram
Note: propagation delay between D and Q is omitted
EE 3610 Digital Systems Suketu Naik
14JK Flip-Flop
Clock
J Q
Q
JK flip-flop symbol
Timing Diagram
K
JK flip-flop circuit
X
Y
CLK
Q
Q’
Truth Table
If J and K are different, Q takes the value of J at the next clk edge
If J and K are both low, no change occurs
If J and K are both high, the output will toggle
EE 3610 Digital Systems Suketu Naik
15T Flip-Flop
T (CLK)
J Q
Q
T flip-flop symbol Timing Diagram
K
T Flip Flop: Tie J and K to high
Output will toggle at half the frequency of the clock at the
positive edge
Good for binary counters and frequency dividers
1
EE 3610 Digital Systems Suketu Naik
164-bit Register
Serial In Parallel Out (SIPO) 4 bit register
EE 3610 Digital Systems Suketu Naik
17Counters
Binary 4-bit
Synchronous Up
Counter
Output in
synchronization with
the clock
Individual output bits
change state at exactly
the same time in
response to the
common clock signal:
no ripple effect and no
propagation delay.
EE 3610 Digital Systems Suketu Naik
18Multiplexer (MUX)
4-to-1 Multiplexer
Select input to output based on S1S0
3 input AND gate
Truth Table
dxxs1s0
dxxs1s0
EE 3610 Digital Systems Suketu Naik
19Demultiplexer (DMX)
1-to-4 Demultiplexer
Select input to output based on S1S0
3 input AND gate
Truth Table
ds1s0
ds1s0
EE 3610 Digital Systems Suketu Naik
20Creating State Machines
(1) states with same next state (look at the
columns of state table): AD adjacent
(2) states that are next states of a common
state (look at the rows of state table) : AB
(2x), AC, DC adjacent
(3) states with same output for given input:
ABC adjacent
Legend:
input/output
Code State
00 A
01 B
11 C
10 D
Assignment mapState table
EE 3610 Digital Systems Suketu Naik
21Creating State Machines
Code (Q1Q2) State
00 A
01 B
11 C
10 D
Assign FFs per the
Assignment map
Step 5: Transition Table
Q1Q2
Q1+ Q2
+ Z
X=0 X=1 X=0 X=1
00 00 01 0 0
01 00 11 0 0
11 10 11 0 0
10 00 01 0 1
Transition Table
Q=present state FF, Q+=next desired state, Z=output
State table
Clock
D QD Q
Q
D Flip-Flop
EE 3610 Digital Systems Suketu Naik
22Creating State Machines
Step 6: Find Next States and Decoders: Use K-maps
Transition
Table
0 0
0 1
1 1
0 0
0 1X
Q1Q2
00
01
11
10
Q1+
0 1
0 1
0 1
0 1
0 1X
Q1Q2
00
01
11
10
Q2+
0 0
0 0
0 0
0 1
0 1X
Q1Q2
00
01
11
10
Z
Q1Q2
Q1+ Q2
+ Z
X=0 X=1 X=0 X=1
00 00 01 0 0
01 00 11 0 0
11 10 11 0 0
10 00 01 0 1
K-maps
EE 3610 Digital Systems Suketu Naik
23Creating State Machines
Step 7: Use K-maps Decoder (triple check your work!)
0 0
0 1
1 1
0 0
0 1X
Q1Q2
00
01
11
10
Q1+
0 1
0 1
0 1
0 1
0 1X
Q1Q2
00
01
11
10
Q2+
0 0
0 0
0 0
0 1
0 1X
Q1Q2
00
01
11
10
Z
D1 = Q1+ = X Q2 + Q1 Q2
XQ2
Q1Q2
D2 = Q2+ = X Z = X Q1 Q2’
Don’t forget:
1) Q1 , Q2 are the outputs (current states) of the FFs,
2) Q1+, Q2
+ are the inputs (next states) to the FFs,
3) Z is the final output of the design
EE 3610 Digital Systems Suketu Naik
24Creating State Machines
Step 8: Circuit !
Q1+ = XQ2 + Q1Q2 Q2
+ = X Z = XQ1Q2’
Q
QSET
CLR
D
Q
QSET
CLR
D
X
Q1
Q2
Q2
Q1+
Q2+
Q1Q2
XQ2
Z
Q1
Q2’
X
Q1Q2
EE 3610 Digital Systems Suketu Naik
25
VHDL
EE 3610 Digital Systems Suketu Naik
26VHDL: Overview
Model
Mathematical Description of a physical device
Simulation
Analysis (automated) of a model given a set of inputs
Digital Circuit Models
Structural: defines sub-models and how they are
interconnected (FFs, Gates, etc)
Behavioral: defines the behavior of the circuit (no
actual components)
EE 3610 Digital Systems Suketu Naik
27Levels of Abstraction: Behavioral, Structural, Physical
S <=ABS
Behavioral
(Algorithms, Dataflow)
Structural
(Components,
interconnections)
Physical
EE 3610 Digital Systems Suketu Naik
28Combinational Circuits
Concurrent Statements
C<=A and B after 5 ns;
E<=C or D after 5 ns;
Order is not important
E<=C or D after 5 ns;
C<=A and B after 5 ns;
EE 3610 Digital Systems Suketu Naik
29Priority of Operators
Let A=”110”, B=”111”, C=”011000”, and D=”111011”
(A & not B or C ror 2 and D)="1010010)
Order: not, &, ror, or, and, = 1) not B = ‘000” --bit-by-bit complement
2) A & not B = “110000” --concatenation
3) C ror 2 = “000110” --rotate right 2
places
4) (A & not B) or (C ror 2) = “110110 --bit-by-bit or
5) (A & not B or C ror 2) and D = “110010”--bit-by-bit and
6) [(A & not B or C ror 2 and D) =
“110010”]=TRUE --with parentheses the equality test is done last
EE 3610 Digital Systems Suketu Naik
30Example: 1-bit Full Adder
Co = A B + A Ci + B Ci; S=A B Ci
entity FullAdder is
port (A,B,Ci: in bit
Co,S: out bit
end FullAdder;
architecture Eq of FullAdder is
begin
S <= A xor B xor Ci;
Co <= (A and b) or (A and Ci) or (B
and Ci);
end Eq;
+ +
Use ( )to specify order of
precedence
EE 3610 Digital Systems Suketu Naik
4 bit Ripple Carry Adder
EE 3610 Digital Systems Suketu Naik
32Fast Carry Adder or Carry Look-Ahead Adder
Problem: ripple carry adder is too slow
Propagation delay on the order of number of bits
let gate delay = tg, 1-bit adder delay = 2tg (SOP
expressions for both sum and carry)
sum(i):= A(i) xor B(i) xor Carry;
carry := (A(i) and Cin) or (B(i) and
Cin) or (A(i) and B(i));
Instead or each stage, you can determine
If a carry is generated (A=1 and B=1) or
If a carry is propagated (A=1 or B=1 and carry =1)
EE 3610 Digital Systems Suketu Naik
331-bit Carry Look-Ahead Adder
entity CLA1 is
port(A,B,C1: in std_logic;
P,G,S: out std_logic);
end CLA1;
architecture behav of CLA1 is
begin
S <= A xor B xor C1;
P <= A or B; --A xor B is more accurate
G <= A and B;
end behav;
EE 3610 Digital Systems Suketu Naik
344-bit Carry Look-Ahead Adder
4-bit Carry Look-Ahead Adder
4-bit Ripple Carry Adder
EE 3610 Digital Systems Suketu Naik
3516-bit Carry Look-Ahead Adder
Use 4-bit modules in hierachical structure to add large number of
bits
EE 3610 Digital Systems Suketu Naik
36Sequential Statements
What does this process do?
process (A, B)
begin
C <= A and B;
Not_C <= not C;
end process
C never gets updated.
Add C in the sensitivity list
If you use “variables”, then assignment is
instantaneous
EE 3610 Digital Systems Suketu Naik
37Q: What does this model?
--------------------------------------------
process(D, G)
begin
if (G='1') then
Q <= D;
end if;
end process;
--------------------------------------------
EE 3610 Digital Systems Suketu Naik
D Flip Flopentity DFF is
port (D, CLK, CLR: in bit;
Q: out bit; QN: out bit:='1');
---intialize Q' to '1' since bit signals
are intialized to '0' by default
end DFF
architecture so of DFF is
begin
process (CLK,CLR)
begin
if CLR='0' then
Q <='0'; QN<='1';
else if CLK'event and CLK='1' then
Q <= D after 10 ns;
QN <= not D after 10 ns;
end if;
end if;
end process;
CLR
Rising Edge of the
Clock
Can also use
if rising_edge(clk)) then
EE 3610 Digital Systems Suketu Naik
39State Machines
Rather than assigning state codes, let VHDL
Compiler do it
Enumerated Types
type state_type is(state A, state B,...);
signal present_state, next_state:state_type
Now we can write,
present_state <= state A;
EE 3610 Digital Systems Suketu Naik
40MUX: Using when and else Concurrently
F <= I0 when A='0' else B;
F <= I0 when B='00' else
I1 when B='01' else
I2 when B='10' else
I3 when B='11';
bit_array (1 down to 0)not necessary
EE 3610 Digital Systems Suketu Naik
41Arrays All arrays must have a new "type" explicitly defined
type register_file is array (0 to 255) of
bit_vector (15 downto 0);
signal reg0: register_file
Access each element using parentheses
reg0(1)<=reg0(2);--cycle
Type can be unconstained (unknown dimension):
1) low and high bound are defined when a
signal/variable is delcared
2) index must be an integral type: natural, positive
type intvec is array(natural range <>) of integer;
signal intvec5: intvec(1 to 5) := (3,26,8,90,1);
EE 3610 Digital Systems Suketu Naik
42Loops: Examples
32 bit Ripple Carry Adderprocess(A,B,Cin)
variable carry: bit; sum: bit_vector (32
downto 0)
begin
carry := Cin;
loop1 for i in 0 to 31 loop
sum(i):= A(i) xor B(i) xor Carry;
carry := (A(i) and Cin) or (B(i) and
Cin) or (A(i) and B(i));
Cin := carry;
end loop loop1;
Cout <= carry;
S <= sum;
end process;
EE 3610 Digital Systems Suketu Naik
43Read Only Memory (ROM)
1. Each output pattern stored in the ROM is called a
word
2. Each input combination serves as an address which
can select one of the words which is stored in the
memory.
3. We defined a ROM (2n x m ROM), means an
array of 2n words and each word is m bits long.
EE 3610 Digital Systems Suketu Naik
Figure 9.20 An 8-Word X 4-Bit ROM
Usefulness of ROM
ROM can model any n-input, m-output combinational
logic problem
Example: BCD to 7-Segment Display
Inputs: 4 bit BCD code
Outputs: 7 control signals for the display
44
EE 3610 Digital Systems Suketu Naik
Figure 9.20 An 8-Word X 4-Bit ROM
VHDL for ROM: declare constants
library ieee;
use ieee.std_logic_1164.all;
entity rom16x8 is
port(addr: in integer range 0 to 15;---can also have bits
here instead
data: out std_ulogic_vector(7 downto 0));
end entity;
architecture sevenseg of rom16x8 is
type rom_array is array (0 to 15) of std_ulogic_vector (7
downto 0);
constant rom: rom_array := ( “11111011”, “00010010”,“10011011”, “10010011”, “01011011”, “00111010”,“11111011”, “00010010”, “10100011”, “10011010”,“01111011”, “00010010”, “10101001”, “00110110”,“11011011”, “01010010”);begin
data <= rom(addr);-may have to use to to_integer if bits
end architecture;
45
EE 3610 Digital Systems Suketu Naik
46
Vector/Numeric
Conversions
EE 3610 Digital Systems Suketu Naik
Figure 9.32 Layout of a Typical FPGAunsigned_vect <= to_unsigned (int, 8)
int <= to_integer (unsigned_vect);
unsigned_vect <= unsigned (vect);
vect <= std_logic_vector (unsigned_vect);
Vector/Numeric Conversions 47
EE 3610 Digital Systems Suketu Naik
48
Registers
and Counters
in VHDL
EE 3610 Digital Systems Suketu Naik
49Register
-- shift register
process (clk, reset)
begin
if reset = '1' then
tsr <= "111111111";
elsif rising_edge (clk) then
if load = '1' then
tsr <= tbr & '0';
elsif shift = '1' then
tsr <= '1' & tsr(8 downto 1);
end if;
end if;
end process;
tsmt <= tsr(0);
EE 3610 Digital Systems Suketu Naik
50
--Timer
Process (clk)
begin
if rising_edge (clk) then
if full_bit = '1' then t <= 5208;
else t <= t-1;
end if;
end if;
end process;
timeout <= '1' when t = 0 else '0';
Counter
EE 3610 Digital Systems Suketu Naik
51
State Machine
Charts
EE 3610 Digital Systems Suketu Naik
52State Machine Chart: Example
A
B
C
X
X X
XX
X
Z1=X
Z1=X
Z2
A
X
Z1
B
X
C/Z2
Z1
0
1
X
State Box Condition Conditional Output
0
1
0
1
EE 3610 Digital Systems Suketu Naik
Binary Multiplier Control 21
SM Chart for Multiplier Controller4-bit Binary Multiplier
State Machine for Multiplier Controller
EE 3610 Digital Systems Suketu Naik
54
Inside the FPGA
EE 3610 Digital Systems Suketu Naik
Figure 9.32 Layout of a Typical FPGAFPGAs contain an array of logic cells called configurable logic blocks
CLB
Field Programmable Gate Arra (FPGA)
Programmable
Interconnect
Area
55
EE 3610 Digital Systems Suketu Naik
56SIDE NOTES: INSIDE THE FPGA
CLB=Configurable Logic Block=4 Slices
Slice=> two Look Up Table (LUT)s and two Flip Flops
EE 3610 Digital Systems Suketu Naik
57Xilinx's CLB
EE 3610 Digital Systems Suketu Naik
58
16:1 MUX
16:1 Addressable Shift Register LUT
(64-bit Shift Register is max possible)
LUT Implementation: Shift Register
Address (A[3:0]):
(1) Dynamically changes the length of the shift register
(2) Asynchronous path to D (output)
EE 3610 Digital Systems Suketu Naik
59
Shift Register LUT (SRL) Structure
LUT Implementation: Shift Register
EE 3610 Digital Systems Suketu Naik
60
Debouncer
and
Single Pulser
EE 3610 Digital Systems Suketu Naik
61Debouncing Mechanical Switches
EE 3610 Digital Systems Suketu Naik
62Single Pulser: State Machine
Use two flipflops
to provide debouncing and
synchronization
EE 3610 Digital Systems Suketu Naik
63Single Pulser: VHDL
entity spulser is
port(reset, SYNCPRESS:in std_logic;
SP: out std_logic);
end spulser;
architecture behav of spulser is
type state_type is (S0,S1);
signal pstate, nstate:state_type;
begin
------------STATE REGISTER---------------------------------
process(clk, reset) ----without reset in the sensitivity list,
--it's a sync process
begin
if reset='1' then
pstate <= S0;
elsif rising_edge(clk) then -- rising edge of clock
pstate <= nstate;
end if;
end process;
--------------------------------------------------------------
EE 3610 Digital Systems Suketu Naik
64Single Pulser: VHDL
------------STATE Controller---------------------------------
process (pstate, SYNCPRESS)
begin
SP <= '0';
case pstate is
when S0 =>
if SYNCPRESS = '0' then nstate <= S0;
else
nstate <= S1; SP='1';
end if;
when S1 =>
if SYNCPRESS = '1' then nstate <= S1;
else
nstate <= S0;
end if;
end process
end behav;