minimum cost fault tolerant adder circuits in reversible logic synthesis
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TRANSCRIPT
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic
Synthesis
Sajib Kumar Mitra*
Department of Computer Science and EngineeringFaculty of Engineering and Technology
University of Dhaka, Dhaka-1000, BangladeshE-mails: [email protected], [email protected]
*Corresponding Author and Presenter
Purposes
• Minimization of Quantum Cost
• Fault Tolerant Circuit
• Reduction of Critical Path Delay
• Reduction of Number of Gates
• Garbage Outputs Optimization
Overview
• Reversible and Quantum Computing
• Quantum Realization of Reversible Circuits
• Fault Tolerant Mechanism
• Proposed Designs of Adder Circuits
• Performance Analysis
• Conclusion
Reversible and Quantum Computing
Reversible Computing
• Equal number of input states and output states• Preserves an unique mapping between input and
output vectors for any Reversible circuit• One or more operations can be united called
Reversible Gate• (N x N) Reversible Gate has N number of inputs and
N number of outputs where N= {1, 2, 3, …}
[1] A. K. Biswas, M. M. Hasan, A. R. Chowdhury, and H. M. H. Babu, “Efficient approaches for designing reversible binary coded decimalimplement in a single adders,” Microelectronics Jounrnal, vol. 39, no. 12, pp. 1693–1703, December 2008.
A
BA B
3
2
1
0
1
0
INP
UT
VE
CT
OR
(A
, B)
OU
TP
UT
VE
CT
OR
(A
B
)
OU
TP
UT
VE
CT
OR
(P
, Q)
3
2
1
0
2
1
INP
UT
VE
CT
OR
(A
, B)
FGA
B Q=A B
P=A
0
3
(a) Irreversible EX-OR operation (b) Reversible EX-OR operation
• Limitation • Feedback is strictly restricted • Fan-out must be one always
Fig. 1: Basic difference between Irreversible and Reversible Circuits
Reversible Computing…
F2GA
BC
A
A C
A B
(d) Feynman Double Gate
PGA
BC
AA B
AB C
(b) Peres Gate
FRGA
BC
A
A’C AB
A’B AC
(f) Fredkin Gate
TGA
BC
A
AB C
B
(c) Toffoli Gate
NFTA
BC
AC’ B’CAC’ BC
A B
(e) New Fault Tolerant Gate
FGAA
B A B
(a) Feynman Gate
Fig. 2: Popular Reversible gates
Reversible Computing…
In Quantum Computing, encode information as a series of quantum-mechanical states such as spin directions of electrons or polarization orientations of a photon that might represent as or might represent a superposition of the two values.
Encoded data is represented by qubits rather than bits which can perform certain calculations exponentially faster than conventional computing.
10 q
Quantum Computing
[2]W. N. N. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski, “Quantum logic synthesis by symbolic reachability analysis,” in 41st Conference on (DAC’04), Design Automation Conference, May 2004, pp. 838–841.
Quantum Computation uses matrix multiplication rather than conventional Boolean operations and the information measurement is realized by calculation the state of qubits .
The matrix operations over qubits are simply specifies by using quantum primitives. For example,
›|B A
|A
|B
|A
›(a) Quantum XOR operation (b) Equivalent matrix
for XOR
UCN=
1 0 0 00 1 0 00 0 0 10 0 1 0
››
Fig. 3: Reversible behavior of Quantum matrix operation
Quantum Computing…
Q= |B A
››
|A
|B ›Quantum XOR operation
›P= |AInput Output
A B P Q
0 0 0 0
0 1 0 1
1 0 1 1
1 1 1 0
Input/output
PatternSymbol
00 a
01 b
10 c
11 d
Quantum Computing…
Fig. 4: Working Principle of Unitary Controlled NOT (UCN)
1 0 0 00 1 0 00 0 0 10 0 1 0
abcd
abdc
Quantum Realization of Reversible Circuits
Quantum Cost
• Quantum Cost (QC): Total number of 2x2 quantum primitives (4x4 unitary matrices) which are used to form equivalent quantum circuit of any Reversible Circuit.
A A
B VIF (A ) THEN V(B )
ELSE B
A A
B V+ IF (A ) THEN V+(B ) ELSE B
A A
B A B
(b) EXclusive-OR
A A’
(a) NOT, Cost =0
(c) Square Root of NOT (d) Hermitian of SRN
Fig. 5: Several Quantum Primitives[3] M. Perkowski and et al, “A hierarchical approach to computer-aided design of quantum circuits,” in 6th International Symposium on Rep-resentations and Methodology of Future Computing Technology, 2003, pp. 201–209.
A A
B B
V V+
A
B
A
B
V V
A
B
A
B
T(a)
T(b)
The attachment of SRN (Hermitian Matrix of SRN) and EX-OR gate on the
same line generates symmetric gate pattern has a cost of 1.
Here T= V or V+
Fig. 6: Difference interactions between Quantum Primitives
Orientation of Quantum Gates
F2G, Cost = 2
A
A B
A
B
C A C
TG, Cost = 5
VV V+
B
AA
B
C AB C
Fig. 7: Equivalent Quantum Circuits of Reversible Gates
Quantum Cost of Reversible gates
FRG, Cost = 5
V
A
BC
A
V V+
A’B AC
A’C AB
VV V+
A B
AA
B
C AB C
PG, Cost = 4
DMIG, Cost = 7
ABC
Peres Gate
A
AB CAB’ D
A B
TG, Cost = 5
VV V+
Q= B
P= AA
B
C R= AB C
TGAB
C
P=A
R=AB C
Q=B
Working Principle of Quantum Circuit
How does Quantum
circuit work?
Fig. 8: Toffoli Gate and corresponding Quantum Circuit
V
1
1
C V R=C’
INPUT OUTPUT
A B R
0 0 C
0 1 C
1 0 C
1 1 C’
V
0
1
C V R=CV+ V
1
0
C V R=CV+
Fig. 9: Working Principle of Quantum Equivalent of TG
Working Principle of Quantum Circuit…
Working Principle of Quantum Circuit…
TGAB
C
P=A
R=AB C
Q=B
V
A
B
C V V+ R=AB C
A
B
INPUT OUTPUT
A B R
0 0 C
0 1 C
1 0 C
1 1 C’
V
A
B
C V V+ R=AB C
P=A
Q=B
Quantum Cost of Toffoli Gate is 5
Working Principle of Quantum Circuit…
Alternate representation of Quantum circuit of TG…
B
AA
B
C AB C
TGAB
C
P=A
R=AB C
Q=B
V
A
B
C V V+ R=AB C
P=A
Q=B
Fig. 9: Quantum Realization of NFT Gate (QC= 5)
V V+V
a
bc
a bac bc
ac bc
Proposed Quantum Circuit of NFT
A
BC
P=A B
R=AC’ BC
Q=AC’ B’CNFT
Proposed Quantum Circuit of NFT…
P=A B
R=AC’ AB
Q=AC’ B’C
A
BC
P=A B
R=AC’ BC
Q=AC’ B’CNFT
P=A B
R=C(A B) A
Q=C(A B) A C
Proposed Quantum Circuit of NFT…
A
BC
P=A B
R=C(A B) A
NFT Q=C(A B) A C
A
BC
A BBC
Proposed Quantum Circuit of NFT…
A
BC
P=A B
R=C(A B) A
NFT Q=C(A B) A C
A
BC
A B
CC(A B) B
Proposed Quantum Circuit of NFT…
A
BC
P=A B
R=C(A B) A
NFT Q=C(A B) A C
ABC
A BC(A B) BC B A
Proposed Quantum Circuit of NFT…
A
BC
P=A B
R=C(A B) A
NFT Q=C(A B) A C
ABC
A BC(A B) BC(A B) A C
Proposed Quantum Circuit of NFT…
A
BC
P=A B
R=C(A B) A
NFT Q=C(A B) A C
ABC
A BC(A B) A CC(A B) B
Proposed Quantum Circuit of NFT…
A
BC
P=A B
R=C(A B) A
NFT Q=C(A B) A C
ABC
A BC(A B) A CC(A B) A
Fig. 9: Quantum Realization of NFT Gate (QC= 5)
V V+V
a
bc
a bac bc
ac bc
Proposed Quantum Circuit of NFT
A
BC
P=A B
R=AC’ BC
Q=AC’ B’CNFT
Fault Tolerant Mechanism
Fault Tolerant Mechanism
Preserves same parity between Input and Output vectors
over one to one mapping of Reversible circuit.
Reversible Circuit
I1
I2
I3
In
O1
O2
O3
On
EV
EN
Par
ity
EV
EN
Par
ity
Reversible Circuit
I1
I2
I3
In
O1
O2
O3
On
OD
D P
arit
y
OD
D P
arit
y
Fig. 10: Fault Tolerant circuit preserves same parity between input and output vectors
[4] B. Parhami, “Fault tolerant reversible circuits,” in In Proc. of 40th Asimolar Conference Signals, Systems and Computers. Pacific Grove, CA, 2006, pp. 1726–1729.
Fault Tolerant Mechanism...
Let, Iv and Ov are input and output vectors of a reversible
circuit, so the relation is Iv↔Ov.
But to be a Reversible Fault Tolerant circuit, itself must
preserve following equation:
where Iv={I1, I2, I3, …, In} and Ov={O1, O2, O3, …, On}
nn OOOIII 2121
Input Parity = Output Parity
Fault Tolerant Mechanism…
A
BC
P=A
R=A’C AB
Q=A’B ACFRG
A
BC
P=A B
R=AC’ BC
Q=AC’ B’CNFT
F2GA
BC
A
A C
A B ABC
P = A
D
Q = A BR = AB CS = AB’ D
MIG
A
B
C
B C D
D
PPHCG B C AB D AC D A
Fig. 11: Most Popular Fault Tolerant Gates
Fault Tolerant Mechanism…
A
BC
P=A
R=A’C AB
Q=A’B ACFRG
RQPCBA
INPUT OUTPUT
A B C P Q R
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 0 1
1 1 1 1 1 1
Fault Tolerant Mechanism…
1
01
1FRG 1
0EV
EN
EV
EN
Fault detection of FRG gate
RQPCBA
Verification of the following equation:
1
01
1FRG 1
1EV
EN
OD
D
Circuit with Faulty OutputCircuit without Fault
Fault Tolerant Mechanism…
A
BC
P=A
R=A’C AB
Q=A’B ACFRG
A
BC
P=A B
R=AC’ BC
Q=AC’ B’CNFTF2GA
BC
A
A C
A B
ABC
P = A
D
Q = A BR = AB CS = AB’ D
MIG
QC= 2
QC= 7
QC=5
QC= 5
Proposed Design of Adder Circuits
F2G F2G NFT F2Ga
b0
0 cin
a b cinab bcin acin
GGG
Proposed Design of Full Adder
CinFRG
F2GF2G
F2G
0
A
B
0
G
G
GA B Cin
AB BCin ACin
Reversible Fault Tolerant Full Adder
2
2 2
5
2 2 5 2
Fig. 12: Proposed Design of Fault Tolerant Adder Circuit
Comparison with Existing Design
ABCD G
MIGSum
MIGCin
CoutG
G
Comparison with Existing [5] Fault Tolerant Design
7 7
F2G F2G NFT F2Ga
b0
0 cin
a b cinab bcin acin
GGG2 2 5 2
Single NFT Full Adder
SNFA[5] M. S. Islam, M. M. Rahman, Z. begum, and M. Z. Hafiz, “Efficient approaches for designing fault tolerant reversible carry look-ahead and carry-skip adders,” MASAUM Journal of Basic and Applied Sciences, vol. 1, no. 3, 2009.
Proposed Design of Carry Skip Adder
Reversible Fault Tolerant Carry Skip Adder (RFT-CSA)
SNFA
x3y3 00
SNFA
x2y2 00
SNFA
x1y1 00
SNFA
x0y0 00
C2 C1C0 Cin
C3
FRG FRG FRG
FRG
0
0
S1S2S3
S000
F2G
Cout
Fig. 13: Proposed Design of Fault Tolerant Carry Skip Adder
Delay Calculation of RFT-CSA
Delay Optimization of Fault Tolerant Carry Skip Adder
SNFA
x3y3 00
SNFA
x2y2 00
SNFA
x1y1 00
SNFA
x0y0 00
C2 C1C0 Cin
C3
FRG FRG FRG
FRG
0
0
S1S2S3
S000
F2G
Cout
4
56789
Fig. 14: Delay Calculation of RFT-CSA
Performance Analysis of RFT-CSA
0
20
40
60
80
100
120
140
Proposed Existing [5] Exising [6] Existing [7]
Un
it(s
)
Gates Garbage Delay Quantum Cost
Fig. 15: Compare with existing designs of Carry Skip Adder[6] P. K. Lala, J. P. Parkerson, and P. Charaborty, “Adder designs using reversible logic gates,” WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, June 2010.[7] J. W. Bruce et al., “Efficient adder circuits based on a conservative re-versible logic gates,” in ISVLSI ’02: Proceedings of the IEEE Computer Society Annual Symposium on VLSI. Washington, DC, USA, 2005, pp. 83–88.
Proposed Carry Look-ahead AdderReversible Fault Tolerant Carry Look-ahead Adder
(RFT-CLA) Circuit
F2G F2G NFT F2Gx0
00
cin
S0
G
G
F2G F2G NFT F2G0
S1
G
G
y0
x1
0y1
G
G
F2G F2G NFT F2G0
S2
G
G
x2
0y2
G
F2G F2G NFT F2G0
S3
G
G
x3
0y3
G
Cout
Fig. 16: Proposed design of Fault Tolerant Carry Look-ahead Adder
Delay Calculation of RFT-CLA
Delay Calculation of Fault Tolerant Carry Look-ahead Adder
F2G F2G NFT F2Gx0
00
cin
S0
G
G
F2G F2G NFT F2G0
S1
G
G
y0
x1
0y1
G
G
F2G F2G NFT F2G0
S2
G
G
x2
0y2
G
F2G F2G NFT F2G0
S3
G
G
x3
0y3
G
Cout
1 2 3
4
5
6 7
Performance Analysis of RFT-CLA
0
10
20
30
40
50
60
70
RFT-CLA RFT-CSA
Un
it(s
) Gates
Garbage
Delay
Quantum Cost
Fig. 17: Performance Analysis between Fault Tolerant Carry Look-ahead Adder and Carry Skip Adder
Conclusions
Reversible Circuit prevents power consumption caused by
input bit loose and tolerates bit error by using fault tolerant
mechanism. The operations of Quantum Computing are
fundamentally reversible and circuit performs multiple
operations in single cycle. We have presented the efficient
designs of fault tolerant reversible adder circuits, where the
designs are preferable for quantum computing because of
minimum quantum cost in the designs.
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