mipi low latency interface (lli) for mobile phone bom … asia expo - arteris... · ericsson, texas...
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Copyright © 2012 MIPI Alliance. All rights reserved.
Scott Yang Greater China Country Manger
Arteris Inc
Copyright © 2012 MIPI Alliance. All rights reserved.
MIPI Low Latency Interface (LLI) for Mobile Phone BoM
Cost Savings
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Copyright © 2012 MIPI Alliance. All rights reserved.
Legal Disclaimer
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this
material or MIPI. The material contained herein is provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is
provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions,
either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a
particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. ALSO,
THERE IS NO WARRANTY OR CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR
NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL.
All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or
otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all
related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior
written permission.
IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF
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DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT
OF THIS OR ANY OTHER AGREEMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE
POSSIBILITY OF SUCH DAMAGES.
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Copyright © 2012 MIPI Alliance. All rights reserved.
• Arteris NoC Milestones • Technical Founders from Tsquared in 2003 • Founded Network-on-Chip Interconnect in 2003 (250 man years of
development) • NoC Solution = first released implementation of a Arteris NoC in 2005 • First Customer in early 2006. • FlexNoC® = second generation of Arteris NoC in 2009.
• Investors: Qualcomm, ARM, DoCoMo, Synopsys, Ventech, TVM & Crescendo
• Awards: EE Times ACE Finalist 2012, Red Herring “Global 100” 2010, MIT Technology Review “10 Private Companies to Watch” 2010, EE Times “60 Emerging Start-ups” 2009, World Economic Forum “Technology Pioneer 2008”, Red Herring “Europe 100” 2007
Arteris: The NoC Interconnect IP Leader
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Copyright © 2012 MIPI Alliance. All rights reserved.
What is MIPI LLI?
LLI = Low Latency Interface
• Enables companion chip use models
• Fast enough for cache refills & DRAM sharing
• No software drivers or stack
• Minimal Pins
• Uses low power MIPI M-PHY
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Copyright © 2012 MIPI Alliance. All rights reserved.
MIPI LLI enables Shared Memory and Companion Chip use cases
Application Processor Baseband Modem
Memory Memory
LLI
M-PHY
LL
I C
on
tro
ller
M-RX
Din
D
out
C
RM
MI
C
M-TX
M-PHY LL
I Co
ntro
ller M-RX
Din
D
out
C
RM
MI
C
M-TX
Removing an LPDDR2 saves $1-2
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Copyright © 2012 MIPI Alliance. All rights reserved.
MIPI LLI is less expensive than PoP
Low Latency Interface
Removing modem baseband’s dedicated memory:
• Saves $1-2 in BoM cost
• Eliminates DRAM area from PCB floorplan
• Maintains vertical height clearance
Modem BB + DRAM PoP
Using a modem baseband + RAM in a PoP:
• Maintains $1-2 RAM BoM cost
• Adds $0.50 to $1+ for PoP packaging cost
• Increases chip vertical height
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Copyright © 2012 MIPI Alliance. All rights reserved.
Arteris participation in MIPI LLI WG
• Joined MIPI at creation of LLI Investigation Group
• Attended LLI IG and WG conference calls and F2F meetings since creation
• Mostly by Philippe Martin
• Deeply involved in Transaction Layer (L5) definition • Protocol interoperability experience • Spec writing owned by TI, Arteris review
• Main driver of Data Link Layer (L2) • Interchip-Link experience • Spec writing owned by Arteris
• Significant contribution to PHY Adaptation layer (L1.5) • ARQ retry scheme
• Major contributor to the upcoming LLI specification versions
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Copyright © 2012 MIPI Alliance. All rights reserved.
How Did We Get Here?
• MIPI Low Latency Interface (LLI) Investigation group formed in December 2009
• LLI confirmed as Working Group in 18 March 2010
• MIPI LLI 1.0 spec approved 4 April 2012
• LLI WG Member Companies: • Analog Devices, ARM, Arteris, Broadcom, Cadence,
Infineon, MCCI, Micron, Motorola, Nokia, Qualcomm, RIM, Samsung, SMSC, STMicroelectronics, ST-Ericsson, Texas Instruments
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Copyright © 2012 MIPI Alliance. All rights reserved.
LLI is a Layered Model LLI C
ontro
ller
M-P
HY
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Copyright © 2012 MIPI Alliance. All rights reserved.
LLI is Implemented in 2 IP components
Chip #1
M-PHY
LLI Controller
Chip #2
M-RX
Din
D
out
C
RM
MI
C
M-TX
1or more Tx/Rx Lanes
NIU
DataLink
Controller PA
NIU
N
IU
NIU
N
IU
µN
oC
BE
BE
LL
LL
SVC
Sideband
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Copyright © 2012 MIPI Alliance. All rights reserved.
Interconnect Adaptation Layer
• IAL is implementation from Arteris • Required, but not defined in MIPI LLI spec
because each SoC interconnect is different
• Connects to SoC interconnect • Typically AXI, OCP for Low Latency (LL) and
Best Effort (BE) Traffic Classes • APB or OCP for config
• Supports any data width • Typically 32 bits to 128 bits
• Mapping between interconnect Traffic Classes (BE, LL, SVC)
• Power management, Connection/ Disconnection, QoS, Clock Management, Rate Matching, etc…
NIU
N
IU
NIU
N
IU
NIU
µN
oC
BE
BE
LL
LL
SVC
*FlexLLI Implementation
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Copyright © 2012 MIPI Alliance. All rights reserved.
Transaction & Data Link Layers
• Arteris FlexLLI embeds Transaction and Data Link Layers in DataLink Controller
• Usually same clock as interconnect
• Optional Master/Slave LL and BE TC ports
• Optional 40-bit LLI addressing
• Handles LLI clock conversions
• Performance parameters
DataLink
Controller
Sideband
*FlexLLI Implementation
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Copyright © 2012 MIPI Alliance. All rights reserved.
System Address translation
• Typically configured by “system master” • Number of regions configurable at design time, per port • Offset configurable at runtime • Same mechanism for ingoing/outgoing transactions
Local Interconnect
mapping
Remote chip mapping
Segment 0
Ex : 64 MB to DRAM
Segment 2
Ex : 32 MB to PER1
Address _ in
+ Offset 0
Address _ in
+ Offset 2
Base 1
PER space
DRAM space
Base 2
Base 3
Segment 1
Ex : 64 MB to DRAM Address _ in
+ Offset 1
Segment 3
Ex : 64 MB to PER2
Address _ in
+ Offset 3
Local
mapping
Remote chip
mapping
Address _ in
+ Offset 0
Segment 0
( LLI : 64 MB )
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Copyright © 2012 MIPI Alliance. All rights reserved.
Physical Adapter Layer
• Interface to MIPI M-PHY
• Configurable number of Rx and Tx lanes
• Configurable RMMI data
• Optional PHY test mode
Din
D
out
C
RM
MI
C PA
*FlexLLI Implementation
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Copyright © 2012 MIPI Alliance. All rights reserved.
MIPI M-PHY
• Industry standard
• Optimized for mobile applications • High performance and scalability • Low power operation and modes
• LLI M-PHY features • Type 1 • HS-Mode Gears G1, G2 or G3 • Up to 5.8 Gbps per lane
M-PHY
M-RX
Din
D
out
C
RM
MI
C
M-TX
1or more Tx/Rx Lanes
PA
*FlexLLI Implementation
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Copyright © 2012 MIPI Alliance. All rights reserved.
Why MIPI LLI?
• Link a chip and a companion chip together
• Remove a memory chip from a mobile phone
• No software complexity
• Fewer pins than other standards
• Scalable – Future-proof designs for high-throughput requirements
• Low Power – Leverage M-PHY (< pwr than PCIe)
Increase Flexibility, Reduce BoM cost
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Copyright © 2012 MIPI Alliance. All rights reserved.
Why Arteris FlexLLI?
• First and only Silicon-proven LLI controller
• Lowest risk, automated environment for fast configuration and verification setup
• Industry-leading M-PHY / LLI joint solution with Synopsys
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Copyright © 2012 MIPI Alliance. All rights reserved.
MIPI LLI is implemented in TI OMAP5 Platform and other SoCs
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Copyright © 2012 MIPI Alliance. All rights reserved.
FlexLLI automated delivery environment
µNoC
DL+PA
controller
Clock management
AXI
APB
AXI
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Copyright © 2012 MIPI Alliance. All rights reserved.
FlexLLI delivery environment
• Provides same capabilities as FlexNoC environment • Parameterization of µNoC and LLI controller • RTL, synthesis scripts and SystemC exports
• FlexVerifier VMM automated test bench export • Allows simulations of µNoC + LLI controller
• Reverse LLI BFM automatically instantiated • Standard diagnostics provided • Open environment for user-defined diagnostics
• Will incorporate M-PHY models • Will be tuned to Synopsys M-PHY specifics
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Copyright © 2012 MIPI Alliance. All rights reserved.
Flexibility: FlexLLI has Many Configuration Options
• Configuration registers • Sideband and IRQ management, transaction user bit
remapping, address translation, Req/Rsp Arbitration priority, credit frame arbitration
• Clock gating and power management • Double-level clock gating (Units and reg levels) • Integrates into SoC power management
• QoS, debug observability, buffering, clock management, traffic class mapping, custom protocols, etc.
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Copyright © 2012 MIPI Alliance. All rights reserved.
Why Arteris FlexLLI?
• First: Silicon-proven with lowest risk
• Easiest: Automated environment for fast configuration and verification setup. Joint solution with Synopsys M-PHY.
• Most Flexible: Extensive configuration options for fastest time to market
Reduce risk and development time
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Copyright © 2012 MIPI Alliance. All rights reserved.
C2C
Remote ChipLocal Chip
o7266v3
REQ
or
RSP
REQ
or
RSP
REQ
or
RSP
REQ
or
RSP
Tx data width8 64 bits…
NT
TP
NT
TP
TxClkEn
TxClkEn
RxActive
RxActive
RxClk
TxClk
Modem Application Processor
memory memory
C2C was developed to enable a modem to use
the DRAM that is connected to an applications
processor
It allows for significant BOM cost savings of up
to $2.00 to the handset manufacturers of
smartphones
Other I/F PCI Express, HSI, Unipro do not
provide a low latency solution to allow modem
cache refill through shared memory - C2C latency = 100ns roundtrip
- Other I/F (pcie) >300 ns roundtrip
- HIS cannot support read throughput for cache refill
Major modem & app processor vendors already
implementing C2C
C2C
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Copyright © 2012 MIPI Alliance. All rights reserved.
Reduced Wire Routing Congestion with Arteris FlexNoC
Crossbar Architecture versus NoC Architecture
FlexNoC Datapath and Wire Density View in action
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Copyright © 2012 MIPI Alliance. All rights reserved.
Arteris Network-on-Chip(NoC) Press Release Arteris携手TSMC合作矽中介层Test Chip
飞思卡尔i.MX应用处理器取得Arteris FlexNoC授权
Arteris FlexNoc Interconnect IP Selected by Toshiba for SoC Deployment
Cavium licenses Arteris NoC Interconnect IP
Samsung adopts Arteris for mobile chips
Arteris FlexNoC(TM) Network-on-Chip (NoC) Solution Selected by LG Electronics
Arteris Network-On-Chip (NoC) Selected by Texas Instruments to Provide SoC Interconnect
北京新岸线公司手机SoC采用Arteris FlexNoC Interconnect与C2C技术
Pixelworks Again Chooses Arteris for Network-on-Chip (NOC) Interconnect Fabric IP
Arteris Network on Chip (NoC) Selected by NEC Electronics Europe for Advanced Development of Complex SoC Applications (Renesas)
NTT Electronics Completes a Graphic SoC Design Using Arteris NoC Technology
Arteris FlexNoC Interconnect IP助力Core Logic移动多媒体处理器设计
MtekVision Licenses Arteris FlexLLI MIPI Low Latency Interface (LLI) IP