mips datapath - single memory - no pipelining...32-bit mips datapath •one memory •instruction...
TRANSCRIPT
![Page 1: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/1.jpg)
MIPS Datapath – Single Memory – No Pipelining
Prof. James L. FrankelHarvard University
Version of 5:28 PM 23-Feb-2016Copyright © 2016 James L. Frankel. All rights reserved.
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32-bit MIPS Datapath
• One memory• Instruction memory & data memory are combined in a single memory
• No pipelining• Multicycle
![Page 3: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/3.jpg)
Notes on the Block Diagram
• Wires are not directional• Arrowheads are present to indicate which component is driving the wire
• Subscripting operator indicates bit selection• For example, [25.21] indicates that bits 25 to 21 are selected
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Memory
DataIn
Ad
dr
Dat
aOu
t
MemReadOrWrite
MemReadOrWrite
4
Sequencer All ControlSignals
All ControlSignals
32
32
32 32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
5
5
[20..16]
[15..11]
5
[25..21]
[31..26] & [5..0]
[25..0]Shift left two bits
2628[31..28]
4
Sign extend
[15..0]
16
Shift left two bits
32 32
32
32
5
5
32
32
ALU Status (Zero, Negative,Carryout, Overflow, etc.)
Add
er
Add
er
ALU
ALUFunctionincl. Carryin
PC
LoadPC
ClearPC
Mux
BranchOrJumpOr
Sequential
Mux
WriteRegFromMemory
OrALU
Mux
ALUSecondOpFromImmediateOrReg2
Mux
Regw#From20..16Or15..11
Mux
MemAddrFromPCOrALU
IR
LoadIR
RegReadOrWrite
RegisterArray
RegReadOrWrite
DataIn
Reg2 #
RegW #
Reg1
Reg2
Reg1 #
![Page 5: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/5.jpg)
Three-Operand R-Type Instructions
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Memory
DataIn
Ad
dr
Dat
aOu
t
MemReadOrWrite
MemReadOrWrite
4
Sequencer All ControlSignals
All ControlSignals
32
32
32 32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
5
5
[20..16]
[15..11]
5
[25..21]
[31..26] & [5..0]
[25..0]Shift left two bits
2628[31..28]
4
Sign extend
[15..0]
16
Shift left two bits
32 32
32
32
5
5
32
32
ALU Status (Zero, Negative,Carryout, Overflow, etc.)
Add
er
Add
er
ALU
ALUFunctionincl. Carryin
PC
LoadPC
ClearPC
Mux
BranchOrJumpOr
Sequential
Mux
WriteRegFromMemory
OrALU
Mux
ALUSecondOpFromImmediateOrReg2
Mux
Regw#From20..16Or15..11
Mux
MemAddrFromPCOrALU
IR
LoadIR
RegReadOrWrite
RegisterArray
RegReadOrWrite
DataIn
Reg2 #
RegW #
Reg1
Reg2
Reg1 #
![Page 7: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/7.jpg)
Three-Operand R-Type Instruction Observations• Implementation of the SLT (Set on Less Than) and SLTU (Set on Less
Than Unsigned) instructions• An unusual ALU output would need to be created for these instructions
• A 32-bit 0- or 1-valued result – not a bit-wise result
• 1 if true, 0 if false
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Multiply/Divide R-Type Instructions
• Multiply and Divide instructions are not supported by our block diagram
• Missing components• HI and LO registers
• Multiply and divide hardware
• Data paths for HI, LO, multiply, and divide hardware
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Shift R-Type Instructions
• Shift R-Type instructions are not supported by our block diagram
• Missing components• Shifter hardware – possibly a barrel shifter
• Data paths for shifter hardware• Including path for the sa bits and for the variable length shift distance
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ALU I-Type Instructions
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Memory
DataIn
Ad
dr
Dat
aOu
t
MemReadOrWrite
MemReadOrWrite
4
Sequencer All ControlSignals
All ControlSignals
32
32
32 32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
5
5
[20..16]
[15..11]
5
[25..21]
[31..26] & [5..0]
[25..0]Shift left two bits
2628[31..28]
4
Sign extend
[15..0]
16
Shift left two bits
32 32
32
32
5
5
32
32
ALU Status (Zero, Negative,Carryout, Overflow, etc.)
Add
er
Add
er
ALU
ALUFunctionincl. Carryin
PC
LoadPC
ClearPC
Mux
BranchOrJumpOr
Sequential
Mux
WriteRegFromMemory
OrALU
Mux
ALUSecondOpFromImmediateOrReg2
Mux
Regw#From20..16Or15..11
Mux
MemAddrFromPCOrALU
IR
LoadIR
RegReadOrWrite
RegisterArray
RegReadOrWrite
DataIn
Reg2 #
RegW #
Reg1
Reg2
Reg1 #
![Page 12: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/12.jpg)
ALU I-Type Instruction Observations
• The block diagram has data paths to sign extend the immediate operand, but ANDI, ORI, and XORI zero extend the immediate operand
• There is no data path for the implementation of the LUI (Load Upper Immediate) instruction
![Page 13: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/13.jpg)
Branch I-Type Instructions
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Memory
DataIn
Ad
dr
Dat
aOu
t
MemReadOrWrite
MemReadOrWrite
4
Sequencer All ControlSignals
All ControlSignals
32
32
32 32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
5
5
[20..16]
[15..11]
5
[25..21]
[31..26] & [5..0]
[25..0]Shift left two bits
2628[31..28]
4
Sign extend
[15..0]
16
Shift left two bits
32 32
32
32
5
5
32
32
ALU Status (Zero, Negative,Carryout, Overflow, etc.)
Add
er
Add
er
ALU
ALUFunctionincl. Carryin
PC
LoadPC
ClearPC
Mux
BranchOrJumpOr
Sequential
Mux
WriteRegFromMemory
OrALU
Mux
ALUSecondOpFromImmediateOrReg2
Mux
Regw#From20..16Or15..11
Mux
MemAddrFromPCOrALU
IR
LoadIR
RegReadOrWrite
RegisterArray
RegReadOrWrite
DataIn
Reg2 #
RegW #
Reg1
Reg2
Reg1 #
![Page 15: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/15.jpg)
Branch and Link I-Type Instructions
• Branch and Link I-Type instructions are not supported by our block diagram
• Missing components• No way to force use of GPR 31 ($ra) as the Regw # of the Register Array
• No path for the return address (incremented PC) to DataIn of the Register Array
![Page 16: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/16.jpg)
Jump J-Type Instruction
![Page 17: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/17.jpg)
Memory
DataIn
Ad
dr
Dat
aOu
t
MemReadOrWrite
MemReadOrWrite
4
Sequencer All ControlSignals
All ControlSignals
32
32
32 32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
5
5
[20..16]
[15..11]
5
[25..21]
[31..26] & [5..0]
[25..0]Shift left two bits
2628[31..28]
4
Sign extend
[15..0]
16
Shift left two bits
32 32
32
32
5
5
32
32
ALU Status (Zero, Negative,Carryout, Overflow, etc.)
Add
er
Add
er
ALU
ALUFunctionincl. Carryin
PC
LoadPC
ClearPC
Mux
BranchOrJumpOr
Sequential
Mux
WriteRegFromMemory
OrALU
Mux
ALUSecondOpFromImmediateOrReg2
Mux
Regw#From20..16Or15..11
Mux
MemAddrFromPCOrALU
IR
LoadIR
RegReadOrWrite
RegisterArray
RegReadOrWrite
DataIn
Reg2 #
RegW #
Reg1
Reg2
Reg1 #
![Page 18: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/18.jpg)
Jump and Link J-Type Instructions
• Jump and Link J-Type instructions are not supported by our block diagram
• Missing components• No way to force use of GPR 31 ($ra) as the Regw # of the Register Array for the
JAL instruction
• No path for the return address (incremented PC) to DataIn of the Register Array
![Page 19: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/19.jpg)
Jump Register Instructions
• Jump Register instructions are not supported by our block diagram
• Missing component for JR and JALR• No path from Reg1 to the input to the PC
• Missing component for JALR• No path for the return address (incremented PC) to DataIn of the Register
Array
![Page 20: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/20.jpg)
Load I-Type Instructions
![Page 21: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/21.jpg)
Memory
DataIn
Ad
dr
Dat
aOu
t
MemReadOrWrite
MemReadOrWrite
4
Sequencer All ControlSignals
All ControlSignals
32
32
32 32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
5
5
[20..16]
[15..11]
5
[25..21]
[31..26] & [5..0]
[25..0]Shift left two bits
2628[31..28]
4
Sign extend
[15..0]
16
Shift left two bits
32 32
32
32
5
5
32
32
ALU Status (Zero, Negative,Carryout, Overflow, etc.)
Add
er
Add
er
ALU
ALUFunctionincl. Carryin
PC
LoadPC
ClearPC
Mux
BranchOrJumpOr
Sequential
Mux
WriteRegFromMemory
OrALU
Mux
ALUSecondOpFromImmediateOrReg2
Mux
Regw#From20..16Or15..11
Mux
MemAddrFromPCOrALU
IR
LoadIR
RegReadOrWrite
RegisterArray
RegReadOrWrite
DataIn
Reg2 #
RegW #
Reg1
Reg2
Reg1 #
![Page 22: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/22.jpg)
Memory
DataIn
Ad
dr
Dat
aOu
t
MemReadOrWrite
MemReadOrWrite
4
Sequencer All ControlSignals
All ControlSignals
32
32
32 32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
5
5
[20..16]
[15..11]
5
[25..21]
[31..26] & [5..0]
[25..0]Shift left two bits
2628[31..28]
4
Sign extend
[15..0]
16
Shift left two bits
32 32
32
32
5
5
32
32
ALU Status (Zero, Negative,Carryout, Overflow, etc.)
Add
er
Add
er
ALU
ALUFunctionincl. Carryin
PC
LoadPC
ClearPC
Mux
BranchOrJumpOr
Sequential
Mux
WriteRegFromMemory
OrALU
Mux
ALUSecondOpFromImmediateOrReg2
Mux
Regw#From20..16Or15..11
Mux
MemAddrFromPCOrALU
IR
LoadIR
RegReadOrWrite
RegisterArray
RegReadOrWrite
DataIn
Reg2 #
RegW #
Reg1
Reg2
Reg1 #
![Page 23: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/23.jpg)
Store I-Type Instructions
![Page 24: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/24.jpg)
Memory
DataIn
Ad
dr
Dat
aOu
t
MemReadOrWrite
MemReadOrWrite
4
Sequencer All ControlSignals
All ControlSignals
32
32
32 32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
5
5
[20..16]
[15..11]
5
[25..21]
[31..26] & [5..0]
[25..0]Shift left two bits
2628[31..28]
4
Sign extend
[15..0]
16
Shift left two bits
32 32
32
32
5
5
32
32
ALU Status (Zero, Negative,Carryout, Overflow, etc.)
Add
er
Add
er
ALU
ALUFunctionincl. Carryin
PC
LoadPC
ClearPC
Mux
BranchOrJumpOr
Sequential
Mux
WriteRegFromMemory
OrALU
Mux
ALUSecondOpFromImmediateOrReg2
Mux
Regw#From20..16Or15..11
Mux
MemAddrFromPCOrALU
IR
LoadIR
RegReadOrWrite
RegisterArray
RegReadOrWrite
DataIn
Reg2 #
RegW #
Reg1
Reg2
Reg1 #
![Page 25: MIPS Datapath - Single Memory - No Pipelining...32-bit MIPS Datapath •One memory •Instruction memory & data memory are combined in a single memory •No pipelining •Multicycle](https://reader034.vdocument.in/reader034/viewer/2022042520/5f461bb31273d75c9f29a41b/html5/thumbnails/25.jpg)
Memory
DataIn
Ad
dr
Dat
aOu
t
MemReadOrWrite
MemReadOrWrite
4
Sequencer All ControlSignals
All ControlSignals
32
32
32 32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
5
5
[20..16]
[15..11]
5
[25..21]
[31..26] & [5..0]
[25..0]Shift left two bits
2628[31..28]
4
Sign extend
[15..0]
16
Shift left two bits
32 32
32
32
5
5
32
32
ALU Status (Zero, Negative,Carryout, Overflow, etc.)
Add
er
Add
er
ALU
ALUFunctionincl. Carryin
PC
LoadPC
ClearPC
Mux
BranchOrJumpOr
Sequential
Mux
WriteRegFromMemory
OrALU
Mux
ALUSecondOpFromImmediateOrReg2
Mux
Regw#From20..16Or15..11
Mux
MemAddrFromPCOrALU
IR
LoadIR
RegReadOrWrite
RegisterArray
RegReadOrWrite
DataIn
Reg2 #
RegW #
Reg1
Reg2
Reg1 #