mips processor continued
DESCRIPTION
MIPS processor continued. Review. Different parts in the processor should be connected appropriately to be able to carry out the functions. Connections depending on what we need Learnt R-type, lw, sw, beq. lw & sw?. Data path only for lw and sw (answer). - PowerPoint PPT PresentationTRANSCRIPT
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MIPS processor continued
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Review
• Different parts in the processor should be connected appropriately to be able to carry out the functions.
• Connections depending on what we need• Learnt R-type, lw, sw, beq
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lw & sw?
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Data path only for lw and sw (answer)
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Data path for both R-type and memory-type instructions
add $rd, $rs, $rt, format: opcode (6 bits) rs (5 bits) rt (5 bits) rd (5 bits) 00000 funct (6 bits)lw $rt, offset_value($rs): opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)sw $rt, offset_value($rs): opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)
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Data path for both R-type and memory-type instructions
add $rd, $rs, $rt, format: opcode (6 bits) rs (5 bits) rt (5 bits) rd (5 bits) 00000 funct (6 bits)lw $rt, offset_value($rs): opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)sw $rt, offset_value($rs): opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)
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Answer
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Datapath for R-type, memory, and branch operations
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Datapath for R-type, memory, and branch operations (Answer)
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Datapath for Memory, R-type and Branch Instructions, plus the control signals
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11/15/2007 5:02:11 PM week-13-3.ppt 11
Jump Instruction
• Jump instruction seems easy to implement– We just need to replace the lower 28 bits of the
PC with the lower 26 bits of the instruction shifted by 2 bits• The shift is achieved by simply concatenating 00 to the
jump offset
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12
Implementing Jumps
• The one we have supports arithmetic/logic instructions, branch instructions, load and store instructions– We need also to support the jump instruction
– What are the changes we need to make?
0 0 1 00 031
opcode Address
26 25 0
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Add j?
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14
Supporting Jump Instruction
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11/25/2007 10:54:43 PM week-14-1.ppt 15
In Class Exercise – Supporting Jump Register