mitigating the performance degradation due to faults in non-architectural structures constantinos...

Mitigating the Performance Degradation Mitigating the Performance Degradation due to Faults indue to Faults in Non-Architectural Structures Non-Architectural Structures

Constantinos Kourouyiannis Veerle DesmetNikolas LadasYiannakis Sazeides

University of Cyprus Ghent University

6th HiPEAC Industrial WorkshopParis, 26/11/2008

6th HiPEAC Industrial Workshop 2

MotivationMotivation Technology scaling: Opportunities and Challenges Reliability and computing tomorrow

• Failures will not be exceptional• Various sources of failures

soft-errors, process-variation, wear-out, hardware and software bugs

Key challenge: provide correct operation with little or no performance degradation in the presence of faults with low-cost solutions


Architectural vs Non-Architectural FaultsArchitectural vs Non-Architectural Faults So far research mainly focused on correctness Emphasis architectural structures, e.g. caches, registers,

buses However, faults can occur in non-architectural structures,

e.g. predictor and replacement arrays Faults in non-architectural structures may degrade

performance


Non-Architectural Faults: Why care?Non-Architectural Faults: Why care? Miss deadlines: unacceptable for real time applications Non-architectural resources cover significant fraction of the

active area of modern cores where temperature is higher• more susceptible to wear-out and process variation faults

If architectural resources protected, with increasing fault frequency/chip eventually non-architectural resources will become a performance bottleneck


This talk…This talk…

Quantifies performance implications of faults in a non-architectural array-structure, specifically a line predictor

Introduces and evaluates a simple detection scheme and repair technique to protect it against faults


OutlineOutline Fault Modeling Arrays background Performance Implications of Faults in a line predictor Detection - Repair Mechanisms Results Conclusions and Future Direction

Work in progress…


Array Fault Modeling Key ParametersArray Fault Modeling Key Parameters Number of faults

• with increasing faults higher potential for performance degradation Location of Faults

• frequently accessed entries more critical, output bit more serious Fault Clustering

• Granularity/“radius” of faults Model for each fault

• e.g. cell stuck-at-1 more critical if bits stored in the cell are biased towards zero


Non-architectural ResourcesNon-architectural Resources Arrays

• line predictor• branch direction predictor• return-address-stack• indirect jump predictor• memory dependence prediction• replacement arrays (various caches)• ...

Non-Arrays• branch target address adder• memory prefetch adder• ....


Worst-case performance (cell faults)Worst-case performance (cell faults)

up to 27%


Worst-case - Hit rateWorst-case - Hit rate


Detection and RepairDetection and Repair Possible to consider previously proposed techniques for

architectural arrays BUT detection and correction for non-architectural arrays

does not have to be exact and provide full repair. Sufficient to minimize the performance effects of faults Our proposition: Address Remapping Exploit non-uniformity of accesses

• Observed experimentally that few entries in the line-predictor are accessed.

• So, the remapping has a wide range of entries to go.


(Sorted) Access Distributions for LP(Sorted) Access Distributions for LP

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1 256511

7661021

12761531

17862041

22962551

28063061

33163571

38264081

entries

no

rmal

ized

cu

mu

lati

ve a

cces

ses


accessed cells

accessed defective cells

not accessed cells

not accessed defective cells

Original Access-Fault Map Rotate accesses down by 1 row

1 instead of 3 accessed faulty cells

Proposed Approach for Remapping Proposed Approach for Remapping


accessed cells

accessed defective cells

not accessed cells

not accessed defective cells

Original Access-Fault Map Remap row accesses1 instead of 3 accessed faulty

cells

Proposed Approach (for cell faults) Proposed Approach (for cell faults) 0

1

2

3

4

5

6

7

7

0

1

2

3

4

5

6


Detection and Repair SchemeDetection and Repair Scheme


Index Remapping UnitIndex Remapping Unit

0

1

2

3

4

5

6

7

original index

XOR 1

value decided from search engine

1

0

3

2

5

4

7

6

remapped index


Remapping Search EngineRemapping Search Engine

40

0

20

3

100

50

0

0

Access map

Fault map

1

0

0

1

1

0

0

0



40

0

20

3

100

50

0

0

Access map

Fault map

1

0

0

1

1

0

0

0

Defective_accessedA=Σi(Access mapi * Fault map) = 40+3+100=143



0

40

3

20

50

100

0

0

Remapped Accesses

Fault map

1

0

0

1

1

0

0

0

Best remapping = XOR 1(fewer defective accessed entries)

Defective_accessedΒ= Σi(Access mapi * Fault map) = 20+50=70


SimulatorSimulator sim-alpha simulator EV6 processor with 15 stage pipeline Baseline configuration: No hard-fault, no remapping SPEC CPU 2000 benchmarks – 100 M instructions

• Representative regions We compare performance without and with remapping for

random fault maps


Random results without and with remappingRandom results without and with remapping


Summary-ConclusionsSummary-Conclusions Reliability should not be limited on correctness but also

consider performance Faults in non-architectural resources can degrade the

performance of a processor and this may make them important to deal with

Proposed framework for detection and repair:• Detects the case where there we have many defective accessed

entries• Finds the best possible remapping• Applies the remapping

Remapping works very well in almost all cases


Future WorkFuture Work Experiments with other non-architectural structures, such as

direction and indirect predictors and replacament arrays for I-cache, D-cache, TLB.

Applicability of ideas to architectural structures.


AcknowledgmentsAcknowledgments Elli Demetriou and Costas Vrionis

Funding: University of Cyprus, Ghent University, SARC, HiPEAC, Intel


Thanks!Thanks!


BACKUP SLIDESBACKUP SLIDES


Processor PipelineProcessor Pipeline

27

. . .

0

4

40954092

8

Adder

4 nops

PCCT1

CT 2

Instruction cache

Line predictor

Branch predictor

RAS

Update line prediction

adder

CT 3

Update program counter

4 nops

CT 4

Miss

Hit

L2

4xn

n n

4xn

=

NLS_PC

Correct PC

Fetch stage Slot stage Commit stage

. . .

Writeback stage

Assign value to PC

(indirect jump)


Line predictor structure Line predictor structure

28

.

.

.

.

.

.

TAG 91 2

Predecode bits

Instruction Cache

way0 way1

51

2

inst0 inst1 inst2 inst3

sb0 sb1 sb2 sb3 sb0 sb1 sb2 sb3

inst0 inst1 inst2 inst3

sbX

Valid sb


Random results without and with remappingRandom results without and with remapping


Faults and ArraysFaults and Arrays Faults may occur in different parts of an array Not practical to study faults at physical level

.

.

.

. . .cell cell ce

llcell cell cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell

cell cell

cell cell cell cell cell cell

WL

WL

WL

WL

WL

WL

WL

WL

WL

WL

BL BL’ BL

BL’ BL BL’ BL BL’ BL BL’ BL BL’

cell

driver

decoder bitline

wordlinewordline


Functional Faults and Array Logical ViewFunctional Faults and Array Logical View

cell

output bit

row address

data_in

Abstractions that ease study of faults Fault locations: cell, input address, output data

mitigating the performance degradation due to faults in non-architectural structures constantinos...

Documents

nonarchitectural arrays

performance slide

performance effects

presence of faults

replacement arrays faults

performance bottleneck

process variation faults

progress slide