mixed mode ch5_v1
TRANSCRIPT
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Memories
Prof. Jader A. De Lima
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Memories
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Moore´s law
LV LP techniques
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Memory Array
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Memory Banks
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Memory Timing
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Non-Volatile Memories (NVM´s)
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Read-Only Memory (ROM)
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Mask-programmed ROM
• ROM is programmed at the manufacturer’s site according to the
specifications of the customer
• economical only when manufactured in large quantities
• once programmed, it cannot be reprogrammed.
• The basic storage element is an NPN bipolar transistor, connected in
common-collector configuration, or a MOSFET in common-drain
configuration.
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
stored 1 stored 0
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Diffusion-programming ROM
• highest density: bit line contact to discharge transistor can be shared by two-bit cells
• very long fabrication cycle time: diffusion programming at early process stage
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
VIA-2 Contact Programming ROM (conventional)
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• The VIA-2 is final stage of process and base process can be completed just
before VIA-2 etching and remaining process steps are quite few
• VIA-2 ROM fabrication cycle time is about 1/5 of the diffusion ROM
• Drawback: poorer density diffusion area and contact must be separated
in each ROM bit cell
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
VIA-2 Contact Programming ROM (new)
• 8-bit block with GND on each side
• higher density
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Multi-level ROM
• transistor-cell (W/L) adjusted according to its logic state
• 2 bits per cell
• Intel (1980´s)
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Programmable ROM (PROM)
• programmed by the customer
• fuse links: metal or poly-Si
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
polyfuse/metalfuse layout
poly-Si/metal fuses
• line heats up to fusion by self-heating mechanism due to current
intensity during programming mode
• fusion increases its resistance and eventually opens the link
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Stacked-Gate Non-Volatile Memory (EPROM/EEPROM)
• DAHC: Drain-Avalanche Hot Carrier
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• HCI: Hot Carrier Injection
• either an electron or hole gains sufficient kinetic energy to overcome a
potential barrier necessary to break an interface state
• can be injected into the gate dielectric, where they can get trapped
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
pinch-off region
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• Fowler-Nordheim tunneling
• current flowing across MOS structure at the high electric field in
the oxide; electrons tunnel from semiconductor conduction band
into oxide conduction band through part of the potential barrier at
the semiconductor-oxide interface (oxide 5-10 nm thick)
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• floating-gate MOS (FAMOS) transistor
• not electrically erasable (only by time-consuming UV-irradiation)
• compatible with double-poly processes
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
EPROM with UV-irradiation erasing
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Flash Memories
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Different p-channel Flash write/erase operations (a) programming with
DAHC and erase with FN tunneling action
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
(b) PGM: DAHC
ERS: FN tunneling (source)
(c) PGM: HCI
ERS: FN tunneling (drain)
(d) PGM: HCI
ERS: FN tunneling
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• Default state is “1”, as current will flow through the channel under
application of an appropriate voltage to the control gate.
• Set to "0“ by applying > 5V (typically) to the CG. Channel is now
turned on, so electrons can flow from the source to the drain. Current is then
sufficiently large to cause some high energy (hot) electrons to jump through the
insulating layer onto the FG.
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• To erase a NOR flash cell (resetting it to the "1" state), a large voltage of
the opposite polarity is applied between the CG and source, pulling the
electrons off the FG through quantum tunneling
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• NAND has significantly higher storage capacity than NOR
• NAND flash has found a market in devices to which large files
are frequently uploaded and replaced: MP3 players, digital
cameras and USB drives
• NOR flash is faster, but it's also more expensive. NOR is most
often used in mobile phones
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• specific type of EEPROM that is erased and programmed in large blocks
Flash memories
NOR-gate flash (Intel, 1988)
Nor-gate Flash: each cell has one end connected directly to ground, and the
other end connected directly to a bit line.
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
NAND-gate flash (Toshiba 1989)
• several transistors (8, 16, 32, …) are connected in series
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
When a cell is read, its gate is set to 0V, while the other gates of
the stack are biased with a high voltage (typically 4–5 V, say)
the other gates work as pass-transistors, regardless of their
threshold voltage.
An erased NAND Flash cell has a negative threshold voltage; on
the contrary, a programmed cell has a positive threshold voltage
but, in any case, less than 4V.
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
NOR Flash: is a random access device, appropriate for code
storage application. It is designed for use in linear program
storage for applications such as boot loaders and BIOS, with its
key benefit being the ability to satisfy requirements that need to
read code wherein each word of data is needed to carry out
instructions.
NAND Flash: a sequential access device appropriate for mass
storage applications. It is optimized for file structures where
each word does not need to be read, but instead provides that
sectors of data can be moved to and from media supporting a
hard drive like repository structure for data storage to support
file systems and allocation tables (FAT)
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Static RAM (SRAM)
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• high speed memory
• data stored as long as power is supplied to the circuit.
• low density high cost!!
6-transistor SRAM cell
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
TFT: Thin-Film Transistor
• Load is formed by using polysilicon as a PMOS device. This PMOS
transistor is called a Thin Film Transistor (TFT), and it is formed by
depositing several layers of polysilicon above the silicon surface.
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
effective resistance ranges from
~ 11 x 1013 W to 5 x 109 W
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Dynamic RAM (DRAM)
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
CS: typically, 30-50fF
“1”: VCS = VDD – VTH
“0”: VCS = 0V
READ: the voltage of the selected word-line is high;
readout process is destructive !!!
write process should occur after reading.
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Charge Sharing
CB
CS
TS Vchave
Linha de dados
+
+-
-
VB
VS
QB = CB VB
QS = CS VS
QT = CB VB + CS VS
CT = CB + CS
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• Data stored in CS should be transferred to data line, - to capacitor CB
– is a quite critical case. The voltage change across CB, after the
transfer, is
DV = VB - Veq = (VB - VS ) CS / ( CB + CS )
reduction of original voltage difference (VB - VS ) by factor
CS / (CB + CS) , as commonly CB >> CS
need for sense amplifiers coupled to bit line
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
CS: typically, 30-50fF
“1”: VCS = VDD – VTH
“0”: VCS = 0V
Ex: Cs = 30fF; CL = 1pF
VDD = 2.2V; VTH = 0.5V
DVB = (VB - VS ) CS / ( CB + CS )
VB(0) = 0V: DVB = (1.1 - 0) 30f /1.03p = +32mV
VB(1) = 0V: DVB = (1.1 – 1.7V) 30f /1.03p = -17mV
CB
CS
TS Vchave
Linha de dados
+
+-
-
VB
VS
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
1-Mb DRAM.
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
?
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
SRAM Sense Amplifiers
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
d) Latched-based SRAM Sense Amplifiers
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
DRAM Sense Amplifiers
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Sense amplifier with dummy-cell sensing structure
• During reading, if LHS cell is read, the dummy word line
on RHS is acessed ( and vice-versa).
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
VDD
SE
SE
CS CS CS
L
...CSCS
...CS
R
BLL BLR
L0L1 R0 R1
dummy
cell
dummy
cell
EQ
Sense amplifier with dummy-cell sensing structure
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
VDD
SE
SE
CS CS CS
L
...CSCS
...CS
R
BLL BLR
L0L1 R0 R1
dummy
cell
dummy
cell
EQ
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
VDD
SE
SE
CS CS CS
L
...CSCS
...CS
R
BLL BLR
L0L1 R0 R1
dummy
cell
dummy
cell
EQ
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• Decoupling of bit-line capacitance
• decoupling devices MT1 and MT2 are initially turned on. SA is not active and
load at its input is CBL + CSA, with CB >> CSA.
•AS is activated when differential input-voltage Vin is large enough.
At this moment, MT1 and MT2 are turned off and load at AS input is only CSA.
Faster arbitration.
• during re-writing, MT1 and MT2 are turned on again.
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
• initially, Fs turns on MN5.
• Ft turns on decoupling devices MT1 and MT2. Both are
turned off with differencial Vin is large enough.
• Vin is then quickly amplified by MN3, MN4 and MN5, as bit-
line capacitances are de-coupled.
• when Vin reaches a given value, Ft goes high, turning on
MT1 and MT2, which allows full Vin swing.
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Alpha-particles
1 particle ~1million carriers
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Alpha-particles
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Memory
Array
Redundant
columns
Redundant
rows
Column Decoder
Ro
w D
eco
der
Row
Address
Column
Address
Fuse
Bank:
Redundancy
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Redundancy and Error Correction
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Address Decoding
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Example:
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Row Decoders
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
Dynamic Decoders
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
WL3
GND GNDPrecharge devices
WL2
WL1
WL0
VDD A0 A0 A1 A1 A0 A0 A1 A1
VDD
VDD
VDD
VDD
WL3
WL2
WL1
WL0
Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder
Propagation delay is primary concern
Dynamic Decoding
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
A0A1 A0A1 A0A1 A0A1 A2A3 A2A3 A2A3 A2A3
A1 A0 A0 A1 A3 A2 A2 A3
WL0
WL1
Splitting decoder into two or more logic layersproduces a faster and cheaper implementation
A NAND decoder using 2-input pre-decoders
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
BL0 BL1 BL2 BL3
D
A0
A1
S0
S1
S2
S3 2 i
np
ut
NO
R d
eco
der
Advantage: speed (tpd does not add to overall memory access time)
Disadvantage: large transistor count
only 1 extra transistor in signal path
4 input pass-transistor based column decoder
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Introdução ao Projeto de CI´s de Sinais MistosJader A. De Lima UFSC, 2014
BL0 BL1 BL2 BL3
D
A0
A0
A1
A1
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
buffers
progressive sizing
combination of tree and pass transistor approaches
Solutions:
4-to-1 tree based column decoder