Mixed Signal LSI

Practical design method of CMOS mixed signal circuits

Kanazawa UniversityMicroelectronics Research Lab.Akio Kitagawa

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0.1 Introduction

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Books of reference• For students who wants to learn the practical CMOS

analog circuit design (*)– R. Jacob Baker, CMOS: Circuit Design, Layout, and Simulation,

3rd Edition, ISBN 978-0-470-88132-3, Wiley-IEEE Press (2010)– R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, 2nd Edition,

ISBN 978-0-470-29026-2, Wiley-IEEE Press (2009)– 松澤昭, はじめてのアナログ電子回路実用回路編, ISBN 978-4-

06-156545-6, 講談社 (2016)• Course wares

– http://jaco.ec.t.kanazawa-u.ac.jp/edu/– http://cmosedu.com/ * These books does not cover the RF (Radio-frequency) circuits.Book of reference for RF circuit design：- RF Microelectronics, B. Razavi, ISBN 0-13-887571-5, Prentice Hall (1998)

Course policy1. Download the lecture slide of the on the timeline

of WebClass.2. Watch a video of the online lecture on the

timeline of WebClass.3. If you have a question, post the question on the

BBS or the timeline (Click the icon of a pen.)4. Submit the assignment by the deadline.

– Academic misconduct and scholastic dishonesty such as a plagiarizing or cheating on examinations can be assigned a penalty based on the University code.

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Q & A• During class (is not available for the time being)

– Feel free anytime in the class.

• Office hours (is not available for the time being)– 5th period on Wednesday– Request for an appointment.

• BBS or timeline on WebClass– For questions about the lecture.

• Email– For questions about your grading, attendance.– kitagawa@merl.jp 5

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Distribution system

Health care

Nursing-care

Home safety and automation

Environment conservation

Cultivation

Disaster prevention

The Internet of Everything

Intelligent transport systems

Keywords: Wireless communication, Energy Harvesting, Sensor integrationAn analog mixed signal (AMS) LSI is fundamental to advanced electronic systems.Regional Information

Medical services

Growing information technology toward a real world and an daily life

Maintenance of infrastructureConventional cyberspace

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Example of Mixed-Signal LSI

Image rejectionDecimatorChannel filterDemodulator

Other functions logic

PLL(RF signal generation) DSM (Frequency control)

LNA(Impedance matching)

Mixer(Frequency conversion)

Amp., ADC(Analog-to-Digital conversion)

Regulator(Power supply)

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Wave forms in mixed signal circuitsContinuous time (CT) Discrete time (DT)

Discrete value

Con-tinuousvalue

Continuous time analog circuit

Discrete time analog circuit

Digital circuitTime domain analog circuit

DSM: Delta-Sigma Modulation

b0

b1

b2

b3

DSM(Pulse width or Delay time)

Binary

(Pulse density or bits)

(Voltage or Current) (Voltage, Current or Charge)

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A/D partition in mixed-signal LSIName of circuit block Function Analog/Digital RemarksAAF (Anti-Aliasing Filter) Band-limitation Analog feasible only in analog

SF (Smoothing Filter) Transformation from discrete time to continuous time

Analog feasible only in analog

LNA (Low Noise Amp.) Impedance matching Analog feasible only in analog

Mixer Down-conversion and Up-conversion Analog for RF signal

Digital for IF signal

Power supply circuits (e.g. Regulator, Reference Voltage, Rectifier)

Voltage regulation, DC-DC conversion,Voltage/Current reference

Analog

ADC (Analog-to-Digital Converter) Analog-to-Digital conversion Analog + Digital

DAC (Digital-to-Analog Converter) Digital-to-Analog conversion Analog + Digital

PLL (Phase Locked Loop) RF frequency synthesis Analog or Digital

DSM (Delta-Sigma Modulator) Digital frequency control of PLL Digital

Memory （Sens-Amplifier, Memory Cell, DLL）

Memory of digital data Analog + Digital

Processor (DSP, MCU) Signal processing, system control Digital

Filter Hardware signal processing Analog for RF signal

Digital for baseband

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Digital design flowSpecification sheet for digital block

Signal flow and transfer function

Block diagram of system architecture

HDL (Hardware Description language)

Logic Synthesis Place and Route

Min. Typ. Max. Min. Typ. Max.電源電圧 1.8 3.3 3.5 1.8 2.1 3.3 V消費電流 ― ― 2.2 mA利得 ― 15 ― dB周波数 300 426 475雑音指数（NF） ― 2 ― dB1dBｺﾝﾌﾟﾚｯｼｮﾝﾚﾍﾞﾙ ― 0 ― dBmｲﾝﾀｾﾌﾟﾄﾎﾟｲﾝﾄ（IIP3） ― 9.6 ― dB入力ｲﾝﾋﾟｰﾀﾞﾝｽ ― 50 ― Ω出力ｲﾝﾋﾟｰﾀﾞﾝｽ ― 500 ― Ω端子間ｱｲｿﾚｰｼｮﾝ（OUT→IN） 20 dB

項目 条件設計値規格値

単位PHSRFU

GPSRFU

ETCRFU

PHSIFU

GPSIFU

ETCIFU

UserModeIFU

DAC

ADC

ADC

WaveFormGEN

QuadDamed

CLKGEN

DBPI/F

DSPI/F

GPSI/F

PHSI/F

ETCI/F

ETC Demed

GPSCorrerator

Marge to analog blocks

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Analog design flowSpecification sheet for analog block

Signal flow and transfer function

Block diagram of system architecture

Circuit schematic with behavior models

Circuit schematic with Transistors Layout artworkvｄｄ

gnd

M18.56/2

M28.56/2

M310.24/2

M410.24/2

M55/2

M65/2

M78/2

M95/2

M85/2

M118/2

M108/2

M125/2

M135/2

M145/2

M155/2

M168/2

M175/2

M185/2

Vin+ Vin- Vout+Vout-

Vbias

Vcm

0.5pF 0.5pF3.5kΩ

Min. Typ. Max. Min. Typ. Max.電源電圧 1.8 3.3 3.5 1.8 2.1 3.3 V消費電流 ― ― 2.2 mA利得 ― 15 ― dB周波数 300 426 475雑音指数（NF） ― 2 ― dB1dBｺﾝﾌﾟﾚｯｼｮﾝﾚﾍﾞﾙ ― 0 ― dBmｲﾝﾀｾﾌﾟﾄﾎﾟｲﾝﾄ（IIP3） ― 9.6 ― dB入力ｲﾝﾋﾟｰﾀﾞﾝｽ ― 50 ― Ω出力ｲﾝﾋﾟｰﾀﾞﾝｽ ― 500 ― Ω端子間ｱｲｿﾚｰｼｮﾝ（OUT→IN） 20 dB

項目 条件設計値規格値

単位PHSRFU

GPSRFU

ETCRFU

PHSIFU

GPSIFU

ETCIFU

UserModeIFU

DAC

ADC

ADC

WaveFormGEN

QuadDamed

CLKGEN

DBPI/F

DSPI/F

GPSI/F

PHSI/F

ETCI/F

ETC Demed

GPSCorrerator

Marge to digital blocks

CAD software

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Schematic Entry

Circuit Simulation

Layout Artwork

Layout Parasitic Extraction

Layout vs Schematic (LVS)

Design Rule Check (DRC)

HDL CodingHDL Coding

Logic SimulationLogic Simulation

Logic SynthesisLogic Synthesis

Timing SimulationTiming Simulation

Place and RoutePlace and Route

Design Rule Check (DRC)

Design Rule Check (DRC)

Mixed-signal integration

Analog Circuits Digital Circuits

Layout Editor

Circuit Simulator

LPE Tool

LVS Tool

DRC Tool

Schematic Editor Text Editor

HDL Simulator

Logic Synthesis Tool

HDL Simulator

P&R Tool

DRC Tool

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Structure of MOSFET and Bipolar Tr.

n-Si substrateSiO2

p-Sin-Si n-Si

contact L

gate

tOX

n-Sip-Si

source drain emitter collectorbase

WB

WE: Emitter Width

MOSFET Bipolar Tr.

Transition frequency fT depends on Leff. Transition frequency fT depends on WB.Leff

Weff

NOTE: The peak transition frequency of bipolar transistor also depends on the base width WB and the base resistance (small WE is better).

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0.1

1

10

100

1000

1996 2000 2004 2008 2012 2016 2020

Peak

Tra

nsiti

on fr

eque

ncy

(GH

z)

Year

Cellular

CDMA

WLAN 802.11a

350nm

250nm

180nm

130nm 90nm65nm

45nm32nm 22nm

16nm 11nmCMOSHigh Speed Bipolar

Bipolar

CMOS Amp., Mixer (20dB)

CMOS ADC, Small Digital

Trends of operating frequency

ITRS 2008

Peak Transition Frequency:The frequency for the current gain h21 = 1 (0dB) of the transistor.

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Performance of ADC architecture

10k

100k

1M

10M

100M

1G

4 6 8 10 12 14 16 18 20 22 24

10G

1k

Resolution (bit)

Sam

plin

g Fr

eque

ncy

(Hz)

HDD DVD

Digital IFVDSL

Digital TV

LANDigital Camera

Motor Servo

ADSL

GSM, PDC

Celluar PhoneCD/MD

Σ-Δ ADC

Pipeline ADCFlashADC

Technology front is limited by GBP of amplifier, switching speed of CMOS-switch, and process variation of capacitance.

SAR ADC

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Advantages and disadvantages of technology scaling

1/(Design Rule) (Log)

Perf

orm

ance

(Lo

g)

Scaling (Shrink)

2LMismatchNoise

SwingSignalRangeDynamic

2

1L

nIntegratio

1

1L

GBP

1LGain

(for constant IDS)

Supply voltage 1L,

Speed

1/Power consumption

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Figure of merit (FOM) of analog circuits

• Before ITRS2004 edition:FOM was defined for each category of circuits.– LNA: Low noise amplifier– VCO: Voltage controlled

oscillator– PA: Power amplifier– ADC: Analog-to-Digital

converter– SerDes(SERializer/DESerializer)

2fPAEGPFOM poutPA

PNFfIIPGFOM LNA

)1(3

PfLffFOMVCO

}{

12

0

PfFOM S

ENOB

ADC

)2( 0

P : Power consumptionIIP3: Third Order Input Intercept PointNF : Noise figureL: Spurious power PAE: Power efficiency

PRRFOM MuxDeMuxB

SerDes

ENOB0: Effective number of bitsfS : Sampling frequencyRB: Data RateRMuxDeMux: Bit count of parallel data

Quiz

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Which circuit is better for a sensitivity and a signal-to-noise ratio?

Digital outputSensor

Sensor Digital output

12dB 16bit

0dB 18bit

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Suggested answer

Equivalent gain for LSB

Why is the increment of 1bit equivalent with the amplification of 6dB (2 times)?

=

0dB amplifier = No amplifier (no noise)

12dB 16bit

0dB 18bit

Suggested answer

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Maximum number of N-bit binary code = 2N -1Dynamic range of N-bit binary code system = (2N -1)/1Maximum number of (N+1)-bit binary code = 2N+1 -1Dynamic range of (N+1)-bit binary code system = (2N+1 -1)/1

Then, the amplitude of signal that is equivalent for the differential dynamic range between (N+1)-bit and N bit system is corresponding to (2N+1 -1)/ (2N -1) ≒ 2 ≒ 6.02dB

Note that this calculation is made on a condition of M = 0 (no noise shaping) and OSR = 1 (no oversampling). More precise analysis is shown in next slide.

21

)]12

log(20log)1020[(02.611][

log)1020(]12

log[2076.102.6][max

MOSRMbitENOB

OSRMM

NdBSNR

M

M

SNR for quantization noise and ENOB(Effective number of bits) in oversampling condition

M : Order of noise-shaping transfer functionOSR: Oversampling ratio

M = 0, OSR = 128, then ENOB = 4.5[bit], ΔSNRmax = 27[dB]M = 1, OSR = 128, then ENOB = 10.6[bit], ΔSNRmax = 64[dB]

Speed Accuracy GainExample

Speed = Accuracy = Gain

NOTE: The theoretical base will be discussed later.