mixed-signal socs with in situ self-healing circuitry

7/28/2019 Mixed-Signal SoCs With In Situ Self-Healing Circuitry

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Mixed-Signal SoCs With

In Situ Self-Healing CircuitryChristopher Maxey

Booz Allen Hamilton

Sanjay Raman

Defense Advanced Research Projects Agency

Kari Groves, Tony Quach, Len Orlando,

and Aji Mattamana

Air Force Research Laboratory

Gregory Creech

Ohio State University

Jay Rockway

SPAWAR Systems Center Pacific

h ADVANCES IN INTEGRATED circuit technologieshave increasingly enabled the single-chip integra-

tion of multiple analog and digital functions, result-

ing in the development of complex mixed-signal

systems-on-a-chip (SoCs). In particular, scaling

channel lengths in CMOS processes to 32 nm and

below has pushed the fmax and ft of silicon CMOS

transistors in excess of 230 and 440 GHz, respec-

tively [1] and the fmax and ft of SiGe BiCMOS transis-

tors in excess of 350 and 300 GHz, respectively [2].

In this regime, it is possible to realize state-of-the-art

RF performance on the same platform used to fa-

bricate digital processors and dense memory cores.

On the other hand, pattern variations partly due to

the complex masks needed for subwavelength litho-

graphy and random variables such as dopant loca-

tion effects become statistically significant at these

dimensions. Therefore, a

major consequence of the

drive towards ever smaller

transistor gate lengths is a

dramatic increase in intra-

wafer and intradie process

variability (as measured by

standard deviation) in crit-

ical device p aramet ers

such as threshold voltage,

effective channel length, etc. Figure 1 plots intra-wafer variability for several process nodes based on

lithographic limitations published by the ITRS [3]

along with projections of yield reduction in these

nodes from Monte Carlo simulations corroborated

by measurements of representative circuits [4]. In

aggregate, variability in several parameters simulta-

neously can greatly exacerbate circuit performance

degradation. Such variation can have significant

impact on digital circuits, but the effect is magni-

fied for analog and mixed-signal circuits due to the

heightened sensitivity of such designs to device

mismatch and the integration of numerous individ-

ual subblocks that can vary greatly in noise charac-

teristics, operating frequency, etc. Consequently,

mixed-signal circuit performance yield degrades

more rapidly with technology scaling than with

digital circuits.

To deal with the impact of variability in advanced

technologies, designers often must conservatively

accommodate worst-case corner case simulations

and relax target performance specifications to

Editors notes:

This article discusses the goals and recent achievements of the HEALICs

program. The program_s aim is to enhance wireless systems with sensors,

actuators, and mixed-signal control loops in order to improve their

performance yield.

VHaralampos-G. Stratigopoulos, TIMA Laboratory, and

Alberto Valdes-Garcia, IBM T. J. Watson Research Center

0740-7475/12/$31.00 B 2012 IEEENovember/December 2012 Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC 27

Digital Object Identifier 10.1109/MDT.2012.2226014

Date of publication: 23 October 2012; date of current version:

17 January 2013.


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guarantee a sufficient postfabrication parametric

yield. These traditional corner-based design techni-

ques require coverage of an extensive and expo-

nentially growing parameter space that becomes

intractable for large designs. Furthermore, efforts tocontrol variability through aggressive fabrication

process management or extensive Design-for-Yield

(DFY) procedures are costly and ultimately limited

in effectiveness [5]. An alternative approach advo-

cated in the Self-HEALing Mixed Signal Integrated

Circuits (HEALICs) program initiated by the

authors is to recover lost performance by employ-

in g on -ch ip sen sors ( meters) , act uat ors

(knobs) and analog/digital control loops that

measure the effects of device variability in situ and

consequently adjust tunable circuit parameters todrive the chip towards a more optimal performance

point. This control circuitry can be applied at both

the sub-block and system level allowing the designer

to focus on performance goals and not on yield

related issues. As with any control system, chal-

lenges related to stability, response times, system

bandwidth, etc. cannot be overlooked when im-

plementing self-healing, and overcoming these

challenges while maintaining performance has

been an important aspect of the program. Further-

more, HEALICs design teams must also address the

possibility that process variability adversely im-

pacts the self-healing circuitry itself, and compen-

sation for this effect has been a particular point of

emphasis.Calibration techniques for mixed-signal circuits

such as analog-to-digital converters (ADCs) have

been studied extensively; however, they typically

focus on fully digital techniques that rely on

known-good states stored in on-chip memory [6].

Furthermore, analog calibration techniques have

been investigated for individual circuit blocks [7],

[8], but they have not been studied extensively for

full SoC applications. HEALICs technology com-

bines analog and digital techniques for low-power

overhead, embedded comprehensive healing forSoCs that compensates not only for process

variation, but also for the extreme environments

and long operational lifetimes experienced by the

Department of Defense (DoD) electronic systems,

as well as other systems: aviation, automotive,

industrial automation, etc. For this reason, we

anticipate that the technology developed under

this program will greatly enhance long-term

reliability in addition to improving performance

yield.

Figure 1. Variability in critical transistor parameters for submicron process nodes

plotted along with the associated impact on performance yield for digital and

mixed signal circuits [3], [4].

IEEE Design & Test of Computers28

Digitally Enhanced Wireless Transceivers


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Program objectives and planTo measure the efficacy and power efficiency of

self-healing, the program design teams have targeted

the yield-improvement and power consumptionoverhead goals described in Table 1.

Performance yield is defined as the percentage of

die per wafer that meets or exceeds a set of prede-

fined circuit performance metrics. The performance

yield for the baseline (or nonself-healing) die is

calculated using the following formula:

Baseline Performance Yield DBaseline

NBaseline(1)

where DBaseline is the number of baseline die that

meet or exceed the same set of performance metricsand NBaseline is the maximum number of baseline die

that can be fabricated on a single wafer. Without self-

healing, baseline die are expected to yield poorly if

held to the same performance standards as the self-

healing chips. In most cases, the defined perfor-

mance criteria exceed state-of-the-art for each

design. In Phase I, the program targeted mixed-signal

cores or sub-blocks, and in Phase II the program

targets larger system-on-a-chip designs.

Posthealing performance yield can be calculated

using:

Posthealing Performance Yield DHEALICs

NBaseline(2)

where DHEALICs is the number of self-healing die per

wafer that meet or exceed all metrics. By dividing

DHEALICs by NBaseline, the performance yield is subject

to an area overhead correction to ensure that the

portions of the chip that are exclusively for self-

healing do not consume an excessive fraction of the

die area. Combining (1) and (2) yields the following

formula used for calculating posthealing performance

yield and accounting for self-healing area overhead:

Posthealing Performance Yield

%PosthealingYieldNHEALICs

NBaseline(3)

where NHEALICs is the number of self-healing die that

can be fabricated on a single wafer and %Postheal-

ingYield is the percentage of self-healing die that

meet all defined metrics. In some cases, self-healing

can enable a smaller chip to meet the performance

metrics compared to a baseline design, i.e.,

NHEALICs > NBaseline. In this case, (3) allows for the

performance yield to exceed 100%, which can be

interpreted as reducing the fabrication costs for agiven part. While not an explicit program require-

ment, we also expect that self-healing will result in a

reduction of performance variance as measured over

the full set of die, indicating that techniques are truly

compensating for process variability and not for poor

initial design or inaccurate device models. This effect

will be readily apparent in the yield measurements

reported in the following section of this paper.

Self-healing designs are also required to incur

minimal power consumption overhead relative to

the baseline design. Power overhead may be mea-

sured at an appropriate healing duty cycle if self-

healing is not expected to be continuously operating.

While the extreme scaling of silicon transistors is

primarily responsible for the variability described as

the motivating factor for self-healing technology, it

simultaneously makes it possible to incorporate

substantial processing capabilities on-chip for self-

healing at low area and power overhead.

To date, the HEALICs program has demonstrated

advancements in self-healing yield and performance

Table 1 HEALICs program goals for self-healing.

November/December 2012 29


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in RF transceivers and subblocks, including ADCs,

phase-locked loops (PLLs), and power amplifiers

(PAs). These designs have been fabricated in

processes ranging from 180 nm SiGe BiCMOS to

32 nm silicon-on-insulator (SOI) CMOS, demonstrat-

ing the efficacy of self-healing across a range oftechnologies and variability effects. Table 2 sum-

marizes the individual program design teams and

the mixed-signal SoCs they have targeted for

demonstrating their self-healing methods.

This paper will describe results obtained by the

IBM, Raytheon, and UCLA teams, however, several

other important self-healing research activities in this

program are not covered in detail because of space

constraints. Examples include self-healing image

reject mixers [9] and LNAs [10] developed at

Georgia Tech (a member of the NGES team), novelI-gate MOSFETs for self-healing circuits [11] devel-

oped at University of Texas at Dallas (a member of

the IBM team), and built-in self-test synthesis tech-

niques for self-healing [12] developed at Auburn

University (a member of the BAE Systems team).

Recent accomplishmentsThis section will cover the measurement and

yield improvement results for several of the fabri-

cated and measured Phase I designs.

Self-healing PA and PLL designs

A research team led by IBM has demonstrated a

self-healing 28 GHz PA in 45 nm SOI and a self-

healing 2127 GHz PLL in 32 nm SOI. Together, these

components were designed for a Ka-band radio

transceiver.The high-level schematic of the self-healing PA

designed by CalTech is shown in Figure 2 [13]. The on-

chip integrated sensors include RF power sensors at

the input and output to estimate gain, junction

temperature sensors to assist with the estimation of

power added efficiency (PAE), and dc current sensors

to determinepower consumption. Thepower sensor is

calibrated by measuring the output of a few represen-

tative die and calculating a ratio between sensed

power and actual power. These data are included in

the healing algorithm for each of the chips. On-chipcontrol knobs include bias actuation mechanisms at

each of the PA stages and tunable transmission lines at

the PA output used to adjust matching impedances.

An embedded fully custom microprocessor is used to

determine the knob settings necessary to minimize

power consumption for a desired output power (thus

maximizing PAE). The control algorithm affords a

level of flexibility in operation and the target output

power can be designated at run time. Through this

control loop, the PAE is increased from 5.6% in the

Table 2 Summary of target self-healing demonstration circuits.




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baseline case to 7.3% in the healed state. PAE is

defined as:

PAE100RF Output PowerRF Input Power

dc power consumption:(4)

Furthermore, the 1 decibel compression point

and the gain are increased from 11.3 to 13.8 dBm

and from 20.3 to 23.7 dB, respectively.

This PA chip was also an excellent platform for

investigating the potential efficacy of self-healing for

Figure 2. Self-healing PA: (a) high-level schematic and (b) die photograph (1.8 mm 0 1.7 mm).



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improving RF/mixed-signal circuit reliability. To this

end, CalTech performed an extreme test of reliability

healing by intentionally and sequentially inducing

damage in one of the PA output stages through theuse of laser ablation and initiating the healing

algorithm after each stage of damage. Notably,

self-healing was capable of recovering significant

amounts of lost output power by autonomously ad-

justing the output matching to compensate for the

change in impedance loading. A set of curves show-

ing output power data for the undamaged and for

three successive ablations is shown in Figure 3 along

with before and after photos of the PA. Ultimately,

the self-healing algorithm is shown to recover up to

4.8 dBm of output power compared to the baselinesettings.

Concurrent with the design of the PA, the IBM

team designed and tested a 25-GHz self-healing

PLL fabricated in 32 nm SOI technology. The PLL

architecture was a hybrid analog/digital design

with proportional and integral paths following the

phase/frequency detector. A peak detector at the

output of the oscillator acts as the primary sensing

path for the self-healing algorithm, which, in this

case, is primarily responsible for reducing phase

noise at a 10-MHz offset from the carrier to

G124 dBc/Hz. The bias values and VCC are

measured along with the frequency to complete

the in situ virtual phase noise model of the PLLperformance [14]. During testing, a quadratic

relationship is derived that relates the output

amplitude, output frequency, bias voltage, bias

current, tuning band, and VCC value to the mea-

sured phase noise. Once this equation is deter-

mined, the coefficients for each term are stored in

on-chip memory. After self-healing is initiated, the

knob settings are stepped through incrementally. An

on-chip processor then evaluates the stored equa-

tion for the sampled sensor values and returns an

estimate of the phase noise. If phase noise is at aminimum, the algorithm stops and the knob settings

are held constant. The algorithm is implemented

completely on-chip in a 16-bit arithmetic logic unit

which uses a 32-word data memory and a 256-word

instruction memory for low healing overhead. Using

this algorithm, the performance yield of the PLL is

improved from $20% in the baseline case to 100%

posthealing for 55 measured die. Healing power

overhead was $10% and healing area overhead

was 12.7%.

Figure 3. Self-healing result for intentionally damaged PA: (a) no damage; (b) 1/8 stage removed;

(c) 1/4 stage removed; and (d) 1/2 of stage removed. Micrographs of PA: (e) before and

(f) after damage.




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Self-healing pipelined ADC

R esearchers f rom UC LA

have pursued the design of a

self-healing ultralow-power pi-

pelined 1 Gsps ADC with a flash

output stage in 65 nm CMOS

[15]. Therefore, canonical self-healing involved adding control

loops and processors to the

baseline chip with the con-

straint of minimizing the over-

head created by these auxiliary

blocks. For this ADC design,

however, the application of

self-healing was found to signif-

icantly decrease the size of the

yielding part relative to a non-

yielding baseline part by en-abling the use of minimum

sized devices in critical analog

parts of the design.

Flash ADCs are well known

for realizing extremely high

sample rate data converters at

the expense of high comparator

cou nt f or h igh n umbers of

digital output bits. Further-

more, these comparators ex-

hibit significant capacitanceand gain mismatch in deeply

scaled CMOS that would other-

wise be an attractive fabrication

process for such ADCs. One

method to combat the mis-

match (the baseline approach)

is to use devices with larger

than minimum dimensions that

exhibit lower variability stan-

dard deviation; but this ob-

viates the speed, the size, andthe power advantages of using

65 nm or better technology.

Alternatively, a self-healing al-

gorithm designed to mitigate

the effect of comparator mis-

match would enable the use of

minimum size devices. Specifically, in this imple-

mentation, capacitance and gain mismatch healing

is employed in the 4-bit input stage and capaci-

tance mismatch healing is employed in the follow-

ing four stages. The final three stages have sufficient

performance margin to not require additional

healing. Figure 4(a) shows the general ADC

architecture schematic.

Figure 4. (a) High-level ADC schematic showing the self-healing required

for each stage. Inset: op-amp comparator schematic and (b) comparison

of self-healing design to recently published ADCs in various submicron

CMOS technologies. (All data points except for self-healing points

compiled from [16]).



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Through this approach, the ADC demonstrated

56.7 dB of signal-to-noise-and-distortion ratio

(SNDR) equivalent to 8.38 effective bits with a

491 MHz input signal sampled at 1 Gsps. More

importantly, the power consumption was merely

33 mW, resulting in an ADC figure-of-merit (FOM)

of$99 fJ/conversion step. The ADC FOM is calcu-lated as follows:

FOM Power

2ENOB Sampling Frequency: (5)

Compared to a baseline design utilizing larger

comparator transistors, this design was 41 smaller

and $100 less power consumptive. A conservative

clock tree design consumed approximately a third of

the power and could have been further reduced

with aggressive design. Furthermore, simulation re-

sults indicate approximately a 16% reduction in theFOM if the design was ported to 45 nm technology. A

plot comparing this result to others in recent liter-

ature is shown in Figure 4(b).

Self-healing radar receivers

In addition to subblocks dedicated for use in

communications systems, self-healing has been

shown to dramatically increase performance yield

for DoD-relevant radar and EW receivers as well. For

example, a team led by Raytheon developed a

618 GHz self-healing radar receiver with several on-chip sensors and actuators designed to reduce I/Q

phase mismatch, PLL output spur level, and gain

fluctuations across the spectral field of regard [17].

Figure 5a shows the design schematic.

Unique to this team, an on-board ARM process-

ing core was synthesized and fabricated to run a

modified Nelder-Mead optimization algorithm used

to efficiently minimize mismatch, suppress spurs

and flatten gain response. The ARM core utilizes

130.4 KB of memory, but only 36 KB are specific to

the healing circuitry. In this case, HEALICs techni-

ques are shown to take advantage of baseline pro-

cessing and memory capabilities to reduce healing

area and power overhead. To reduce phase mis-

match, for example, an auxiliary mixer is used to

produce a dc value proportional to the amount of

phase offset between the Iand Q paths. Feedback to

variable amplifiers in each path are used to fine tune

the phase offset, and the Nelder-Mead algorithm is

used to establish values for each amplifier that mini-

mizes mismatch. The search routine is applicable to

bound-constrained and discretized optimization

problems and has shown efficacy for the types of

self-healing required for the radar receiver designed

in this effort. Furthermore, Nelder-Mead is particu-

larly robust in the presence of noisy measurement

data, which is expected from the low-power sensors

typically incorporated in self-healing designs. Toheal PLL spur levels, a similar algorithm is used with

slightly different knobs and sensors. A power de-

tector on the output is fed to the algorithm, which

independently sets two knobs: charge injection on

the VCO control line and a trigger setting to establish

the precise timing of the charge injection. Finally, to

heal gain flatness, the output power sensor is mo-

nitored and the tunable amplifiers are further ad-

justed while maintaining optimum phase matching.

Figure 5b shows histograms for healed mismatch

and gain flatness. The area shaded in green repre-sents the performer-defined metric that sets the stan-

dard for yield in the case of this design. For both of

these metrics, yield was improved from 0% in the

baseline case to 100% in the healed case.

The Raytheon team is also investigating the

effects of ageing on circuits, which is of particular

interest given that some defense, as well as com-

mercial, electronic systems are fielded for decades.

The main cause of aging in PMOS is negative bias

temperature instability (NBTI) which shifts the

threshold voltage over time and is especially delete-rious for gate lengths shorter than 100 nm. Hot-

carrier injection (HCI) is an important in ageing

mechanism for NMOS and has an amplified impact

on mixed signal circuits compared to pure digital

circuits. NCSU, a member of the Raytheon team, is

developing techniques for the purposes of designing

self-healing knobs and sensors specifically for

ageing and has published initial results in [18].

Self-healing 60 GHz radio transceiver

Another research group at UCLA has successfully

incorporated self-healing sensors, actuators and

control loops to substantially improve the perfor-

mance yield of a 60 GHz, 4 Gbps communications

transceiver fabricated in 65 nm CMOS [19]. The

schematic for this design, identifying additions spe-

cific to self-healing, and the photograph of the fabri-

cated die are shown in Figure 6.

Circuitry dedicated solely to self-healing repre-

sented 8% of the total area. Likewise, the power

consumption of these blocks amounted to only 3.7%




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of the chips total. On-chip sensors include an envel-

ope sensor for tracking the output spectrum; a tem-

perature sensor for estimating the kT noise level; apower sensor for estimating the path gain; and an

auxiliary ADC for quantizing the sensor outputs. Self-

healing control knobs include phase offset and dc

offset for the individual I/Q paths; PA and mixer

current biases; variable gain LNAs; and an auxiliary

DAC for generating control signals. The transceiver

utilizes a loop-back healing approach, where the Tx

is used to drive the Rx for the purposes of measuring

the radios performance. This minimizes the need

for off-chip calibration of the on-chip sensors. The

central component for mediating the self-healing

algorithms is the parameter estimator (PE) block

shown in the block diagram in Figure 6a. The (PE)comprises a 128-point FFT processor synthesized in

digital logic along with spectrum magnitude estima-

tion for both the Iand Q channels. The PE is respon-

sible for estimating LO leakage power, image tone

power, among other parameters and consumes only

0.56 mm2 of die area and 4.8 mW. The DAC control-

ler, meanwhile, provides test tones for measuring

circuit response to 1-tone and 2-tone tests.

Critical performance parameters for this design

include receiver noise figure; transmitter linearity;

Figure 5. (a) Radar receiver schematic showing location and connections for self-healing sensors and

knobs; histograms showing improvement in performance yield for phase error (b) and gain flatness (c).



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Figure 6. 60 GHz, 4 Gbps self-healing transceiver: (a) high-level schematic; (b) die

photograph (4 mm4 mm); and performance yield enhancement for (c) image tone

rejection and (d) receiver NF.




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and image tone power. The target noise figure was

6 dB, and self-healing was able to correct the

baseline value of 9.4 dB to 4.9 dB for 100% of the

chips. Likewise, the target Tx third-order output

intermodulation product level (OIM3) and the target

image tone rejection level were both 40 dBc, and

the on-chip algorithm was able to correct baselinevalues of32.4 dBc and 32.8 dBc to 42.6 dBc

and 41.8 dBc, respectively, on 100% of the die.

To heal the image tone power, the envelope

sensor captures the spectrum of the transmitter out-

put and the PE estimates the magnitude of the power

in each of the FFT frequency bins. After the estima-

tion is performed, the phase offset, relative gains and

dc offsets between the I/Q channels are adjusted to

minimize the power at the image frequency. A

coarse/fine search algorithm is implemented in cus-

tom logic to close the control loop and minimize the

measured image power. Likewise, to heal the noise

figure, the temperature sensors are sampled by the

auxiliary ADC to estimate the current kT level. Given

the relationship between stage gain and overall

noise figure, the NF can be optimized by adjusting

the gain in each of the three stages. Figure 6c and d

show histograms for each of these performance pa-rameters comparing the healed state to the baseline

state. Since the area of the baseline design is con-

strained by the number of bond pads and since the

self-healing circuitry fit in vacant parts of the die,

there is no area overhead correction necessary for

this part.

IN SITU SELF-HEALING has been shown to dramat-

ically improve the performance yield of RF/mixed-

signal designs at deep-submicron nodes. A wide

range of cores and subblocks from PAs to entire

Table 3 Summary of yield improvement through self-healing for the circuits described in this paper.



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transceivers have been co-integrated with sensors,

actuators, and control loops, resulting in the resto-

ration of lost performance at low power and die area

overhead. A summary of some of the performance

yield improvement capabilities highlighted in this

paper is included in Table 3.

Activities that promise to extend these capabil-ities to the system-on-a-chip level are already

underway, and a repository of self-healing IP has

been established at the Air Force Research Labo-

ratory to facilitate a more widespread adoption of

these techniques throughout the DoD design

community.

AcknowledgmentsThe authors would like to thank all of the per-

formers on the HEALICs program for their effortstowards achieving the program goals; in particular,

those who contributed to the work outlined in this

paper: principal investigators Dr. Jose Tierno and

Mr. Daniel Friedman from IBM, Prof. Behzad Razavi

from UCLA, Mr. Gerry Sollner from Raytheon, Prof.

Frank Chang also from UCLA, and their teams. The

HEALICs program was developed at and funded by

the Defense Advanced Research Projects Agency.

The work presented in this paper was supported

through Air Force Contracts FA8650-09-C-7924,

FA8650-09-C-7925, and FA8650-09-C-7926; Navygrants N66001-09-1-2029 and N66001-09-1-2030; and

Navy contract N66001-09-C-2023. The views, opi-

nions, and/or findings contained in this article are

those of the authors and should not be interpreted

as representing the official views or policies, either

expressed or implied, of the Defense Advanced

Research Projects Agency or the Department of

Defense. h

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radio-on-a-chip, in Proc. 2012 IEEE Int. Solid-State

Circuits Conf. (ISSCC), Feb. 1923, 2012.

Christopher Maxey is an Associate with Booz

Allen Hamilton. His research interests include mixed-

signal and RF circuits. He has a Masters degree in

electrical engineering from Virginia PolytechnicInstitute and State University (Virginia Tech) in

2004. He is a member of the IEEE.

Sanjay Raman is a Program Manager at DARPA,

currently on assignment from Virginia Polytechnic

Institute and State University (Virginia Tech), where

he is a Professor of Electrical and Computer

Engineering. His research interests include silicon-

based RF/microwave millimeter-wave circuits; self-

correcting RF/mixed-signal circuits; heterogeneous

integration; and sensor microsystems. He has a PhD

in electrical engineering from the University of

Michigan in 1998. He is a senior member of the IEEE.

Kari Groves is an RF Engineer with the Air Force

Research Laboratory.

Tony Quach is an RF Engineer with the Air Force


Len Orlando is an RF Engineer with the Air Force


Aji Mattamana is an RF Engineer with the Air

Force Research Laboratory.

Gregory Creech is recently retired from the AirForce Research Laboratory. He is now with Ohio

State University.

Jay Rockway is with SPAWAR Systems Center

Pacific.

h Direct questions and comments about this article

to Chri stopher M axey , B ooz A ll en Hami lton;

[email protected].


mixed-signal socs with in situ self-healing circuitry

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