mmu memory management unit chapter # 14 memory management unit1
TRANSCRIPT
MMUMMUMemory Management UnitMemory Management Unit
Chapter # 14Chapter # 14
Memory Management Unit11
Group#13Group#13
•Asmaa Rabie Abdualaziz•Islam Ameen Abdualaziz•Doaa Ahmed Mohamed•Sherif Mohamed Medhat
22 Memory Management Unit
Presented by:Presented by:
Presented toPresented to:•Dr.Amr Wassal
•CMP 2012
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
3 Memory Management Unit
What What will we learn from will we learn from chapterchapter??
Learn basics of ARM MMU and some basic concepts that underlie the use of the
virtual memory
44 Memory Management Unit
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
5 Memory Management Unit
• Virtual addresses: Assign by Compiler and Linker
•Physical addresses : Access the actual hardware components
IntroductionIntroduction
66 Memory Management Unit
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
7 Memory Management Unit
Moving From An MPU To An MMUMoving From An MPU To An MMU
88 Memory Management Unit
•What is the difference between active and dormant region?
•Difference Between MPU & MMU
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
9 Memory Management Unit
How Virtual Memory works How Virtual Memory works
0x0800 00e3
0x0400 00e3
1010 Memory Management Unit
The components of a virtual The components of a virtual memory systemmemory system
Virtual memory Physical memoryMMU
Relocation register
Page
Page frame
Page tables
PTE
1111 Memory Management Unit
Defining Regions Using PagesDefining Regions Using Pages
Stack
Data
Text
Region 3
Region 2
Region 1
Virtual Memory Physical Memory
Page tables
RAM
Flash
PTEPagePage
frame
1212 Memory Management Unit
Memory Management Unit13
Memory Management Unit14
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
15 Memory Management Unit
• Page tables
• Translation Lookaside Table (TLB)
• Domain and access permission
• Caches and write buffer
• CP15: c1 control register
• Fast Context Switch Extension
Details Of The ARM MMUDetails Of The ARM MMU
1616 Memory Management Unit
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
17 Memory Management Unit
• L1Entries for translating 1 MB pagesPointers to the starting address to level 2 page tables
• L2Fine page table
Coarse page table
Page Table Page Table
1818 Memory Management Unit
Level 1 page table accepts four types of entry
• A 1MB section translation entry
• A directory entry that points to a fine L2 page table
• A directory entry that points to a coarse L2 page table
• A fault entry that generates an abort exception
Level 1Level 1
1919 Memory Management Unit
L1 page entriesL1 page entries
The upper 12 bits of the page table entry replace the upper 12 bits of the virtual address to generate the physical address
Domain
BufferedCached
Section Entry
2020 Memory Management Unit
L1 page entriesL1 page entries
a pointer to the base address of a second-level coarse page table
Coarse Entry
Domain information for the 1 MB sectionof virtual memory represented by the L1 table entry.
2121 Memory Management Unit
L1 page entriesL1 page entries
Fine Entry
Domain information for the 1 MB section
of virtual memory represented by the L1 table entry.
2222 Memory Management Unit
L1 page entriesL1 page entries
Fault Entry
2323 Memory Management Unit
Translation Table Base AddressTranslation Table Base Address
The CP15:c2 register holds the translation table base address (TTB)—an address pointing to the location of the master L1 table in virtual memory.
2424 Memory Management Unit
Level 2 page table accepts four types of entry
•A large page entry defines the attributes for a 64 KB page frame.
•A small page entry defines a 4 KB page frame.
• A tiny page entry defines a 1 KB page frame.
•A fault page entry generates a page fault abort exception when accessed.
Level 2Level 2
2525 Memory Management Unit
L2 page entriesL2 page entriesThe entry also has four sets of permission bit fields
A large PTE includes the base address of a 64 KB block of physical memory.
Large page
2626 Memory Management Unit
L2 page entries
The entry also has four sets of permission bit fields
A small PTE holds the base address of a 4 KB block of physical memory
Small page
2727 Memory Management Unit
L2 page entriesL2 page entries
The entry also has 1 permission bit fields
A tiny PTE provides the base address of a 1 KB block of physical memory.
Small page
2828 Memory Management Unit
Fault
L2 page entriesL2 page entries
2929 Memory Management Unit
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
30 Memory Management Unit
Translation Lookaside BufferTranslation Lookaside Buffer
•Fully associative cache of recently used translations
•Stores Access permission set
•Use round-robin replacement algorithm
•Supports flush and lock operations
3131 Memory Management Unit
L1 Page table virtual-to-physical L1 Page table virtual-to-physical memory translation using 1 MB memory translation using 1 MB
sectionssections
L1 master page table
Selects physical memoryBase offset
offsetBase
Page table entry
Translation table base address
Virtual address
physical address
Copied to TLB
3232 Memory Management Unit
Two-level virtual-to-physical Two-level virtual-to-physical address translation using address translation using
coarse page tables coarse page tables
L1 master page tableCoarse L2 page table
L1 Page table entry
L2 Page table entry
Virtual address
physical address Physical Base Page offset
Page offsetL2 offsetL1 offset
Step 1
Step 2
Copied to TLB
L2 Page table base
address
Translation table base address
3333 Memory Management Unit
TLB OperationsTLB Operations
42f467263889ab5635de9001f8d9
8845878778428fd39999
Flush
6726
9001
8fd3
Lock down
3434 Memory Management Unit
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
35 Memory Management Unit
Domain & Access permissionDomain & Access permission
There are two different controls to manage a task’s access permission to memory.
•Primary: is the Domain.
•Secondary: is access permission set in the page tables.
Domain control basic access to virtual memory by isolating on area of memory from another when sharing common virtual memory map
3636 Memory Management Unit
Domain bit access bit assignment Domain bit access bit assignment
3737 Memory Management Unit
Page Table-Based Access permissionPage Table-Based Access permission
3838 Memory Management Unit
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
39 Memory Management Unit
Caches and Write BufferCaches and Write Buffer
4040 Memory Management Unit
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
41 Memory Management Unit
Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration
4242 Memory Management Unit
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
43 Memory Management Unit
Fast Context Switch Extension Fast Context Switch Extension (FCSE)(FCSE)
•Enables multiple independent tasks to run in a fixed overlapping area of memory
•FCSE eliminates the need of flushing the cache and TLB
•Uses process ID to convert overlapping virtual address(VA) to a unique modified virtual address(MVA)
•MVA = VA + (0x200000 * process ID)
Memory Management Unit44
1. Save active tasks context and put the task in dormant state
2. Write the awakening task’s process ID to CP15:c13
3. Locate set the current tasks' domain to no access and the awakening task’s domain to client access by writing to cp15:c3:c0
4. Restore the context of awakening task
5. Resume execution of re stored task
Steps to perform context switch when Steps to perform context switch when using FCSEusing FCSE
4545 Memory Management Unit
Agenda Agenda • 1. What we will learn from chapter ?1. What we will learn from chapter ?• 2. Introduction 2. Introduction • 3. 3. Moving From An MPU To An MMUMoving From An MPU To An MMU• 4. How Virtual Memory works 4. How Virtual Memory works
4.1 The components of a virtual memory system4.1 The components of a virtual memory system
4.2 Defining Regions Using Pages4.2 Defining Regions Using Pages
4.3 Multitasking and The MMU4.3 Multitasking and The MMU
4.4Memory Organization in a Virtual Memory System 4.4Memory Organization in a Virtual Memory System • 5. Details Of The ARM MMU5. Details Of The ARM MMU• 6. Page Table 6. Page Table
6.1 Level 16.1 Level 1
6.2 6.2 Translation Table Base AddressTranslation Table Base Address
6.3 Level 26.3 Level 2• 7. Translation Lookaside Buffer7. Translation Lookaside Buffer
7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections
7.2 Two-level virtual-to-physical address translation using coarse page tables7.2 Two-level virtual-to-physical address translation using coarse page tables
7.3 7.3 TLB OperationsTLB Operations• 8. Domain & Access permission8. Domain & Access permission• 9. Caches and Write Buffer9. Caches and Write Buffer• 10.10. Coprocessor 15 and MMU configurationCoprocessor 15 and MMU configuration• 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE)• 12. A small virtual memory system12. A small virtual memory system
46 Memory Management Unit
• 3 Tasks
• The same execution region
• 256 MB of memory for peripheral devices
Very simple example!
A small virtual memory systemA small virtual memory system
4747 Memory Management Unit
1. Define a fixed system software region
2. Define 3 virtual memory maps for the 3 tasks
3. Locate regions in step 1 & 2 into the physical memory
4. Define and locate the page tables within the page table region
5. Data structures for regions and page tables
6. Initialize the MMU, caches, and write buffer
7. Set up a context switch routine to switch between tasks
How to setup the MMU?How to setup the MMU?
4848 Memory Management Unit
• 16 KB for the master table
• 1 KB each for the fourL2 tables.
• 12 KB free memory
• Shared libraries
• The transition routines for switching from privileged mode to user mode during a context switch
• The OS kernel code and data
• Fixed addressing to avoid the complexity of remapping when changing to a system mode context.
1- Fixed system software region1- Fixed system software region
1MB
32 KB
32 KB
32 KB
• Controls the system device I/O space
• Noncached & Nonbuffered region
4949 Memory Management Unit
2- Define Virtual Memory Maps for Each 2- Define Virtual Memory Maps for Each TaskTask
32 KB
32 KB
• Text, data, and stack of the running user task.
• Remap the Task region on task switch
Discussed!
5050 Memory Management Unit
3- Locate Regions in Physical Memory3- Locate Regions in Physical Memory
5151 Memory Management Unit
4- Define and Locate the Page Tables4- Define and Locate the Page Tables
5252 Memory Management Unit
5- Define Page Table and Region Data 5- Define Page Table and Region Data StructuresStructures
5353 Memory Management Unit
1) Page Table struct
typedef struct {unsigned int vAddress; //Address of a 1 MBsection of virtual memory
unsigned int ptAddress; //Location in virtual memory.
unsigned int masterPtAddress; //Address of the parent master L1 page table.
unsigned int type; //COARSE, FINE, or MASTER
unsigned int dom; // Domain value
} Pagetable;
5- Define Page Table and Region Data 5- Define Page Table and Region Data StructuresStructures
1) Page Table struct
typedef struct {unsigned int vAddress; //Address of a 1 MBsection of virtual memory
unsigned int ptAddress; //Location in virtual memory.
unsigned int masterPtAddress; //Address of the parent master L1 page table.
unsigned int type; //COARSE, FINE, or MASTER
unsigned int dom; // Domain value
} Pagetable;
54 Memory Management Unit
5- Define Page Table and Region Data 5- Define Page Table and Region Data StructuresStructuresExample:
/* vAddress, ptAddress, masterPtAddress, type , dom*/
Pagetable systemPT = {0x00000000, 0x1c000, 0x18000, COARSE, 3};
55 Memory Management Unit
5- Define Page Table and Region Data 5- Define Page Table and Region Data StructuresStructures
1) Region struct
typedef struct {
unsigned int vAddress; // Address of the region in virtual memory
unsigned int pageSize; //Size of a virtual page
unsigned int numPages; // Number of pages in the region
unsigned int AP; // Region access permissions
unsigned int CB; // Cache and write buffer attribute
unsigned int pAddress; // Address of the region in virtual memory
Pagetable *PT; // pointer to the Pagetable in which the region resides
} Region;
56 Memory Management Unit
5- Define Page Table and Region Data 5- Define Page Table and Region Data StructuresStructuresExample:
/* vAddress, pageSize, numPages, AP, CB , pAddress , *PT */
Region kernelRegion = {0x00000000, 4, 16, RWNA, WT, 0x00000000, &systemPT};
57 Memory Management Unit
6- Initialize the MMU, caches, and write 6- Initialize the MMU, caches, and write bufferbuffer
1. Initialize the page tables in main memory by filling them with FAULT entries
2. Fill in the page tables with translations that map regions to physical memory.
3. Activate the page tables.
4. Assign domain access rights.
5. Enable the MMU and cache hardware
58 Memory Management Unit
6- Initialize the MMU, caches, and write 6- Initialize the MMU, caches, and write bufferbuffer1)Initialize the page tables:
mmuInitPT(Pagetable *);
• Fill the Page Table by Fault entries
• The size of the table is determined by reading the type of Page table defined in pt->type (Master, Coarse, Fine)
Memory Management Unit59
6- Initialize the MMU, caches, and write 6- Initialize the MMU, caches, and write bufferbuffer
2)Filling Page Tables with Translations
mmuMapRegion(Region * region ){switch (region->PT->type){
case SECTION mmuMapSectionTableRegion(region);
case COARSE: mmuMapCoarseTableRegion(region);
case FINE: mmuMapFineTableRegion(region);
}}
Memory Management Unit60
6- Initialize the MMU, caches, and write 6- Initialize the MMU, caches, and write bufferbuffer3) Activating a Page Table
• Why?
• mmuAttachPT(Pagetable *pt);
• It activates an L1 master page table by placing its addressinto the TTB in the CP15:c2:c0 register
• Or activates an L2 page table by placing its base address into an L1 master page table entry
Memory Management Unit61
6- Initialize the MMU, caches, and write 6- Initialize the MMU, caches, and write bufferbuffer
4) Assigning Domain Access and Enabling the MMU
• All active memory areas must have a domain assignment
• The minimum domain configuration places all regions in the same domain and sets the domain access to client access.
• void domainAccessSet(unsigned int value, unsigned int mask);
Memory Management Unit62
6- Initialize the MMU, caches, and write 6- Initialize the MMU, caches, and write bufferbuffer
5) Enable the MMU
/* Call the previous functions */void mmuInit(){
mmuInitPT(Pagetable *); //Init the Page Tables
mmuMapRegion(Region * region ) //Map The regions
mmuAttachPT(Pagetable *pt); //Activate the Page Table
void domainAccessSet(unsigned int value, unsigned int mask); //Set Domain Access
}
63 Memory Management Unit
7- Establish a Context Switch 7- Establish a Context Switch ProcedureProcedure
1. Save the active task context and place the task in a dormant state.
2. Flush the caches
3. Flush the TLB to remove translations for the retiring task
4. Configure the MMU to use new page tables
5. Restore the context of the awakening task
6. Resume execution of the restored task
6464 Memory Management Unit
Any Questions Any Questions
65 Memory Management Unit