MOCVDMOCVD Growths are performed at room pressure or Growths are performed at room pressure or

low pressure (10 mtorr-100 torr)low pressure (10 mtorr-100 torr) Wafers may rotate or be placed at a slant Wafers may rotate or be placed at a slant

to the direction of gas flowto the direction of gas flow– Inductive heating (RF coil) or conductive heatingInductive heating (RF coil) or conductive heating

Reactants are gases carried by NReactants are gases carried by N22 or H or H22 into into chamberchamber– If original source was a liquid, the carrier gas is If original source was a liquid, the carrier gas is

bubbled through it to pick up vaporbubbled through it to pick up vapor– Flow rates determines ratio of gas at wafer Flow rates determines ratio of gas at wafer

surfacesurface

Schematic of MOCVD Schematic of MOCVD SystemSystem

http://nsr.mij.mrs.org/1/24/figure1.gif

http://www.semiconductor-today.com/news_items/2008/FEB/VEECOe450.jpg

AdvantagesAdvantages

Less expensive to operateLess expensive to operate– Growth rates are fastGrowth rates are fast– Gas sources are inexpensiveGas sources are inexpensive

Easy to scale up to multiple wafersEasy to scale up to multiple wafers

DisadvantagesDisadvantages

Gas sources pose a potential health Gas sources pose a potential health and safety hazardand safety hazard– A number are pyrophoric and AsHA number are pyrophoric and AsH33 and and

PHPH33 are highly toxic are highly toxic

Difficult to grow hyperabrupt layersDifficult to grow hyperabrupt layers– Residual gases in chamberResidual gases in chamber

Higher background impurity Higher background impurity concentrations in grown layersconcentrations in grown layers

Misfit DislocationsMisfit Dislocations

Occur when the difference between Occur when the difference between the lattice constant of the substrate the lattice constant of the substrate and the epitaxial layers is larger than and the epitaxial layers is larger than the critical thickness. the critical thickness.

http://www.iue.tuwien.ac.at/phd/smirnov/node68.html

Critical Thickness, tCritical Thickness, tCC

where where

b is the magnitude of the lattice distortion caused b is the magnitude of the lattice distortion caused by a dislocation (Burger vector)by a dislocation (Burger vector)

f is the mismatch between the lattice constants of f is the mismatch between the lattice constants of film and the substratefilm and the substrate

is Poisson’s ratio (transverse strain divided by the is Poisson’s ratio (transverse strain divided by the axial strain).axial strain).

Key InventionsKey Inventions

Three discoveries made integrated Three discoveries made integrated circuits possible:circuits possible:– Invention of the transistorInvention of the transistor

(1949 by Brattain, Bardeen, and (1949 by Brattain, Bardeen, and Schockley; Nobel prize 1972)Schockley; Nobel prize 1972)

– Development of planar transistor Development of planar transistor technologytechnology(1959 by Bob Noyce and Jean Hoerni; (1959 by Bob Noyce and Jean Hoerni; Noyce was a founder of Intel)Noyce was a founder of Intel)

– Invention of integrated circuitInvention of integrated circuit(1959 by Kilby; Nobel prize 2000)(1959 by Kilby; Nobel prize 2000)

The First TransistorThe First Transistor

The first transistor, a point The first transistor, a point contact pnp Ge device, was contact pnp Ge device, was invented in 1947 by John invented in 1947 by John Bardeen, Walter Brattain, Bardeen, Walter Brattain, and William Shockley. They and William Shockley. They received the Nobel Prize in received the Nobel Prize in physics in 1956.physics in 1956.

The first integrated circuitThe first integrated circuit

The first integrated circuit The first integrated circuit was invented by Jack Kilby was invented by Jack Kilby of TI. He received the of TI. He received the Nobel Prize in 2000.Nobel Prize in 2000.

Levels of Integrated CircuitsLevels of Integrated Circuits Small Scale Integration (SSI)Small Scale Integration (SSI)

1-10 transistors1-10 transistors Medium Scale Integration (MSI)Medium Scale Integration (MSI)

up to 100 transistorsup to 100 transistors Large Scale Integration (LSI)Large Scale Integration (LSI)

up to 10,000 transistorsup to 10,000 transistors Very Large Scale Integration (VLSI)Very Large Scale Integration (VLSI)

millions of transistorsmillions of transistors Ultra Large Scale IntegrationUltra Large Scale Integration Wafer Scale IntegrationWafer Scale Integration System on a Chip (SOC)System on a Chip (SOC) System in a Package (SiP)System in a Package (SiP) 3D IC3D IC

Increase in Complexity of Increase in Complexity of ChipsChips

Moore’s LawMoore’s Law

Gordon Moore observed (1965) that Gordon Moore observed (1965) that the number of transistors on a Si chip the number of transistors on a Si chip was doubling every year. Later, was doubling every year. Later, revised this to every 18 months.revised this to every 18 months.– This cannot continue forever; when This cannot continue forever; when

components reach size of atoms, the components reach size of atoms, the physics changes.physics changes.

– Currently, there is no known solution. Currently, there is no known solution.

Historical TrendsHistorical Trends of Minimum Feature Size of Minimum Feature Size

Minimum Minimum Feature Size: Feature Size: 13% reduction 13% reduction each year; each year; recently closer recently closer to 10%.to 10%.

Projections from 1997 Projections from 1997 RoadmapRoadmap

The fundamental assumption is that Si will be the The fundamental assumption is that Si will be the material of choice and that Moore’s law will apply until material of choice and that Moore’s law will apply until 20122012

Scaling as a Function of Cycle Scaling as a Function of Cycle TimeTime

1)(

7.0

2

12

TSTCARR

S

S is the minimum feature size

T is the cycle time

CARR is the Compound Annual Reduction Rate

On average, the minimum feature size On average, the minimum feature size decreases by decreases by 10-13%/10-13%/year. Currently at 45 or year. Currently at 45 or 32 nm node32 nm node

Where are we today?Where are we today?

Semiconductor TrendsSemiconductor Trends Overall chip size has been increasing by Overall chip size has been increasing by

16%/16%/year over past 35 yearsyear over past 35 years– Recently 6.3%/year for microprocessors and Recently 6.3%/year for microprocessors and

12%/year for DRAM12%/year for DRAM– Major limitation is the number of pads that can Major limitation is the number of pads that can

be placed on the chip to get signals in and outbe placed on the chip to get signals in and out Trends are now projected by the SIA Trends are now projected by the SIA

national Technology Roadmap for national Technology Roadmap for Semiconductors Semiconductors

Current version is called Current version is called International Technology Roadmap for Semiconductors

Cost of Designing a ChipCost of Designing a Chip

The cost of designing a chip has The cost of designing a chip has increased with the complexity of the increased with the complexity of the chip.chip.– Initially, the cost seemed to follows Initially, the cost seemed to follows

Moore’s law—the cost doubled every Moore’s law—the cost doubled every time the complexity doubled.time the complexity doubled.

– The controlling factor was the The controlling factor was the development of CAD and modeling development of CAD and modeling software.software.

CleanroomsCleanrooms

Federal Standard

TC 209 ISO

1

2

1 3

10 4

100 5

1,000 6

10,000 7

100,000 8

9

ISOFED STD 209

0.1 µm0.2 µm

0.3 µm

0.5 µm5.0 µm

CLASS 3 1 1000 / 35     35 / 1  

CLASS 4 10 10,000 / 345 75 30 352 / 10 0

CLASS 5 100 100,000 / 3,450 750 300 3520 / 100 0

CLASS 6 1,000 1,000,000 / 34,500 N/A N/A 35,200 / 1,000 7

CLASS 7 10,000 345,000 N/A N/A 352,000 / 10,000 70

CLASS 8 100,000 3,450,00 N/A N/A3,520,000 / 100,000

700

ISO 14644-1 (per cubic meter)Fed Std. 209 E USA (per cubic foot)ISO standard requires results to be shown in cubic meters (1 cubic meter = 35.314 cubic feet)

Room Classifications Class

Classification System            

ISO 14644-1 Class 3 Class 4 Class 5 Class 6 Class 7 Class 8

Federal Standard 209E 1 10 100 1,000 10,000 100,000

EU GGMP - - A/B - C D

Air Changes per hour 360-540 300-540 240-480 150-240 60-90 5-48

HEPA FiltersHEPA Filters

High Efficiency Particulate Air (HEPA) filters are 99.99% efficient in removing particles 0.3 micron and larger. HEPA filters utilize glass fiber rolled into a paper-like material. This material is pleated to increase the fiber surface area and bonded, or potted, into a frame. Hot melt is used to hold the pleats far enough apart to allow air to flow between them.

http://terrauniversal.com/products/cleanrooms/pharmclroom.php

Positive Pressurized RoomsPositive Pressurized Rooms

Air returns are built into the room – usually integrated into the chase.

Chases are the separate areas along side of the cleanroom that contain pumps, gas cylinders, and other needed (but dirty) materials and equipment.

First Line of Protection: Bunny First Line of Protection: Bunny SuitsSuits

www.intel.com

Similar bunny suit to what is worn up in the 6th floor Whittemore cleanroom and other Class 100-10,000 cleanrooms.

Missing elements are the face shield and safety eyeglasses.