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Page 1: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

©20

04 T

he M

athW

orks

, Inc

.

Model-Based Design of Embedded Signal Processing Systems Using Simulink®

Altera SOPC World 2004<Name of presenter here>

Page 2: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

2

Agenda

Model-Based Design of Embedded Systems– Challenges in DSP system design

Simulink and Blocksets– Quick Simulink demo– Video surveillance demo

Hardware Implementations– Implementation on DSPs and Altera FPGAs

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3

The MathWorks at a Glance

Headquarters:Natick, Massachusetts USA

USA: California, Michigan, Washington DC, Texas

Europe:UK, France, Germany, Switzerland, Italy, Spain, Benelux

Asia-Pacific:Korea

Worldwide training and consulting

Distributors in 25 countries

Earth’s topography on an equidistant cylindrical projection, created with the

MATLAB Mapping Toolbox

Page 4: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

4

Key Industries

Core– Aerospace and Defense– Automotive– Communications, Electronics,

Semiconductor, Computers and Office Equipment

– EducationEmerging

– Biotech, Pharmaceutical and Medical– Financial Services– Industrial Equipment and Machinery– Instrumentation

Ongoing– Chemical and Petroleum– Earth and Ocean Sciences– Utilities and Energy

Page 5: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

5

The MathWorks Product Family

Code Generation for Rapid Prototyping and Production Deployment

Desktop ApplicationsAutomated Reports

DAQ cardsInstrumentsDatabases

BlocksetsSignalToolboxesS

ignal

StateflowStateflowStateflow

Core Platform forSignal Processing System Design

Page 6: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

6

Challenges in Embedded System Design

Handle Increasing complexity

Design team integration

Reduce Time-to-Market

Page 7: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

7

Problems with Traditional Development

Requirements and Specifications

Design Implementation Test and Verification

Text-based- Prevents

rapid iteration

Physical prototypes- Incomplete and

expensive

Manual coding - introduces human

error

Traditional testing- errors found

too late in the process

Page 8: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

8

Advantages of Model-Based DesignRequirements and Specifications

Design Implementation Test and Verification

Model elaborationContinuous verification

Executable models-una-onl

mbiguousy “one truth”

Automatic code generation-minimizes coding errors

Test with Design - detects errors earlier

Simulation-reduces “real” prototypes-systematic “what-if”analysis

Page 9: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

9

Model-Based Design with Simulink

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10

Model-Based Design Allows You to Overcome Design Challenges:

Handle Design Complexity– Reuse IP, Simulate at high speeds, collaborate with multiple

design teams, utilize system-level design abstraction

Design team integration– Analog/Mixed-Signal, digital hardware, DSP S/W, control S/W

designed in one model– Co-design and partition HW and SW components

Reduce Time-to-Market– Generate code automatically for HW and SW– Accelerate verification using executable specification

Page 11: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

11

User stories: RealTek

Page 12: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

12

Simulink Tutorial: Model ConstructionDrag and dropConnect

Digital– Fast frame-based

simulationAnalog– Variable-step

numerical integration solvers

– Zero-crossing detection

Page 13: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

13

Signal Processing BlocksetStreaming dataMulti-rate systemsTransforms, filters, estimatorsEnables frames in SimulinkFixed- and Floating-Point Support

Example 1 - Envelope Detection>> dspwwvlib.mdl>>dspwwv

Page 14: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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Example 2 - Video Surveillance Systems using the Video and Image Processing Blockset

Fixed-point video surveillance system based on Sum of Absolute Differences motion detection

Page 15: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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Example 2: Video Surveillance System

Total # of Recorded Frames

Source FramesHigh rate: 30 fps

Recorded FramesAperiodic rate

(<< 30 fps)

>> vipsurveillance_win32

Page 16: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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Estimate motion

Compare Threshold

Record frames& update count

Motion Estimation:Sum of Absolute Differences

Page 17: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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Example 2: Video Surveillance System

Total # of Recorded Frames

Source FramesHigh rate: 30 fps

Recorded FramesAperiodic rate

(<< 30 fps)

>> vipsurveillance_win32

Page 18: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

18

Estimate motion

Compare Threshold

Record frames& update count

Motion Estimation:Sum of Absolute Differences

Page 19: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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Motion Detection with Thresholding

Motion levels

Video Motion Estimate

Detection Threshold

Captured Video Frames

Page 20: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

©20

04 T

he M

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, Inc

.EmbeddingSignal Processing Applications

on DSPs and FPGAs

Page 21: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

21

Production Code Generation

Based on Real-Time Workshop code generation engineGenerated code is ANSI C – efficient, readable, editableSupports and utilizes Real-Time Workshop Embedded Coder

Proven automatic code generation technology for critical applications

Page 22: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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Production Code GenerationSuccessful in Automotive and Aerospace industries

“Visteon Powertrain has demonstrated that model-based software development can generate quality software in less time, and the automatic code ROM & RAM sizes are equal to or better than hand written code.*”

* Multi-Target Modeling for Embedded Software Development for Automotive ApplicationsGrantley Hodge, Jian Ye and Walt Stuart, Visteon Corporation2004 SAE World Congress, Detroit, MI. March 8-11, 2004

Page 23: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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Embedded Target for TI C6000 DSP is…… 1. a tool for production code generation

– Processor-specific, optimized– Simulink blocks and optimized libraries (FIR, FFT, …)

…2. a means for project automation– Processor-specific, automatic– APIs for CCS IDE, Compiler/Linker

… 3. a platform for rapid prototyping– Target-specific, integrated– Simulink hardware blocks and device drivers

(ADC, DAC, RTDX, daughter cards)

Page 24: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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1. Production Code Generationa) How good is the generated code for TI C6000?

Code generation philosophy for C6000 DSPs:

– Generates efficient, portable, readable, editable code

– Supports code profiler to help identify code performance bottlenecks

• code segments that provide highest return on optimization

Page 25: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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1. Production Code Generationb) How can I further optimize the code?

Provides alternate methods for code optimization– Manual optimization by user

Click on link in profile report to jump to relevant code section

– Target-specific blocks

– Engineering services

Page 26: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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1. Production Code GenerationTarget-Specific Blocks

C-callable assembler libraries– Simulate bit-true in Simulink– Generate calls to hand-

optimized assembler libraries– Highly optimized implementation

of core functionality– C62x and C64x fixed-point

DSPs

Page 27: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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1. Production Code Generation

Recap of code generation withEmbedded Target for TI C6000

– Quickly create a complete, working code base

– Utilize code profiler to help identify any performance bottlenecks in generated code

– Choose from several approaches for code optimization

…optimize only when and where necessary…

Page 28: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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2. Project Automation

Create and populate CCS project

Automate compile/link/download

Page 29: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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2. Project Automation

Breakpoints

Watch Window

Utilize CCS to:

– debug, test, and verify code

– add and customize code

Page 30: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

30

3. Rapid Prototyping – Scenarios

Use Supported DSK/EVM# Use Custom Board + Emulator

Use TI DSP Simulator

1. PC + DSK/EVM2. Emulator Optional3. Connect through USB,

Parallel, PCI, or JTAG ports

1. PC + Custom Board + Emulator

2. Connect through JTAG port

1. PC2. Simulator: Very Slow

1. Generate code2. H-I-L prototyping*

3. RTDX4. Access hw devices –

ADC, DAC, daughter cards, etc.

1. Generate code2. H-I-L prototyping*

3. RTDX

1. Generate code2. S-I-L prototyping*

• Test and verify in CCS• Test and verify using

MATLAB andLink for CCS

• Test and verify in CCS• Test and verify using

MATLAB andLink for CCS

• Test and verify in CCS• Test and verify using

MATLAB andLink for CCS

# Supports 6701 EVM, 6711, 6713, and 6416 DSKs. In v.2.1, DM642 EVM will also be supported.

* From MATLAB

Page 31: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

31

Steps to Target the TI C6416 DSK

RTDX blocks

DIP Switch

>> c6416dsksurveil_hsrtdx

Page 32: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

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Steps to Target the TI C6416 DSK – 2Select target options (DSP/BIOS, compiler settings, etc)

High/Speed RTDX

Incorporate DSP-BIOS

Inline Signal ProcessingBlockset functions

Page 33: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

33

Steps to Target the TI C6416 DSK – 3

Build process

– Auto-generate ANSI C and ASM code

– Integration of RTOS and scheduler

– Create full CCS project in IDE Invoke compiler, linker, and download code

– Run target

Page 34: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

34

Target the TI C6416 DSK – 4

Automatic profilingof program executingon DSPSystem profilingIncludes entire DSP application code

Subsystem profiling

>> cc=ccsdsp;>> profile(cc,’report’)

Page 35: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

35

Design Verification:Real-time Visualization

Host-side visualization using Link for Code Composer Studio

Log and plot estimatesover time (scrolling data)

Input video frames

Captured frames >> c6416dsksurveil_hsrtdx

Page 36: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

©20

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, Inc

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EmbeddingSignal Processing Systems in Altera

FPGAs Using the DSP Builder

Page 37: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

37

Altera DSP Builder

Page 38: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

38

CreatesHDL Code

DSP BuilderDownloadDesign to

DevelopmentBoard

CreatesSimulation Test Bench

Verifyin

Hardware

CreatesProcess

orPlug-In

HDLSynthesis

Page 39: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

39

Dedicated Hardware Architecture

Stand-Alone Processor

Processor + Co-Processor

Custom Co-Processor DevelopmentCustom Co-Processor DevelopmentDSP BuilderDSP BuilderSOPC BuilderSOPC Builder

Page 40: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

40

DSP Builder Library Components

ArithmeticBus ManipulationComplex Signals Logical ComponentsSOPC PortsStorageMegaCore® IPRate ChangeState MachineAltera LibraryDSP Board

Page 41: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

©20

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.Other MathWorks Products for HDL Code Generation and Verification

Page 42: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

42

Filter Design HDL Coder for Digital Filters

Description– Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog– Verify implementation through

co-simulation

What you will see– Fixed-point filter design– Automatic HDL generation with

Filter Design HDL Coder– Verify implementation with

Link for ModelSim

Page 43: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

43

Link for ModelSim

Generate SynthesizableVHDL or Verilog code

Fixed-point support across MATLAB and Simulink

Design Fixed-Point Filters

Co-simulate with ModelSim

Page 44: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

44

Simulink and Model-Based Design Produce Results Across Industries

Standard for Powertrain Controls Production Code Development

JSF Flight Control System

W-CDMA Baseband Processors

Specialty Chipsets for DSP Customers

Page 45: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

45

MATLAB Centralwww.matlabcentral.comOver 1,500 MathWorks- and user-contributed filesMATLAB files and Simulink models for download

Page 46: Model-Based Design of Embedded Signal Processing Systems ... · Filters Description – Design IIR fixed-point filter – Generate synthesizable VHDL or Verilog – Verify implementation

46

SummarySimulink brings:– Model-Based Design to large-scale projects– More comprehensive coverage of

embedded system development – New domains and applications

Visit the web for morewww.mathworks.com/r14

Visit us at the booth to see more product demonstrations


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