modeling mos transistors - electrical and computer …€¦ · · 2013-02-05– bsim is latest...
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Modeling MOS Transistors
Prof. MacDonald
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Modeling MOSFETs for simulation
l Software is used simulate circuits for validation l Original program – SPICE – UC Berkeley
– Simulation Program with Integrated Circuit Emphasis l Other programs:
– IBM’s internal ASX – developers work closely with Berkeley – Synopsys’ HSPICE (most commonly used?) – Cadence Spectre – Cadence PSPICE – used for PCB simulation (not really ICs) – Agilent’s ADS and Ansofts Nexxim (for RF simulation) – NGSPICE – at sourceforge.com for free – SPICE OPUS
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MOSFET models
l Simulation models are – used in circuit simulators to simulate transistor behavior – created by device engineers – and used by circuit designers to validate larger designs
l Transistor models – take as input
l voltages at four terminals (drain, source, gate, body) l environmental conditions (temperature, noise)
– generate as output currents and capacitances l Several levels of models:
– Level 1 is based on GCA analysis in previous chapter – BSIM is latest and accounts for deep sub-micron effects
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MOSFET models – Level 1
l Based on Gradual Channel Approximation l Good for long channel devices l low accuracy and slow l Ignores deep sub-micron effects l Ignores sub-threshold current (Ioff) l Includes device parameters – physical and electrical:
– VTO – no body bias threshold voltage – KP – transconductance – LAMBDA – channel modulation coefficient – PHI – surface inversion potential – GAMMA – body effect coefficient – and much more (30 or so more) 4
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MOSFET models – level 1 device model
l Based on Gradual Channel Approximation l Not accurate or fast
Cgd
Cgs
Cgb
Csb
Cdb
gate
drain
source
bulk + Vgs -
+ Vds -
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Correlating Model to cross section
Gate
Silicon Substrate
Source Field Oxide
Drain Field Oxide N+ N+
P
Field Oxide
P+
b s g
d
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gate to body oxide capacitances
Cgd
Cgs
Cgb
Csb
Cdb
gate
drain
source
bulk + Vgs -
+ Vds -
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Capacitance between gate and substrate
Gate
Silicon Substrate
Source Field Oxide
Drain Field Oxide N+ N+
P
Cgb
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source / drain oxide capacitances
l Based on Gradual Channel Approximation l Not accurate or fast
Cgd
Cgs
Cgb
Csb
Cdb
gate
drain
source
bulk + Vgs -
+ Vds -
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Oxide Capacitance – Source Drain Overlap
Gate
Silicon Substrate
Source Field Oxide
Drain Field Oxide N+ N+
P
Oxide capacitance is always present between gate and both source and drain although this cap tends to be small.
ox
oxdgs
tLWC ε••
=
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Oxide Capacitance – Linear Mode
Gate
Silicon Substrate
Source Field Oxide
Drain Field Oxide N+ N+
P
Oxide capacitance is split between Cgs and Cgd in linear mode. Substrate is shielded by inversion layer. Also includes small overlap capacitance.
ovox
oxdsgs C
tLWCC +••
•= =ε
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Oxide Capacitance – Saturation Mode
Silicon Substrate
Source Field Oxide
Drain Field Oxide N+ N+
P
Oxide capacitance is to incomplete inversion layer which provides a connection to the source only. Gate to drain cap is limited to overlap only.
ovox
oxgs C
tLWC +••
•=ε
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MOSFET models - junction capacitance
Cgd
Cgs
Cgb
Csb
Cdb
gate
drain
source
bulk + Vgs -
+ Vds -
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Oxide Capacitance – Saturation Mode
Silicon Substrate
Source Field Oxide
Drain Field Oxide N+ N+
P
Junction capacitance increases with increases in doping and decreases with increases in reverse bias voltage. SOI virtually eliminates this capacitance.
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MOSFET models – series resistance
Cgd
Cgs
Cgb
Csb
Cdb
gate
drain
source
bulk + Vgs -
+ Vds -
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Oxide Capacitance – source/drain resistance
Silicon Substrate
Source Field Oxide
Drain Field Oxide N+ N+
P
As source / drain junction depth (Xj) decreases with each new technology generation, source drain series resistance is growing.
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Simple SPICE program *Spice Input File (deck)for an inverter VIN in gnd PULSE(0 1.0 2ns 2ns 2ns 50ns 100ns) * d g s b model mp out in vdd vdd PMOS L=0.18u W=0.8u mn out in gnd gnd NMOS L=0.18u W=0.4u .tran 0.1ns 20ns 0n 100p .print TRAN V(out) V(in) .model P1 PMOS Level=1 +VT0=0.35 KP=2.0e-5 GAMMA=0.37 PHI=0.65 LAMBDA=0.02 +RD=1.0 RS=1.0 .model N1 NMOS Level=1 +VT)=0.35 KP=4.0e-5 GAMMA=0.37 PHI=0.65 LAMBDA=0.02 +RD=1.0 RS=1.0 .end 17
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Simple SPICE program *Spice Input File (deck)for a NAND gate VIN in gnd PULSE(0 1.0 2ns 2ns 2ns 50ns 100ns) * d g s b model mpa out a vdd vdd PMOS L=0.18u W=0.8u mpa out b vdd vdd PMOS L=0.18u W=0.8u mna out a int gnd NMOS L=0.18u W=0.8u mna int b gnd gnd NMOS L=0.18u W=0.8u .tran 0.1ns 20ns 0n 100p .print TRAN V(out) V(a) V(b) .include NMOS_MODEL .include PMOS_MODEL .end
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MOSFET models – BSIM3
l Models generated by UC Berkeley l Depends on empirical fitting l includes Short Channel Effects (SCE)
– Vt rolloff – Vts are influenced by Leffs at short channel length – mobilities – sub-threshold leakage
l Capacitance models the same but more accurate l Source / Drain resistance l Designed with computational speed in mind l Used universally now
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UFSOI models
l Models generated by University of Florida l Incorporated into Berkeley Spice 3E5 l Models describe physical features of transistor l Best models for SOI but can model bulk too. l Used in this class l Compiled for Sun machine, but we have source
which could be ported to Linux or PC (extra credit?)
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Specifying Source/Drain areas/perimeters
n-well
5u
mp 0 1 2 2 PMOS L=0.18u W=5u AS=35p PS=24u AD=35p PD=24u By specifying area and perimeters of the source and drain, the caps can be calculated for the area and sidewalls.
7u 7u
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Spice in interactive mode
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Spice in batch mode
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Spice Example
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