modeling of device aging - example: diode · 2018-03-22 · the simple solution would be to add a...

Modeling of Device Aging - Example: Diode

Franz Sischka*, Bertrand Ardouin**

* SisConsult, Stuttgart** XMOD Technologies, Bordeaux

[email protected]@xmodtech.com

... a step-by-step tutorial ...

-1-

Franz Sischka*, Bertrand Ardouin**

* SisConsult, Stuttgart** XMOD Technologies, Bordeaux

[email protected]@xmodtech.com

Further Co-Authors:Thomas Gneiting & Heidrun Alius, AdMOS, FrickenhausenK-W. Pieper, Infineon, Munich

AcknowledgementsMeasurement Data: Falk Korndörfer & Gerhard Fischer, IHP, Frankfurt (Oder)Verilog-A Code Inspection: Geoffrey Coram, Analog Devices, USA

Agenda

Motivation

How to Implement Aging in a CAD Environment

Schottky Diode Aging Measurement Data

Developing a Verilog-A Model for Diode Aging

Using the Aging Model

Conclusions

Motivation





Conclusions

-2-

Motivation for this Presentation

Presentations and Discussionsat the Bipolar-AK Meetingin Erfurt, Nov.2017

Hicum 2 Custom Aging Model

see:https://www.iee.et.tu-dresden.de/iee/eb/forsch/AK-Bipo/ak_bipo_bei.html#2017

-3-

Combine the Basic Ideasof these 3 Papers in a Single,Simple Demo:the Aging of a Single Diode.

InP HBT Gummel-Poon Characteristic:monitored during stress

IC:increase below ohmic rangedecrease in ohmic range

IB:important increase

Motivation for this Presentation (cont'd)

VBE[V]

Detail of XMOD's Presentation:

-4-

InP HBT Gummel-Poon Characteristic:monitored during stress

IC:increase below ohmic rangedecrease in ohmic range

IB:important increase

Resulting Current Gain Degradation vs. Stress Time

VBE[V]

Motivation for this Presentation (cont'd)

XMOD's presentation featured an Hicum HBT aging modeling,

which can easily be adapted also to diode aging.

-5-

Why Diode Aging Modeling: simple model equations allows focus on aging, avoiding confusion by complex model equations results can be applied to all kinds of models which include diodes

(bipolar, HBT, MOS, HEMT ...)

XMOD's presentation featured an Hicum HBT aging modeling,

which can easily be adapted also to diode aging.

Outlook of this Presentation:Enhancing Diode Parameter IS for Aging Modeling

1vtNavexpai IS

time,voltage,TEMPdttdIS AIS

Diode Current:

-6-

BIS, EIS, ALPHA and BETA are aging model parameters for IS

time/voltagevt

exptime,voltage,TEMP

AIS BIS -EIS ALPHA BETA

age

dt

0IS_aged = IS + ΔIS_aging = IS + AIS

Agenda

Motivation





Conclusions

-7-

Motivation





Conclusions

How to Implement Aging in a CAD Environment ?

The simple solution would be to add a new parameter 'Age' in Cadence CDFe.g. a new Pcell Variable, like W and L

Not possible,because the 'Age' or Degradationof a device depends on: Temperature Voltage (DC bias & dynamic) Time

Each device instancesuffers from a differentstress/degradation,which is also dependent on theaging of the neighboring devices.

The effect of aging has to be simulated circuit specific !

-8-

Not possible,because the 'Age' or Degradationof a device depends on: Temperature Voltage (DC bias & dynamic) Time

Each device instancesuffers from a differentstress/degradation,which is also dependent on theaging of the neighboring devices.

The effect of aging has to be simulated circuit specific !

Age 10 years

We are talking about Dynamic Aging

i.e. we need an aging model which works for both,

static aging (DC bias only)

aging due to large signal excitation (DC & nonlinear RF)

i.e. we need an aging model which works for both,

static aging (DC bias only)

aging due to large signal excitation (DC & nonlinear RF)

-9-

Why a Dynamic Aging Model ?

Aging is a dynamic phenomenon !

It does not simply depend on 'Quiescent' Bias Point,

but rather on the integration of stress impacts over time.

[Volt]

-10-

[Volt]

Dynamic Aging ExampleStress conditions can evolve over circuit life cycle with positive or negative feedback effect i.e. saturation of degradation, or exponential growth of degradation.

This can’t be accounted for by “static models”.

In the Example Circuit on the rightM1 is stressed, its VTH drifts during circuit life cycle: Ibias changes IDSM3 / M4 change VDSM3 / M4 change

The aging rates of each, M3 and M4,are impacted by the aging of M1. there is an aging feedback loop within the circuit !!

IDSM4IbiasM3

Stress conditions can evolve over circuit life cycle with positive or negative feedback effect i.e. saturation of degradation, or exponential growth of degradation.

This can’t be accounted for by “static models”.

In the Example Circuit on the rightM1 is stressed, its VTH drifts during circuit life cycle: Ibias changes IDSM3 / M4 change VDSM3 / M4 change

The aging rates of each, M3 and M4,are impacted by the aging of M1. there is an aging feedback loop within the circuit !!

M1

M4

IbiasM3

M2

Dynamic Aging allows observing degradation effects “LIVE”.

-11-

Agenda

Motivation





Conclusions

-12-

Motivation





Conclusions

Available Measurement Data:Sweeps of ia = f(va), on different chips, measured at t=0,and after stress intervals with different stress bias, stress time

Developing a Model for Schottky Diode Aging

stress

stressstress

-13-

AGING MODELING STEP 1:

DATA NORMALIZATIONFIRST AN OVERVIEW:

from the individual stress measurements of different devices,

the ia(va) traces at stress time 0 have been inspected,

and a 'golden chip' has been identified.

the measurements of the other chips have been normalized

to this 'golden chip',

resulting in consistent aging measurement data,

to be applied for this aging demo.

DATA NORMALIZATIONFIRST AN OVERVIEW:

from the individual stress measurements of different devices,

the ia(va) traces at stress time 0 have been inspected,

and a 'golden chip' has been identified.

the measurements of the other chips have been normalized

to this 'golden chip',

resulting in consistent aging measurement data,

to be applied for this aging demo.

-14-

Step 1:the ia(va) measurements of the non-golden-chip devices (chips 3.4, 5.4, 6.4),before stress, at t=0,have been normalized, point-per-point, to the t=0 measurement of the golden-chip (3.11),resulting in identical t=0 curves for all devices.

MEASUREMENT DATA CLEAN-UP IN DETAILS

ia(va) before stress (t=0)

chip3.1103.4005.400

1E-3

1E-2

ianorm(va) before stress (t=0)

chip3.1103.4005.400

1E-3

1E-2

ia(va) measurements before stress (t=0) ia_norm(va) before stress (t=0)

va [E+0]

ia.M

[LO

G]

5.4006.400

-3 -2 -1 0 11E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

va [E+0]

ia_n

orm

.M[L

OG

]

5.4006.400

-3 -2 -1 0 11E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

-15-

before normalization after normalization

Step 2:These per-chip normalization factors have then been appliedto the stress measurements of each non-golden-chip, and again point-per-point (see also next slide).

DATA CLEAN-UP IN DETAILS

ia(va) stress measurements ia_norm(va) normalized stress meas.

before normalization after normalization

ia.M

[LO

G]

ia_n

orm

.M[L

OG

]

-16-

... and zoomed-in at va = -2.5Via

.M[L

OG

]

ia_n

orm

.M[L

OG

]

ia(va) stress measurements ia_norm(va) normalized stress meas.

after normalization

ia.M

ia_n

orm

.Mdue to normalization,all stress measurements now sharethe same starting points for t=0

-17-

before normalization

3 Model Parameterscan fit the stress effectsDMAIN: RSDMAIN: ISDREV: IS

AGING MODELING STEP 2:Develop a Spice Model for t=0,which can alsofit all stress conditionsby just varying its parameter values

DMAIN

ia_n

orm

.M[L

OG

]

DMAIN: IS↓

DMAIN: RS↑

DREV: IS↓

DREV_RECOMB

stress ↑

stress ↑

stress ↑t=0

t=0

IC-CAP Icon: _1_SchottkyDiode_Mdlg

DREV_RECOMB

DREV

A C

-18-

AGING MODELING STEP 3:Parameters of individual modelingof each stress measurement,vs. StressTime & StressBias

NOTE:This is the last pre-inspection of the meas.data,before starting the very aging modeling.

It represents the aging of the 3 model parameters,which are affected by the aging,as identified in the slide before.

DREV_IS_vs_stresstime

DR

EV

_IS

_scl

d.M

[E-1

2]

chip3.1103.6005.4006.400

100

150

200

DMAIN_IS_vs_stresstime

DM

AIN

_IS

_scl

d.M

[E-1

2]

560

580

600

DMAIN_RS_vs_stresstime

DM

AIN

_RS

_scl

d.M

[E+0

]

180

200

220

-4.0-3.5-3.0-2.5

stress bias

DMAIN_RSDREV_IS Parameter IS affected by stress

680

700

720

740

DMAIN_IS

stresstime_scld [LOG]

DR

EV

_IS

_scl

d.M

1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 1E+40

50


DM

AIN

_IS

_scl

d.M

1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4500

520

540


DM

AIN

_RS

_scl

d.M

1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4140

160

stresstime [LOG] stresstime [LOG]1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4600

620

640

660

stresstime [LOG]

-19-

Parameter IS affected by stressvi

su_I

S.M

[E-1

2]

660

680

700

720

740

DMAIN_IS affected by stress

visu

_IS

.M[E

-12]

stress bias

DMAIN_IS affected by stress

To keep the Aging Modeling Example simple for this presentation,we will only discuss the aging shift of parameter DMAIN_IS

stresstime_swp [E+3]

visu

_IS

.M

0 1 2 3 4 5600

620

640

stresstime [LIN]

linear time axis

visu

_IS

.M

stresstime [LOG]

log time axis

... the aging modeling for RS and DREV_ISof the total Schottky Diode Spice Deckcan be done in the same way ...

-20-

Only the aging shift of parameter DMAIN_IS @ va=0.2V is considered further

ia_norm_vs_va__X_LOGY_Plot

[LO

G]

1E-6

1E-5

1E-4

1E-3

1E-2

ia_norm of all stress conditions vs. va

ia_n

orm

.M[L

OG

]

-3 -2 -1 0 11E-12

1E-11

1E-10

1E-9

1E-8

1E-7

stressbias

DMAIN_IS

stresstime

va=0.2V

va [E+0]

-21-

Consequently,

from now on, in this Tutorial,

we will only consider

the Aging of a Single Spice Diode Model

DMAINA C

-22-

applied stress bias:va = -2.5V, -3V, -3.5V, -4V

applied stress times:0 sec ... 4000 sec (no fixed grid)

followed by aia(va) DC meas. sweep [E

-9]

stre

ss ti

me stre

ss ti

me

stre

ss ti

me

stre

ss ti

me

ia_norm(va=0.2V) = f(stressbias, stresstime)

Stress Measurement Details for va=0.2V(to be modeled) applied stress bias:

va = -2.5V, -3V, -3.5V, -4V

applied stress times:0 sec ... 4000 sec (no fixed grid)

followed by aia(va) DC meas. sweep

ia_n

orm

.M[E

-9]

stress bias [E+0]

stre

ss ti

me

-23-

Agenda

Motivation





Conclusions

Motivation





Conclusions

-24-

AGING MODELING STEP 4:Simplified Verilog-A DC-only Diode Model

this shall be enhanced for the aging modeling of parameter 'IS'

`include "disciplines.vams"

module diode_va(anode,cathode);

electrical anode,cathode;

branch (anode,cathode) br_AnodeCathode; // branch def. (mnemotic shorthand)

parameter real is=1e-14 from [1e-30:inf);parameter real n=1 from [0:10];

real vd, id;

analog begin

vd = V(br_AnodeCathode); // set variable vd: diode voltage

// ==== calc. dc diode current ====id = is * (limexp( vd / (n * $vt)) - 1);

// ==== return DC current ==========I(br_AnodeCathode) <+ id;

end

aging detail

measurementsimulationt=0

`include "disciplines.vams"

module diode_va(anode,cathode);

electrical anode,cathode;

branch (anode,cathode) br_AnodeCathode; // branch def. (mnemotic shorthand)

parameter real is=1e-14 from [1e-30:inf);parameter real n=1 from [0:10];

real vd, id;

analog begin

vd = V(br_AnodeCathode); // set variable vd: diode voltage

// ==== calc. dc diode current ====id = is * (limexp( vd / (n * $vt)) - 1);

// ==== return DC current ==========I(br_AnodeCathode) <+ id;

end

IC-CAP Icon: _2_diode_DC_VA

DMAIN

A C

-25-

AGING MODELING STEP 5:Modeling the Aging of Parameter 'IS', due to stress bias and time

[E-9

]

[E-1

2]

Current ia(va=0.2V), affected by stress Parameter IS, affected by stress

IC-CAP Icon: _3_diode_aging_mdlg

ia_n

orm

.M[E

-9]

visu

_IS

.M[E

-12]

-26-

Aging Model Equation for Parameter 'IS'

ΔIS_aging is the integral over aging effects,obtained by a transient simulation

timevoltagevt

exptime,voltage,TEMP

AIS BIS -EIS ALPHA BETA

IS_delta_aged = IS + ΔIS_aging = IS + AIS∫age

t=0dt

Aging IS

Aging Parameters

BIS over all proportionality

EIS aging dependency on stress temperature

ALPHA aging dependency on stress bias

BETA aging dependency with time

-27-

Simulating Aging with Dynamic Aging ModelsExplanation of the additional Parameter

ATSF: Accelerating Time Scale Factor

age

0IS_delta_aged = IS + ΔIS_aging = IS + ATSF * AIS dt

/ ATSF

The introduction of ATSF for a dynamic aging model is a matter of scale:If you wish to simulate 10 years of circuit life, for eg. a circuit working at 1 GHz, that's 3.15E17 periods.

Simulating just 2 points per period, requiring ~2ms of CPU time per transient step (e.g. a medium scale circuit),

that is million years of CPU time ... a bit long ... most of us will be retired by then (hopefully).

In practice: ATSF=1E12: 1ps aging transient simul. time = 1 sec. aging in real world.

ATSF = 3.6E15: 1ps simul.time = 1h real.time aging

Benefit:

Changing ATSF permits accelerated transient aging simulations

w/o modifying the other aging parameter values.

The introduction of ATSF for a dynamic aging model is a matter of scale:If you wish to simulate 10 years of circuit life, for eg. a circuit working at 1 GHz, that's 3.15E17 periods.

Simulating just 2 points per period, requiring ~2ms of CPU time per transient step (e.g. a medium scale circuit),

that is million years of CPU time ... a bit long ... most of us will be retired by then (hopefully).

In practice: ATSF=1E12: 1ps aging transient simul. time = 1 sec. aging in real world.

ATSF = 3.6E15: 1ps simul.time = 1h real.time aging

Benefit:

Changing ATSF permits accelerated transient aging simulations

w/o modifying the other aging parameter values.

-28-

Implementation of IS Aging Model into Verilog-A File→ Overview:

module diode_va(anode,cathode) ;electrical anode,cathode ;

branch (anode,cathode) br_AnodeCathode;

parameter real is = 1e-14 from [1e-30:1];parameter real n = 1 from [0.5:50];

//--------------------------------------------------------real vd, id ;

analog beginvd = V(br_AnodeCathode);

id = is * (limexp( vd / (n * $vt)) - 1);//

I(br_AnodeCathode) <+ id;

endendmodule

our Verilog-A file so far: enhanced for IS aging:module diode_va(anode,cathode,is_delta);electrical anode,cathode,is_delta;

branch (anode,cathode) br_AnodeCathode;branch (is_delta) br_isdelta;

parameter real is = 1e-14 from [1e-30:1];parameter real n = 1 from [0.5:50];parameter real bis = 1 from (-inf:inf);parameter real eis = 1.2 from (-inf:inf);parameter real alpha = 2 from (-inf:inf);parameter real beta =0.5 from (-inf:inf);parameter real atsf = 1e12 from (-inf:inf);

//--------------------------------------------------------real vd, id, ais, is_eff;


// ======================================================agingtime = $abstime*atsf;ais = atsf * bis * exp(-eis / $vt) * pow(abs(vd),alpha) / pow(agingtime,beta);

if (analysis("tran")) beginif (analysis("ic")) begin

V(br_isdelta) <+ 0.0;end else begin

I(br_isdelta) <+ ais;I(br_isdelta) <+ ddt(V(br_isdelta));

endend else begin

V(br_isdelta) <+ 0.0;end

// ======================================================is_eff = IS + V(br_isdelta);id = is_eff * (limexp( vd / (n * $vt)) - 1);

//I(br_AnodeCathode) <+ id;

endendmodule

module diode_va(anode,cathode) ;electrical anode,cathode ;

branch (anode,cathode) br_AnodeCathode;

parameter real is = 1e-14 from [1e-30:1];parameter real n = 1 from [0.5:50];

//--------------------------------------------------------real vd, id ;


id = is * (limexp( vd / (n * $vt)) - 1);//

I(br_AnodeCathode) <+ id;

endendmodule

Notes: for simplicity, temperature modeling is skipped above, and in the following slides, but will be covered later. also, a switch parameter CODEG for on/off switching of the aging part is omitted for the moment, but is explained later.The complete, full Verilog-A Code is available as an attachment to the handout.

module diode_va(anode,cathode,is_delta);electrical anode,cathode,is_delta;

branch (anode,cathode) br_AnodeCathode;branch (is_delta) br_isdelta;

parameter real is = 1e-14 from [1e-30:1];parameter real n = 1 from [0.5:50];parameter real bis = 1 from (-inf:inf);parameter real eis = 1.2 from (-inf:inf);parameter real alpha = 2 from (-inf:inf);parameter real beta =0.5 from (-inf:inf);parameter real atsf = 1e12 from (-inf:inf);

//--------------------------------------------------------real vd, id, ais, is_eff;


// ======================================================agingtime = $abstime*atsf;ais = atsf * bis * exp(-eis / $vt) * pow(abs(vd),alpha) / pow(agingtime,beta);

if (analysis("tran")) beginif (analysis("ic")) begin

V(br_isdelta) <+ 0.0;end else begin

I(br_isdelta) <+ ais;I(br_isdelta) <+ ddt(V(br_isdelta));

endend else begin

V(br_isdelta) <+ 0.0;end

// ======================================================is_eff = IS + V(br_isdelta);id = is_eff * (limexp( vd / (n * $vt)) - 1);

//I(br_AnodeCathode) <+ id;

endendmodule

-29-

module diode_va(anode,cathode);electrical anode,cathode; // electrical nodes definition

branch (anode,cathode) br_AnodeCathode; // branches def. (mnemotic shorthands)

parameter real is = 1e-14 from [1e-30:1]; // DC paramsparameter real n = 1 from [0.5:50];

//--------------------------------------------------------real vd, id; // variables used in modeling section below

analog beginvd = V(br_AnodeCathode); // set variable vd: diode voltage

id = is * (limexp( vd / (n * $vt)) - 1);

I(br_AnodeCathode) <+ id; // contribute DC current into branch br_AnodeCathode

endendmodule

module diode_va(anode,cathode);electrical anode,cathode; // electrical nodes definition

branch (anode,cathode) br_AnodeCathode; // branches def. (mnemotic shorthands)

parameter real is = 1e-14 from [1e-30:1]; // DC paramsparameter real n = 1 from [0.5:50];

//--------------------------------------------------------real vd, id; // variables used in modeling section below

analog beginvd = V(br_AnodeCathode); // set variable vd: diode voltage

id = is * (limexp( vd / (n * $vt)) - 1);


endendmodule

-30-

module diode_va(anode,cathode,is_delta);electrical anode,cathode,is_delta; // electrical nodes definition

branch (anode,cathode) br_AnodeCathode; // branches def. (mnemotic shorthands)branch (is_delta) br_isdelta;

parameter real is = 1e-14 from [1e-30:1]; // DC parametersparameter real n = 1 from [0.5:50];parameter real bis = 1 from (-inf:inf); // - proportionalityparameter real eis = 1.2 from (-inf:inf); // - temp. dependencyparameter real alpha = 2 from (-inf:inf); // - stress bias dependencyparameter real beta = 0.5 from (-inf:inf); // - aging dependency with timeparameter real atsf = 1e12 from (-inf:inf); // - accelerating time scale factor, a fixed value

// e.g. 1e12: 1ps simul.time = 1s real time aging//--------------------------------------------------------real vd, id, ais, is_eff; // variables used in modeling section below

analog beginvd = V(br_AnodeCathode); // set variable vd: diode voltage//====================================================== calculate delta_is, diode aging: f(temp(=$vt), vd)agingtime = $abstime*atsf;ais = atsf * bis * exp(-eis / $vt) * pow(abs(vd),alpha) / pow(agingtime,beta);if (analysis("tran")) begin

if (analysis("ic")) begin // case: transient simulation, initial conditionV(br_isdelta) <+ 0.0; // short the branch br_isdelta

end else beginI(br_isdelta) <+ ais;I(br_isdelta) <+ ddt(V(br_isdelta));

endend else begin

V(br_isdelta) <+ 0.0; // short the branch br_isdeltaend//====================================================== calculate: is_eff = is + is_delta_agingis_eff = is + V(br_isdelta);id = is_eff * (limexp(vd / (n * $vt)) - 1);


endendmodule

module diode_va(anode,cathode,is_delta);electrical anode,cathode,is_delta; // electrical nodes definition

branch (anode,cathode) br_AnodeCathode; // branches def. (mnemotic shorthands)branch (is_delta) br_isdelta;

parameter real is = 1e-14 from [1e-30:1]; // DC parametersparameter real n = 1 from [0.5:50];parameter real bis = 1 from (-inf:inf); // - proportionalityparameter real eis = 1.2 from (-inf:inf); // - temp. dependencyparameter real alpha = 2 from (-inf:inf); // - stress bias dependencyparameter real beta = 0.5 from (-inf:inf); // - aging dependency with timeparameter real atsf = 1e12 from (-inf:inf); // - accelerating time scale factor, a fixed value

// e.g. 1e12: 1ps simul.time = 1s real time aging//--------------------------------------------------------real vd, id, ais, is_eff; // variables used in modeling section below

analog beginvd = V(br_AnodeCathode); // set variable vd: diode voltage//====================================================== calculate delta_is, diode aging: f(temp(=$vt), vd)agingtime = $abstime*atsf;ais = atsf * bis * exp(-eis / $vt) * pow(abs(vd),alpha) / pow(agingtime,beta);if (analysis("tran")) begin

if (analysis("ic")) begin // case: transient simulation, initial conditionV(br_isdelta) <+ 0.0; // short the branch br_isdelta


endend else begin

V(br_isdelta) <+ 0.0; // short the branch br_isdeltaend//====================================================== calculate: is_eff = is + is_delta_agingis_eff = is + V(br_isdelta);id = is_eff * (limexp(vd / (n * $vt)) - 1);


endendmodule

-31-

C=1 V(is_delta)ais

is_delta

Fitted AgingofParameter IS

-32-

Following the aging implementation of HiSIM-HV,an additional aging switch parameter CODEG has been added to the Verilog-A file:

...analog begin

vd = V(br_AnodeCathode);

//======================================== calculate delta_is, diode aging: f(temp(=$vt),vd)=====if (codeg==1) begin // simulate aging

agingtime = $abstime*atsf;ais = atsf * bis * exp(-eis / $vt) * pow(abs(vd),alpha) / pow(agingtime,beta);if (analysis("tran")) begin

if (analysis("ic")) beginV(br_isdelta) <+ 0.0;


endend else begin

V(br_isdelta) <+ 0.0;endis_eff = is + V(br_isdelta);

end else begin // else perform normal simulationis_eff = is;

end

//====================================================== calculate dc diode current ===========id = is_eff * (limexp(vd / (n * $vt)) - 1);I(br_AnodeCathode) <+ id;

end...

...analog begin

vd = V(br_AnodeCathode);

//======================================== calculate delta_is, diode aging: f(temp(=$vt),vd)=====if (codeg==1) begin // simulate aging




endend else begin



end

//====================================================== calculate dc diode current ===========id = is_eff * (limexp(vd / (n * $vt)) - 1);I(br_AnodeCathode) <+ id;

end...

-34-

Temperature Modeling

...

...

...

...// is_eff = aged parameter value 'is', calculated in the code above

// ====================================================== TEMP modeling ==========================t = $temperature;t_nom = tnom + `P_CELSIUS0;is_temp = is_eff * pow(t/t_nom, xti/n) * exp(eg / ($vt(t_nom) * n) * (t/t_nom - 1));

// ====================================================== calculate dc diode current =============id = is_temp * (limexp(vd / (n * $vt)) - 1);


endendmodule

Temperature dependence needs to be applied to the aged parameter IS,so that we end up with the same boundary conditions as with the models with self-heating implemented.

Note:the temperature equations can't be handled isolated from the core model, in a separate code block ,which is run only once, independently of bias and iterations.(this is sometimes done in some verilog-A models, to save CPU time).

...

...

...

...// is_eff = aged parameter value 'is', calculated in the code above

// ====================================================== TEMP modeling ==========================t = $temperature;t_nom = tnom + `P_CELSIUS0;is_temp = is_eff * pow(t/t_nom, xti/n) * exp(eg / ($vt(t_nom) * n) * (t/t_nom - 1));

// ====================================================== calculate dc diode current =============id = is_temp * (limexp(vd / (n * $vt)) - 1);


endendmodule

-35-

Agenda

Motivation





Conclusions

Motivation





Conclusions

-36-

1. Modeling @ t=0 2. Stress Modeling

3. Applying the Stress Modelto different Model Instances

(transient simulation t=2000s)

Instance 1 Instance 2va=-4V va=-3.5Vdone ! done !

AGING MODELING STEP 6:Obtaining the Aged Parameter Valuesfrom Aging Transient Simulations

IC Circuit with 2 neg. biasedDiode Instances

3.5V

4VColored Frames:

□ Model Switch□ Stress Parameters

same aging model card,but individual aging of each instance

due to individual stress levels

IC-CAP Icon: _2_diode_DC_VA IC-CAP ICON: _3_diode_aging_mdlg

IC-CAP Icon: _4_diode_aging_different_instances

-37-

1. Modeling @ t=0 2. Stress Modelingdone ! done !



Instance 1 Instance 2va=-4V va=-3.5V

AGING MODELING STEP 6:Obtaining the Aged Parameter Valuesfrom Aging Transient Simulations


due to individual stress levelsColored Frames:

□ Model Switch□ Stress Parameters

IC-CAP Icon: _4_diode_aging_different_instances


IS1_aged:527.54p IS2_aged:

682.33p

-38-

The question is, how to get the aged parameter values, shown in the slide before,

from the Verilog-A file

to an ASCII file,

which can later be used in the simulator to replace the non-aged parameters

e.g. using an ALTER statement (Spectre)

The question is, how to get the aged parameter values, shown in the slide before,

from the Verilog-A file

to an ASCII file,

which can later be used in the simulator to replace the non-aged parameters

e.g. using an ALTER statement (Spectre)

-39-

we currently have: (compare with the slide #34 above)

→ Last Enhancement to the Verilog-A File...

...analog begin

vd = V(br_AnodeCathode);//======================================== calculate delta_is, diode aging: f(temp(=$vt),vd)=====if (codeg==1) begin // simulate aging




endend else begin



end......

-40-

...

...analog begin





endend else begin



end......

...parameter string outfile="C:/tmp/par_degrad.out"; // output file name of parameter 'is' aging values...analog begin





endend else begin

V(br_isdelta) <+ 0.0;endis_eff = is + V(br_isdelta);//======================================== output is_eff to file ===================pardegfile=$fopen(outfile);$fwrite(pardegfile, "Set_IS_aged_%M alte r dev=%M param=is value=%.5g // vd=%.5g \n", is_eff, vd);$fclose(pardegfile);


end......

When in Aging Simulation Mode, the additional lines, marked in blue,output the Aged Parameter IS_eff and its Values to an ASCII file:

41

...parameter string outfile="C:/tmp/par_degrad.out"; // output file name of parameter 'is' aging values...analog begin





endend else begin

V(br_isdelta) <+ 0.0;endis_eff = is + V(br_isdelta);//======================================== output is_eff to file ===================pardegfile=$fopen(outfile);$fwrite(pardegfile, "Set_IS_aged_%M alte r dev=%M param=is value=%.5g // vd=%.5g \n", is_eff, vd);$fclose(pardegfile);


end......

Contents of File'par_degrad.out':

Set_IS_aged_XCKT.DMAIN1 alter dev=XCKT.DMAIN1 param=is value=5.2754e-010 // vd=-4Set_IS_aged_XCKT.DMAIN2 alter dev=XCKT.DMAIN2 param=is value=6.8233e-010 // vd=-3.5

AGING MODELING STEP 7:Simulating with the Aged Diode Instances:Parameters IS1 and IS2

1. Modeling @ t=0 2. Stress Modeling



Instance 1 Instance 2va=-4V va=-3.5Vdone ! done !

done !

Colored Frames:□ Model Switch□ Stress Parameters


due to individual stress levelsIC-CAP Icon: _4_diode_aging_different_instances


4. Simulating With Aged Performance

-42-

*** Netlist in Spectre syntax ***

// link to your circuit (design kit)include "/tmp/diode_aged_AlterCommand.scs"

subckt diode_aging (A1 C1 A2 C2)

// link to the previously saved, aged parameter valuesinclude "/tmp/par_degrad.out"

// Call subucircuit 'my_diodes' in the included circuit,// applying the aged param.valuesX1 (A1 C1 A2 C2) my_diodes

ends diode_aging

Spectre Netlist Applying/Linking the Aged Model Parametersahdl_include "C:/tmp/diode_aging.va"

subckt my_diodes (A1 C1 A2 C2)

*** diode model parameters ********************parameters is = 1E-10parameters n = 1

Rterm1 (is_delta1 0) resistor r=1E9Rterm2 (is_delta2 0) resistor r=1E9

*** diode instance 1 **************************DMAIN1 (A1 C1 is_delta1) DMAIN


*** common model card *************************model DMAIN diode_va+ is = is+ n = n

ends my_diodes

Verilog-ADiodeCODEG=0

*** Netlist in Spectre syntax ***

// link to your circuit (design kit)include "/tmp/diode_aged_AlterCommand.scs"

subckt diode_aging (A1 C1 A2 C2)

// link to the previously saved, aged parameter valuesinclude "/tmp/par_degrad.out"

// Call subucircuit 'my_diodes' in the included circuit,// applying the aged param.valuesX1 (A1 C1 A2 C2) my_diodes

ends diode_aging

IC-CAP Icon: _6_diode_aged_different_instances_by_Alter

ahdl_include "C:/tmp/diode_aging.va"

subckt my_diodes (A1 C1 A2 C2)

*** diode model parameters ********************parameters is = 1E-10parameters n = 1

Rterm1 (is_delta1 0) resistor r=1E9Rterm2 (is_delta2 0) resistor r=1E9



*** common model card *************************model DMAIN diode_va+ is = is+ n = n

ends my_diodes

-43-

Set_IS_aged_XCKT.DMAIN1 alter dev=XCKT.DMAIN1 param=is value=5.2754e-010 // vd=-4Set_IS_aged_XCKT.DMAIN2 alter dev=XCKT.DMAIN2 param=is value=6.8233e-010 // vd=-3.5

Test Scenario for Testing the Aging Model

In the Operating Circuit,the 2 Diode Instances are neg. biased, and suffer from stress (aging).

For inspection, they are unsolderedand their individual, aged ia(va) characteristic are measured (here: simulated).

-44-

Diode 1: va_stress=-4V

mea

sure

dbe

fore

stre

ss

afte

rst

ress

,si

mpl

edi

ode

mod

el[L

OG

]

1E-9

1E-8

1E-7

Diode 2: va_stress=-3.5V

mea

sure

dbe

fore

stre

ss

afte

rst

ress

,si

mpl

edi

ode

mod

el[L

OG

]

1E-9

1E-8

1E-7

Simulation of the Performance of the Aged/Stressed Diode Instances:ia(va) Curves

aging effect forsingle diodemodel range ~0.2V

aging effect forsingle diodemodel range ~0.2V

va1 [E+0]

mea

sure

dbe

fore

stre

ss

afte

rst

ress

,si

mpl

edi

ode

mod

el

-3 -2 -1 0 11E-10

va2 [E+0]m

easu

red

befo

rest

ress

afte

rst

ress

,si

mpl

edi

ode

mod

el

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.51E-10

IC-CAP Icons: _5_diode_aged_different_instances_by_ParamTransfer_6_diode_aged_different_instances_by_Alter

D1D2

-45-

Agenda

Motivation





Conclusions

Motivation





Conclusions

-46-

A complete flow for modeling the agingof electronic devices has been demonstrated.

For each step, a corresponding IC-CAP demo filehas been developed.

CONCLUSIONS

IC-CAP Files:

DiodeAging_all_in_One.mdl

plus

UTILITIES.mdl

Contact F.Sischka for a copy

-47-

The method supports different aging,for diode instances with different DC operating points,sharing the same Model Card.

This way, the other components around the aging component(s)experience the performance change and react correspondingly,resulting in a realistic aging simulation of complete ICs.

The method can describe a varying DC stressas a function of time,and even any shape of AC stress.

And it can describe the degradation of a complete circuitunder real and under accelerated aging conditions.

That's the whole point of being a Dynamic Aging Model.

CONCLUSIONS

The method supports different aging,for diode instances with different DC operating points,sharing the same Model Card.

This way, the other components around the aging component(s)experience the performance change and react correspondingly,resulting in a realistic aging simulation of complete ICs.

The method can describe a varying DC stressas a function of time,and even any shape of AC stress.

And it can describe the degradation of a complete circuitunder real and under accelerated aging conditions.

That's the whole point of being a Dynamic Aging Model.

-48-

Publicationsin addition to the ones already mentioned in Slide 3:

Mukherjee, Ardouin et.al., Reliability-Aware Circuit Design Methodology for Beyond-5G Communication SystemsIEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 17, NO. 3, SEPTEMBER 2017

Mukherjee et.al., Hot-Carrier Degradation in SiGe HBTs: A Physical and Versatile Aging Compact ModelIEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 12, DECEMBER 2017

Verilog-A Tutorials:G.J.Coram, "How to (and how not to) Write a Compact Model in Verilog-A",

Proc. 2004 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2004)

G.J.Coram, C.McAndrew, "Verilog-A for Compact Modeling: Best Practices", CMRF2005

Verilog-A Manual:Accellera Systems Initiative, "Verilog-AMS Language Reference Manual", Version 2.4.0, May 30, 2014

Publicationsin addition to the ones already mentioned in Slide 3:

Mukherjee, Ardouin et.al., Reliability-Aware Circuit Design Methodology for Beyond-5G Communication SystemsIEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 17, NO. 3, SEPTEMBER 2017

Mukherjee et.al., Hot-Carrier Degradation in SiGe HBTs: A Physical and Versatile Aging Compact ModelIEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 12, DECEMBER 2017

Verilog-A Tutorials:G.J.Coram, "How to (and how not to) Write a Compact Model in Verilog-A",

Proc. 2004 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2004)

G.J.Coram, C.McAndrew, "Verilog-A for Compact Modeling: Best Practices", CMRF2005

Verilog-A Manual:Accellera Systems Initiative, "Verilog-AMS Language Reference Manual", Version 2.4.0, May 30, 2014

-49-

eMail: [email protected]

www.SisConsult.de

-50-

www.xmodtech.com

eMail: [email protected]

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