modeling of self- & mutual-inductance for traces … of self- & mutual-inductance for traces...

© International Microelectronics And Packaging Society

The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number3, Third Quarter 2000 (ISSN 1063-1674)

Intl. Journal of Microcircuits and Electronic Packaging

244

Modeling of Self- & Mutual-Inductance ForTraces Partially Influenced by the Conductive DieAttach in Chip Scale BGA

Maoyou Sun and M. F. CaggianoDepartment of Electrical and Computer EngineeringCollege of EngineeringRutgers University94 Brett RoadPiscataway, New Jersey 08854-8058Phone: 732-445-0678Fax: 732-445-2820e-mails: [email protected], [email protected]

Abstract

The effect of parasitic inductance in the Chip Scale Ball Grid Array, CSBGA, is significant at frequencies of one gigahertz and higher.Modeling of its effect is necessary to optimize its design and simulate the package circuit performance. In this paper, a computermodel of the parasitic inductance for the CSBGA is demonstrated. The model considers the significant contributions of the partialground effect generated by the conductive die attach material on both the self and the mutual inductance. The model simplifies the3D problem into a 2D one rather than using the commonly employed boundary element method, Finite Difference method, or FiniteElement method. These other methods are usually complicated and require longer run times. This is accomplished by making asmart projection of the trace in three-dimensional space onto a plane. Based on available formulas in the previous References1,2, theself- and mutual-inductance for traces on different layers and with a ground plane formed by the conductive die attach material canbe quickly extracted. Finally, these routines are simulated with a commercially available 3D solver program which employs a fastmultipole method. The simulation results show that the model is accurate with relative error of less than 10%.

Key words:

Chip Scale, FPBGA, EMI, and Mutual Inductance.

1. Introduction

The rapid advances of very large scale integration technologyare shrinking the device size while increasing the density andthe IC operating speed. In the near future, many systems will beimplemented on a single chip. With the dense integration of themixed-signal circuits together, one critical issue needed to besolved is the electromagnetic interference (EMI) and electromag-

netic compatibility (EMC) within the chip, within the package,and between the chip and the package. In the dense and com-pact IC package, the parasitic self and mutual inductance willsignificantly affect the chip core IC performance at frequenciesapproaching one giga-hertz. For example, in the higher fre-quency applications, such as 900MHz and 1.8GHz cordless phoneor cellular phone, the effect will be very observable, becomingmore significant with increasing frequencies. Therefore, model-ing and simulation of this parasitic effect is necessary in order tooptimize the package design and simulate the packaged circuitperformance. The Chip Scale Ball Grid Array (CSBGA) pack-age has a prevalent distribution due to its small size and goodapplication for high frequency ICs. The parasitic self and mu-tual inductance between the traces is around a 2-3 nano-henries,and less than 1 nano-henry, respectively.

In this paper, a computer model of the parasitic inductancefor the CSBGA is demonstrated. This model considers the sig-nificant contributions of the partial ground effect generated by

Modeling of Self- & Mutual-Inductance For Traces Partially Influenced by the Conductive Die Attach in ChipScale BGA


© International Microelectronics And Packaging Society 245

the conductive die attach material on both the self and the mu-tual inductance. First, some typical trace configurations are ex-tracted from the package drawings. Then, based on fundamen-tal electromagnetic theory, the three dimensional problem is sim-plified into a two dimensional one by a smart projection of thetwo traces onto the same plane. In this way, the mutual induc-tance can be quickly extracted3-5 as opposed to solving the com-plicated differential equations and setting the boundary condi-tions. Considering the large number of traces within a package,the time savings with this method is significant. To verify thismodeling method, Ansoft Q3D maxwell extractor7 was used tosimulate all the modeled configurations presented. Comparisonof the results of both simulations shows the rapid simulationmethod provides a good approximation where the relative dis-agreement is within 10%.

2. Chip Scale BGA with TypicalGeometric Configurations

The mutual layer chip scale BGA package structure is shownin Figure 1. The chip is glued onto the silver-epoxy layer, whichis grounded. The chip bond pad is connected to the package toptrace, which is below the dielectric. This trace runs from thewirebond finger to the package via to the trace below. The bot-tom trace continues below the package material from the via tosolder ball. More detail descriptions could be referred in previ-ous publication5. For some basic trace configurations, where thetraces lie on the same layer, the formulas for self and mutualinductance can be found in F. W. Grover’s work1 and C. S.Walker’s work2. For the traces on different layers or with partialground plane coverage below them due to the silver-epoxy dieattach layer, there are no available formulas which can be used.These routines in CSBGA can be classified as three cases. CaseA considers two traces on two different parallel planes, one onthe top layer from the package pad to via and the other on thebottom layer from via to ball. In Case B, the two traces are on thesame plane, either on the top layer or the bottom layer but apartial ground plane exists below them. In Case C, the two tracesare on two different parallel planes (as in case A), however, thereis a partial ground plane just below them. The partial groundplane is due to the die attach silver-epoxy layer.

chipsilver-epoxy

wire

pad

top metal trace

ball

via

dielectric

bottom metal trace

package material (plastic)

Figure 1. Mutual layer chip scale BGA package.

3. Theoretical Analysis andSimplification Method

To calculate the mutual inductance of two traces in three-di-mensional space, one effective way is to transform the 3D prob-lem into 2D problem. Then, the problem is simplified into thecase as shown in Figure 2, where two random traces lie on thesame plane and the mutual inductance between them can be cal-culated based on the formula in Reference1. The projection prin-cipal is according to the electromagnetic theory. As long as themagnetic flux through the area between the two traces is kept thesame, the mutual inductance between them should be same. Inthis way, one trace can be projected onto the plane which theother trace lies. Figure 3 shows the projection process. Themutual inductance between trace A1A2 and trace B1B2 is equalto that between the trace A1A2 and the curve trace BB1BB2. Tosimplify the calculation, the straight trace BB1BB2 is used inplace of the curve one.

Figure 2. Two random traces on one plane.

-2-1

01

2

0

12

340

0.5

1

1.5

xy

z

Projection of Trace to the Bottom Plane

A2

BB2

A1

B2

B1

BB1

Figure 3. Projection of two traces on a plane, the mutualinductance between A1A2 and B1B2 is approximatelyequal to that between A1A2 and BB1BB2.

To calculate the mutual inductance of two traces with a groundplane below them, as in case B and C discussed in part 2, theformula based on four conductor systems can be used6. As shownin Figure 4, the mutual inductance for the system is given asfollows,




246

M5 = π

µµ2

or*

2413

2314lnDD

DD

(1)

The total mutual inductance equals the sum of inductance foreach conductor in loop A with loop B, and can be expressed asfollows,

232414135 MMMMM −+−= (2)

For two traces with a ground plane below them, the groundeffect can be equivalently represented by their images. The traceand its image form a return loop. The mutual inductance be-tween these two traces will be equal to half the mutual induc-tance of the four-conductor system shown in Figure 4. This isdue to the magnetic flux through the area between the trace andground plane is reduced to half of the four conductor system.

loop Aloop B

1

2

3

4

(a)

1

D14

2

3

4

D13

D24

D23

(b)

Figure 4. Mutual inductance for four conductor system. (a)Top view (b) Edge view.

4. Modeling and Extraction of the Self-& Mutual-Inductance

4.1. Mutual Inductance Between Two Traceson Different Planes

As shown in Figure 1, for two traces on different planes (CaseA discussed in part 2), the above projection methods can be usedto calculate the mutual inductance. The program first requires aprojection function to make this transformation. After that, a

parallel function is defined to check whether the projected traceis exactly parallel to the other. If so, one trace is rotated a smallangle Q, about five degree. Otherwise, an undefined result willbeen obtained since µ and ν become infinite.

In a CSBGA package, the lengths of some traces are smallerthan the distance between them. If the traces are also parallel ornearly parallel, the values of µ and ν will become very large andthis will lead to a significant error. In this case, the effect of asmall difference between the practical trace distribution and thetrace position used in the program is significant. More detailsare discussed in Reference3. The program skews one trace asmall angle to effectively reduce this kind of error. On the con-trary, if the lengths of the traces are much longer than the dis-tance between them, skewing one trace for a same small anglewill have a large impact on the value.

To reduce this kind of effect, a minimum distance is main-tained between two traces. In addition, a factor F is defined inthe program to indicate the ratio of the distance to the length ofthe traces. With regard to Figure 2, F is given as follows,

F = )(2

)4321(

ml

RRRR

++++

(3)

If the program tests the traces’ position and they are withinthe parallel limitation, then one trace will be skewed an angle

α * F . To test if this modeling is correct, the mutual induc-tance is simulated for all cases rotating one trace every ten de-gree starting from the parallel case. The simulations are com-pared with the results extracted by a commercially available 3Dsolver7. The results are shown in Figure 5, where each trace is0.5 cm (200 mils) long, 0.2 mm (8 mils) away from each otherhorizontally, and 0.2 mm (8 mils) vertically. The comparisonshows an excellent match between these results and those of the3D extractor.

Figure 5. Mutual inductance for two traces on differentplanes, where (+) is 3D extractor’s result; (*) our model’sresult.




4.2. The Mutual Inductance for One or TwoTraces Partially over the Ground Plane

For case B and C discussed in part 2, in which two traces bothare partially over the ground plane due to the die attach material,the mutual inductance can be modeled according to the abovetheoretical analysis. One elementary procedure, to calculate themutual inductance, is to separate the trace into two parts. Onepart is just above the ground plane and the other is uncovered bythe ground plane.

To consider the ground effect, the image of the trace above theground plane was included. As shown in Figure 6, the mutualinductance can be approximately given as follows,

M = M1 - M2 + M3 - M4 (4)

where M1 is the mutual inductance between AB and EF, M2 isthe mutual inductance between AB and D’F’, M3 is the one be-tween C’A’ and D’F’, and M4 is that between C’A’ and EF. A’C’and D’F’ are the images of the traces AC and DF, respectively.Each mutual inductance can be calculated by the above projec-tion method.

Figure 6. Two traces both are partially over a ground planewith their image parts.

For the case in which one trace extends beyond the groundplane but the other is covered by the ground plane, the mutualinductance is divided into two parts. Figure 6 considers the mutualinductance between BC and EF. The mutual inductance will beapproximately given by the following expression,

M = M1 - M2 (5)

where M1 is the mutual inductance between BC and EF, and M2is that between BC and D’F’.

To check the accuracy of the above approximation, severaltrace configurations are simulated and compared with a com-mercially available 3D solver7. The first mutual inductance casestarts with the two traces initially parallel and then one is rotatedin ten-degree increments. For the case B (discussed in part 2),two traces on the same plane, only 0 to 200 degree are simulated,since beyond that the traces will intercept. For each case, onetrace is 7.5 mm (300 mils) long, and the other is 5 mm (200

mils). When considering this case, the wirebond finger is sepa-rated from under the die attach by about 2.5 mm (100 mils),therefore, one can position both trace wire bond fingers awayfrom the ground by this 2.5 mm (100 mils). The remaining partis covered by the ground plane. For case B, the separation dis-tance is 0.2 mm (8 mils) and both of them are 0.2 mm (8 mils)above the ground. For case C, the two traces are 0.2 mm (8mils) away from each other horizontally, and the longer trace is0.05 mm (2 mils) above the ground, and the short one is about0.31 mm (12 mils). This corresponds to the top layer long traceand the bottom layer shorter one. As shown in Figure 7, thematching for the two traces between 80 and 280 degrees is goodbut for the near parallel case, it is not as good.

Figure 7. Mutual inductance for the case B and C discussedin part II, where (+) is the 3D extractor’s resulty; (*) ourinitial model; (O) our improved model by moving trace imageone tenth of the trace length; (x) our improved model bymoving trace image two tenth of the trace length.




248

4.3. The Improved Model for MutualInductance of Two Traces Partially over theGround Plane

The partial ground plane causes the mismatch (shown in Fig-ure 7) near the parallel position. Considering Figure 8, if theground plane extends to infinity, the image of the trace AC isA’C’, but for the present instance the image of point C should befurther away from the ground plane than point C’. To considerthis effect, one can move C’ away from the ground plane by aboutone tenth of the length of trace AB to C”, as shown in Figure 8.One can do same thing for the other trace. Then, one can repeatthe simulation and compare the results with a 3D solver7. Abetter match is thus obtained for all cases. The improved simu-lation results are also illustrated on Figure 7.

Figure 8. Improved model for the mutual inductance inFigure 6 by moving C’ far away the ground plane to C”(cross section view of trace AC).

4.4. Self Inductance for Traces Partially Overthe Ground Plane

For traces that are partially over the ground plane, one simpleand accurate approximation, to calculate the self-inductance, isto separate the trace into two parts. One is over the ground planeand the other is off the ground plane. The self-inductance will beequal to the sum of the two parts’ self-inductance. As shown inFigure 9, the self-inductance is given as follows,

Ls.AB = L

s.AC + L

s.CB (6)

where Ls.AC and L

s.CB are the self-inductance of trace AC with-

out ground plane, and the self-inductance of trace CB with groundplane, respectively. The formulas for self-inductance are avail-able in the Reference4-5. The simulation results and the 3D ex-tractor are shown in Figure 10. It can been found that thesesimulation results match well with the Q3D extractor. The twopeaks at 90 and 270 degree for the 3D extractor7 are due to themutual inductance between the trace and the ground plane. There-fore, the total self inductance is equal to its own self inductancewithout ground plane plus their mutual inductance. At 180degree, this mutual inductance is zero since the trace is perpen-dicular to the edge of the ground plane.

Figure 9. The self-inductance for the trace partially over theground plane.

Figure 10. The self-inductance of a trace over a partial groundplane, the trace thickness 1 mil and width 3 mils and length200 mils, and 120 mils above ground plane, where (+) is 3Dsolver’s result, (*) is the model devised by the researchers.

5. Conclusions and Future Directions

A computer model of the parasitic self and mutual inductancein the multiple layer Chip Scale BGA package is demonstrated.This model considers the significant ground effect due to theconductive die attach material. Some 3D trace configurations inCSBGA were taken from the package drawings. Instead of em-ploying the common used 3D problem solving methods, thismodel simplifies the 3D problem into a 2D one by making asmart projection of the traces, in three dimensional space, ontothe same plane. In this way, the CSBGA parasitic self and mu-tual inductance for traces on different layers and with a groundplane due to the die attach layer below them, can be quickly cal-culated. To verify the accuracy of this model, Ansoft MaxwellQ3D extractor, which employs the multipole method, is used tosimulate these package configurations also. The results showthat this model is accurate to within 10%. Not only can it quicklysolve for the inductance, but also the results match well withAnsoft Q3D extractor.

The projection of the top trace onto the plane of the bottomtrace forms a curved trace. The procedure for calculating themutual inductance does not take into account this curvature[8,9,10].One technique for handling the curvature would be to approxi-




mate the curved trace as a trace with a bend in it. This wouldprovide a more accurate representation of the trace position.Future research in techniques for solving for mutual inductanceof traces with bends in them is currently being worked on. Bet-ter calculations for mutual inductance of traces on different planescan be obtained by applying these new routines.

Acknowledgments

The authors would like to thank David Lischner and DonnaNoctor in the Packaging and Reliability Development Group ofLucent Technologies for providing package dimensions and in-sightful discussions.

References

1. F. W. Grover, “Inductance Calculation, Working Formulasand Tables”, Dover Publications Inc., New York, New York,pp. 6-58, 1973.

2. C. S. Walker, “Capacitance, Inductance, and Crosstalk Analy-sis”, Artech House Inc., Boston, Massachusetts, pp. 85-125,1990.

3. M. F. Caggiano, R. M. Brush, etc. “Electrical Modeling of theChip Scale BGA”, Proceedings of the 48th Electronics Com-ponents and Technology Conference, ECTC ‘98, Seattle,Washington, pp. 1280-1285, May 1998.

4. M. F. Caggiano, “A PC Program That Generates a Model ofParasitics for BGA Package ”, Proceedings of the 45th Elec-tronics Components and Technology Conference, ECTC ‘95,Las Vegas, Nevada, pp. 959-963, May 1995.

5. M. F. Caggiano, “RF Electrical Measurements Comparisonsof a 64 TQFP with a Computer GeneratedModel”, AppliedMicrowave and Wireless, Vol. 9, No. 4, pp. 24-36, July 1997.

6. W.E. Rogers, “Introduction to Electrical Field”, New York,McGraw-Hill, pg. 316, 1950.

7. “Maxwell Q3D Extractor”, Ansoft Company, December 19978. M. Sun, M. F. Caggiano, “Modeling of Self & Mutual-Induc-

tance for Traces Partially Influenced by the Conductive DieAttach in Chip Scale BGA”, International Conference andExhibition on High Density Interconnect and System Pack-aging, Denver, Colorado, April 25-28, pp. 295-300, 2000.

9. M.F. Caggiano, R. M. Brush, J. T. Kleban, and P. J.Chuaypradit, “Computer Program that Generates an Electri-cal Circuit Model of the Chip Scale BGA”, MicroelectronicsJournal, Vol. 29, No. 12, December 1998.

10. A. J. Rainal, “Computing Inductive Noise of Chip Pack-ages”, AT&T Bell Laboratories Technical Journal, Vol. 63,pp. 177-195, January 1984.

About the authors

Maoyou Sun received his Bachelor of Science Degree in Phys-ics from Lanzhou University, P.R. China, and Master’s Degreein Electrical Engineering from Rutgers University, New Jersey,in 1999. He is presently working towards the Ph.D. degree atRutgers University. He was a Member of the Technical Staff atNational Semiconductor Center, BGRINM, China from 1989 to1995. He has recently joined Anadigics Company as a RF engi-neer. His research interests are in RF modeling of the Crosstalkin IC packages and RF circuit and package co-design.

Michael Caggiano received his Bachelors in Electrical Engi-neering from CCNY, Masters of Electrical Engineering alsofrom CCNY and was awarded a Ph.D. from UCLA in 1979. Hewas a Member of the Technical Staff at the Electronics ResearchCenter of Rockwell International, Anaheim, California, from 1975to 1978 and an MTS of Hughes Aircraft Co., from 1978 to 1980.He became a member of the technical staff of Bell Labs, Holmdel,New Jersey in 1980 and has been a visiting professor at RutgersUniversity in the Department of Electrical and Computing Engi-neering since January 1988. In September of 1996, he joinedRutgers as a full time faculty member in the Solid State Electron-ics Group and has a collaborative association with WINLab atRutgers. At Bell Labs, he was the subject matter expert in thefield of electrical packaging of high performance and microwaveIC packaging. The programs developed generated the packagecircuit models for the Lucent (AT&T) entire line of high perfor-mance data processor and RF ICs.

modeling of self- & mutual-inductance for traces … of self- & mutual-inductance for traces...

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