modeling r-2r segmented-ladder dacs

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010 31

Modeling � �� Segmented-Ladder DACsDavid Marche and Yvon Savaria, Fellow, IEEE

Abstract—Although � ladders are commonly used asdigital-to-analog converter (DAC) cores, complete equivalentcircuits are still missing from the literature for most of the con-figurations used in practice. In this paper, expressions for theinput and output impedances of � ladders are derived forcurrent- and voltage-mode operations. In addition, since manyDACs use segmentation to reach higher resolutions, the impedanceexpressions are also obtained for different segmentation schemes.Using these expressions, the existing current-mode model is ex-tended to segmented architectures, and a new equivalent circuitis proposed for voltage-mode designs. This allows modeling themost common � DAC designs. Simulation results producedwith the proposed models are compared to measurements on two14-bit � DAC prototypes. These results demonstrate howimpedance variation with code can limit the static performancesof high-resolution converters.

Index Terms— DAC, � , model, impedance.

I. INTRODUCTION

T HE ladder is a compact resistive network whichcan generate binary weighted current or voltage levels and

is mostly used in digital-to-analog converters (DAC) [1]. Basedon a reduced set of identical components, they are well suitedto layout optimization for reaching low mismatch levels criticalin high-resolution flash converters. Furthermore, resistive net-works are naturally suited to laser trimming matching enhance-ment, allowing even higher resolution products. References [2]and [3] are examples of such products that are commerciallyavailable. Even though such converters are widely available,little information can be found on the challenges faced whendesigning such high-resolution converters.

Resistor deviation is the most obvious linearity pa-rameter: The relation between mismatch level and maximumdifferential nonlinearity (DNL) is well known and highlights theneed for calibration or trimming solutions [4], [5]. For voltage-mode ladders, an expression of the output voltage in terms ofresistance ratio is derived in [6] along with test and trimmingstrategies. In [7], a similar analysis is conducted for the cur-rent-mode ladder, and other major sources of errors are listed:switches and wire resistance. Indeed, switching circuitry is crit-ical for settling time, but switch resistance itself can have sig-nificant impact on linearity. An overview of explored switchsizing and compensation solutions can be found in [8]. The inputand output impedance expressions for the current-modeDAC are derived in [9] and can be used to compute the impactof wire resistance on linearity for this configuration.

Manuscript received October 02, 2008; revised January 20, 2009. First pub-lished March 27, 2009; current version published January 20, 2010. This paperwas recommended by Associate Editor M. Delgado-Restituto.

The authors are with the Department of Electrical Engineering, ÉcolePolytechnique de Montréal, Montréal, QC H3T 1J4, Canada (e-mail:[email protected]).

Digital Object Identifier 10.1109/TCSI.2009.2019396

Fig. 1. Current-mode �� DAC.

Fig. 2. Zurada and Goodman’s current-mode �� DAC equivalent circuit.

For hand analysis or fast simulation in larger systems, it isoften desirable to use high-level models which are accuratesimple equivalent circuits. This is particularly true for DACssince the number of input codes to be verified grows exponen-tially with the input word bit count, making exhaustive codescan simulation difficult for high-resolution designs. In thesecases, if no high-level model is available, partial simulations areoften used, and the designer’s knowledge and understanding ofsignificant factors involved become critical. Although currentand voltage analog output expressions are available, complete

DAC models including input and output impedancesare still limited to current-mode ladders with no segmentation[9]–[11]. This is a significant drawback since most recent

networks use segmentation to meet the ever-increasingresolution demand. Furthermore, many converters are based onthe voltage-mode operation of the network for which noimpedance expressions have been published yet. Thus, actualmodels have limited value for today’s DAC simulation andoptimization.

The objective of this paper is to present new models derivedfor all the most common DAC structures: voltage-and current-mode , with or without segmentation. InSection II, the existing current-mode model is extended tosegmented designs. In Section III, an equivalent circuit is pro-posed for voltage-mode converter and is also valid forsegmented architectures. An analysis of the model limits andcircuit implications follows in Section IV with some simulationresults. Before concluding, a practical high-resolution

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32 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 1, JANUARY 2010

Fig. 3. Current-mode DAC segmentation. (a) Addition of �� stages. (b) Addition of� stages. � and� subscripts denote the thermoencoded and binary-encodeddigital inputs, respectively.

DAC design case is studied in Section VI: Simulation resultsbased on the simplified models are compared with chip mea-surements to show the significant impact of code-dependent

impedance on linearity.

II. CURRENT-MODE

A. All Binary Current-Mode s (No Segmentation)

Fig. 1 shows a current-mode ladder with -bitresolution. The equivalent circuit proposed by Zurada andGoodman [10] is shown in Fig. 2. In this configuration, theinput impedance is simply equal to , and most of themodel’s complexity lies in the expression of the output resis-tance , which is code dependent

(1)This expression was derived by Erb and Wierzba, and com-

plete derivation details can be found in [9]. Note that the outputcurrent source is proportional to the digital input

(2)

B. Current-Mode Segmentation

Fig. 3 shows two possible segmentation solutions commonlyused to extend the ladder with unary weighted bits.

In these configurations, binary weighted stages are controlledby binary-encoded bits , and unary weighted stages arecontrolled by thermoencoded bits . Both options willallow segmentation but lead to different areas and impedance ofthe network.

1) Segmentation A: Additional unary weighted stages arecontrolled by thermoencoded bits [cf. Fig. 3(a)]. This so-lution requires a larger area and results in a higher inputimpedance.

2) Segmentation B: Additional unary weighted stagesare controlled by thermoencoded bits [cf. Fig. 3(b)].This solution requires less area and results in a lowerinput impedance. In this case, the current drawn from thevoltage reference input is higher.

Zurada’s model (cf. Fig. 2) is also valid for the segmentedversions of the DAC, but the input impedance and output

Fig. 4. Setup for output impedance analysis of the current-mode �� withsegmentation A.

Fig. 5. Binary-bit � contribution to the test source current with type-A segmen-tation (current mode).

impedance expressions must be adapted. The derived ex-pressions for these cases are given in Sections II-C and D.

C. Current-Mode With Type-A Segmentation

When segmentation A is used [Fig. 3(a)], the input impedancecan be expressed as a function of thermobit count

(3)

Fig. 4 shows the setup for output impedance analysis: Atest voltage source is connected at the output, and theinput voltage reference source is grounded. The outputimpedance can be derived if the expression of the currentsourced by the test voltage is obtained: .

Fig. 5 shows the contribution of one active binary bit tothe test source current. In this configuration, all thermoresistorsare shorted, and the binary segment currents are not affected


MARCHE AND SAVARIA: MODELING SEGMENTED-LADDER DACs 33

Fig. 6. Unary bit � contribution to the test source current with type-A segmen-tation (current mode).

by the segmentation. In this case, the expression of binary-bitcontribution to derived by Erb and Wierzba [9] is still valid

(4)

Fig. 6 shows a circuit that reflects the contribution of one ac-tive thermobit to the test source current. Since all thermosexcept one are shorted to ground, the current contribution issimply and independent of other bits states. Note thatthe binary most significant bit (MSB) can be either consideredas a thermobit or a binary bit , but its current contri-bution must be counted only once.

By superposition, the current contribution of all thermos andbinary bits can be added to get the expression of the total currentflowing out of the test source

(5)

The corresponding output impedance is given by(6), shown at the bottom of the page. Note that these expres-sions are valid for both segmented and unsegmentedarchitectures : Setting into (6) gives back (1).

D. Current-Mode With Type-B Segmentation

Segmentation B (Section III-B) offers half the inputimpedance of segmentation A

(7)

Fig. 7. Setup for output impedance analysis of the current-mode �� withsegmentation B.

Fig. 8. Unary bit � contribution to the test source current with type-B segmen-tation (current mode).

Fig. 7 shows the setup for output impedance analysis in thecase of type-B segmentation. The test source current in this con-figuration must be derived to obtain the output impedance ex-pression. Fig. 5 shows the contribution of one active binary bit,and the binary segment contribution is given by (5).

Fig. 8 shows the contribution of one active thermobit .Since all thermos are shorted to ground, their current contribu-tion is simply .

By superposition, the current contribution of all thermos andbinary bits can be added to get the expression of the total currentflowing out of the test source

(8)

The corresponding output impedance is given by (9), shownat the bottom of the next page. This expression is also valid forunsegmented architectures since setting gives back (1).

(6)



Fig. 9. Voltage-mode �� DAC.

Fig. 10. Voltage-mode DAC segmentation. (a) Addition of �� stages. (b) Addi-tion of� stages. � and� subscripts denote the thermoencoded and binary-en-coded digital inputs, respectively.

III. VOLTAGE-MODE

Voltage-mode operation is another common use ofladders. Fig. 9 shows a voltage-mode ladder with resolu-tion . In this case, input impedance becomes code dependent,and output impedance is constant.

A. Voltage-Mode Segmentation

As for the current-mode operation, there are two commonlyused segmentation options to extend the resistor binary ladderwith unary weighted bits. Fig. 10 shows these two solutions.Binary weighted stages are controlled by binary-encoded bits

, and unary weighted stages are controlled by ther-moencoded bits .

B. All Binary Voltage-Mode s (No Segmentation)

Output impedance, when no segmentation is used, is not af-fected by the resolution of the converter

(10)

Fig. 11 shows the setup for the input impedance analysis: Atest voltage source is connected at the input, and the output

Fig. 11. Setup for the input impedance analysis of the voltage-mode ��(no segmentation).

Fig. 12. Bit � contribution to the test current (voltage mode; no segmentation).

is left open. The input impedance is derived by finding theexpression of the current sourced by the test voltage.

Fig. 12 shows the current contribution drawn from each bitwhen one bit is active. Superposition theorem can then be usedto add these current contributions and compute the total testsource current.

(9)



With ideal resistors, it is easy to see that . How-ever, the expression for is not so obvious

(11)

Thus,

(12)

(13)

(14)

Moreover, the current contribution of bit is

(15)

The expressions of all other branch currents caused by theactive bit are

(16)

(17)

By superposition, the total current drawn from the test sourcecan be expressed as

(18)

Fig. 13. Setup for the input impedance analysis of the voltage-mode ��with segmentation A.

Fig. 14. Binary-bit � contribution to the test current with type-A segmentation(voltage mode).

With the appropriate change of variable, (16) and (17) can beinserted into (18) to get the total test source current expression(13). Thus, the input impedance of the unsegmented voltage-mode ladder is (14).

C. Voltage-Mode With Type-A Segmentation

When segmentation A is used [Fig. 10(a)], the outputimpedance can be expressed as a function of thermoencodedbit count

(19)

Fig. 13 shows the setup for the input impedance analysis: Atest voltage source is connected at the input, and the output

is left open.The input impedance can be derived if the expression of the

current sourced by the test voltage is obtained: .Fig. 14 shows the contribution of a binary bit to the test source

current. Fig. 15 shows the equivalent simplified ladder usedfor binary-bit contribution analysis. Thermoresistors have beengrouped together in a single equivalent resistor

(20)

With ideal resistors, it is easy to see that . How-ever, the expression for is not so obvious, and it can beshown to be

(21)



Fig. 15. Simplified ladder for the analysis of binary-bit � contribution to thetest current (voltage mode).

Thus,

(22)In addition, the current contribution of binary bit is

(23)

This is the expression of the test source current when all inputbits are set to zero except one of the binary bits. The generalsolution valid for any number of active binary bit requires theexpression of all branch currents caused by an active binary bit.Solving for the network of Fig. 15, we find that

(24)

(25)

Equations (23)–(25) are the current contributions of the bi-nary weighted section only. To analyze thermobit contributions,the ladder can be simplified as shown in Fig. 16, where the bi-nary part is replaced by an equivalent resistance: .In this case,

(26)

(27)

(28)

Fig. 16. Unary part of the segmented DAC.

Moreover, the current contribution of bit is

(29)

Other thermobranch currents caused by a unary bit are

(30)

The interaction between unary and binary segments must alsobe taken into account. Currents in the binary ladder due to theunary bit are

(31)

and currents in the unary ladder due to the binary bit are

(32)

By superposition, the total test source current is

(33)

With the appropriate change of variables, (23), (24), (25),(29), (30), (31), and (32) can be inserted into (33) to get thetest source current expression (35) and the input impedance ex-pression (36), shown at the bottom of the page. Note that thisexpression is valid for both segmented and unsegmented archi-tectures: Setting gives back (14).

D. Voltage-Mode With Type-B Segmentation

When segmentation B is used [Fig. 10(b)], the outputimpedance can be expressed as a function of thermoencodedbit count

(34)



Fig. 17 shows the setup for the input impedance analysis. Theinput impedance can be derived if the expression of the current

, shown at the bottom of the page, sourced by the test voltageis obtained: .

Fig. 15 shows the equivalent simplified ladder used forbinary-bit contribution analysis. Thermoresistors have beengrouped together in a single equivalent resistor

(37)

With ideal resistors, it is easy to see that . It canalso be shown that the expression for is

(38)

Thus,

(39)Moreover, the current contribution of binary bit is

(40)

This is the expression of the test source current when all inputbits are set to zero except one of the binary bits. The generalsolution valid for any number of active binary bit requires theexpression of all branch currents caused by an active binary bit.Solving for the network of Fig. 15, we find that

(41)

(42)

Equations (40)–(42) are the current contributions of the bi-nary weighted section only. To analyze thermobit contributions,the ladder can be simplified as shown in Fig. 16, where the bi-nary part is replaced by an equivalent resistance: .In this case

(43)

(44)

(45)

In addition, the current contribution of bit is

(46)

Other thermobranch currents caused by a unary bit are

(47)

The currents in the binary ladder due to the unary bit are

(48)

and the currents in the unary ladder due to the binary bit aregiven by (49)–(51), shown at the bottom of the next page.

By superposition, the total test source current is

(52)

With the appropriate change of variables, (40)–(42) and(46)–(49) can be inserted into (52) to get the test source currentexpression (50) and the input impedance expression (51). Note

(35)

(36)



Fig. 17. Setup for the input impedance analysis of the voltage-mode ��with segmentation B.

Fig. 18. Equivalent circuit for voltage-mode �� DAC.

that this expression is valid for both segmented and unseg-mented architectures: Setting gives back (14).

E. Voltage-Mode Equivalent Circuit

The proposed equivalent circuit for voltage-mode operationis shown in Fig. 18. This same model can be used for bothsegmented and unsegmented ladders, given that the input andoutput impedance expressions are adapted to the ladder type.These expressions were derived in the previous sections ac-cording to the segmentation type [cf. (10), (19), (34), (14), (36),and (51)].

If voltage output deviations due to resistance mismatch mustbe simulated, the ideal voltage source can be replacedby the output expression in terms of resistor ratios derived in[6]. This would allow a Monte Carlo simulation including errorscoming from ladder mismatch.

IV. VOLTAGE-MODE MODEL CONSIDERATION

The following is a list of considerations related to the useof the simplified voltage-mode DAC model shown inFig. 18.

1) Input Node: Although grounded in our analysis, the neg-ative input node of the equivalent circuit can be tied to anotherpotential. This can be used on purpose to set the output voltagerange lower limit.

2) Output Impedance: Since voltage-mode DACshave a constant output impedance, the stabilization of anyoutput amplifier is simplified. The stable nature of the outputimpedance also allows loading the DAC without linearity loss.In this case, the load resistor can be used to adjust the converterfull-scale output (i.e., gain).

3) Input Impedance: Voltage-mode DACs have acode-dependent input impedance. The input impedance of theDAC sets the input voltage reference loading. To validate ourmodel, a segmented voltage-mode DAC was netlistedand simulated with the Hspice simulator to measure the inputreference current for all possible digital input codes. The testnetlist is a 16-bit segmented voltage-mode ladder basedon 50-k resistors and using segmentation A with three ther-moencoded bits. The same circuit simulation was performed an-alytically using our proposed model: (36) was used with

, , and k . Fig. 19 shows the reference currentas computed with our model and as simulated with Hspice. Theanalytical solution is very accurate with a maximum error of 30ppm, arising from the single-pole double-throw (SPDT) switch

values, which are not considered in our model. Consideringthe complexity of the derived equations, the observed accuracyof the results constitutes a useful validation of our models. Ap-propriate reference circuit design or selection must take into ac-count the DAC input current curve in order to get accurate con-verters.

4) Reference: It was found in practice that, in high-resolutiondesigns, the varying input impedance puts some constraints onthe reference distribution network. Indeed, since the referencecurrent varies with the digital input code, the voltage drop acrossthe reference distribution path modulates the reference voltagelevel seen by the converter. For high-resolution converter, this

(49)

(50)

(51)



Fig. 19. 16-bit segmented voltage-mode �� reference current computation (type-A segmentation, � � ��, � � �, � � � V, and � � �� k�).(a) Simulated solution with Hspice and a complete netlist and (b) analytical solution with the proposed model. Results differ by less than 30 ppm. The differenceis mainly due to switch � value, which is not taken into account in the simplified model.

Fig. 20. Reference bus impedance analysis with the simplified voltage-mode�� model.

phenomenon can significantly affect linearity. Using the equiv-alent circuit in Fig. 18, it is possible to rapidly evaluate the im-pact of reference connection impedances on the output of theDAC. Fig. 20 shows the DAC equivalent circuit, including par-asitic impedances and modeling typical positive andnegative reference distribution buses. Since the current iscode dependent, the apparent reference voltage as can beseen by the DAC is also code dependent. This creates linearityerrors. Fig. 21 shows the simulated impact of reference connec-tions on integral nonlinearity (INL) and DNL, as obtained withthe simulation of a detailed netlist simulation, as well as with thesimple equivalent model analysis result. Both results are verysimilar. They show that only 1- parasitic resistance betweenthe reference source and the DAC would be responsible for al-most 2 LSB INL and 1.5 LSB DNL errors in the modeled 16-bitDAC. Note that the parasitic resistance on reference inputs isalso responsible for gain errors, not plotted here, but which canalso be obtained with the proposed model.

5) Resistors: In our model, the simplified impedance expres-sions and output voltage expression are based on ideal equalresistors. In reality, however, resistors are subject to variationsinherent to fluctuations of any fabrication processes, and theirvalue can be modulated by temperature and voltage state. Takingall these effects into consideration still requires simulations witha complete detailed netlist of the DAC.

6) Switches: The switches of voltage-mode DACs areSPDT devices connecting input branches to either the positive ornegative reference potential. This wide operating voltage rangesets constraints on the switch design. Our proposed model doesnot take into account switch parasitic resistance which

should either be minimized or well compensated. Note that, inthe voltage-mode configuration, the switches are placed at theDAC inputs and separated from the output by the re-sistors, thus providing some shielding of the output from theswitching glitches.

Appendix II lists the bit values creating situations of max-imum/minimum input impedances and current values.

V. CURRENT-MODE MODEL CONSIDERATION

As for the voltage mode, the current-mode model (cf. Fig. 2)can be very useful for fast simulation. Although it is a high-level model that depicts accurately the DAC behavior in manysituations, it also shows some limitations due to the fact that itignores significant circuit details. Note that the expression ofoutput current in terms of resistance ratio derived in [7] can beused in place of the ideal current source to considerresistance mismatches. The following are some considerationsto be aware of when using the current-mode model shown inFig. 2.

1) Output Nodes: The current-mode ladder featurestwo current outputs, between which the input current is dividedin a proportion dictated by the digital input code: It is a cur-rent steering circuit. However, Zurada’s current-mode equiva-lent circuit only models one output and assumes the other isgrounded. Although grounding one of the outputs is probablythe most common situation, the converter is really a two-outputblock, and some simulations require the DAC to be consideredas such. In these cases, the model is not valid. For example,the model cannot be used to analyze accurately a current-mode

DAC with the complementary output tied to the groundthrough a resistor nor can it take into consideration any varyingvoltage found on that same output.

2) Input Impedance: Contrary to voltage mode, the inputimpedance of current-mode DACs is not modified by thedigital input code. In this situation, the current drawn from thereference input is constant, and the input voltage drop throughthe input connection parasitic resistances will only impact thegain error but not linearity. This relaxes the constraint on ref-erence distribution path design and also allows gain adjustmentwith the addition of an input resistor, as shown in Fig. 22. Whenthe DAC output is not grounded or virtually grounded with an



Fig. 21. Voltage-mode �� reference connection impedance impact on INL and DNL (type-A segmentation,� � ��,� � �, � � � V, � � ��, and� � � � � �). (a) Detailed netlist simulation results. (b) Simplified model analytical results.

Fig. 22. Gain adjustment resistor addition �� in current-mode��DAC.

Fig. 23. Fourteen-bit current-mode �� DAC.

op amp, the controlled current source present at the input sideof the model allows taking into consideration the output voltageeffect on the input current. Note again that the model assumesa grounded complementary output and does not have the abilityto adjust the input current with the output voltage found on acomplementary output.

3) Output Impedance: Contrary to voltage mode, the outputimpedance of current-mode DACs is code dependent.This impacts the stabilization of the operational amplifier gen-erally found at the output of such a converter [10] and also putsconstraints on the output path design as any resistance presenton that path will degrade linearity. An observation of this degra-dation is reported in [7], where the authors have noted that theoutput wire resistance is a source of INL error. Controlling thisfactor becomes important when target resolution increases, andan illustration of this will be given in Section VI with actual chipmeasurements.

4) Resistors and Switches: As for voltage mode, resistorswere all considered ideal, and switches are ignored to ob-tain simple impedance expressions. Adequate switch sizing andcompensation options needed to make this valid can be found in[8] and [12]–[15].

VI. HIGH-RESOLUTION DAC CASE STUDY

A. Chip Implementation and First Results

Fig. 23 shows a 14-bit current-mode DAC chip fab-ricated in 0.25- m TSMC CMOS process and previously de-scribed in [5]. The three MSBs are thermoencoded, and segmen-tation is of type A [cf. Fig. 3(a)]. The remaining 11 bits controlthe binary weighted currents generated with stages. Theunit resistance value is 50 k , and all resistors can be individ-ually and precisely adjusted by laser trimming: This trimmingis done with laser-diffused resistors [16], allowing the cancella-tion of any significant mismatches found after fabrication. Thisallows trimming away significant DNLs, which, in turn, is ex-pected to result in a very low INL performance.

Fig. 24(a) shows the typical linearity curves as measured onthe first prototype version of the chip and before any trimmingoperation. Fig. 24(b) shows the corresponding linearity curvesobtained if the most significant mismatches affecting the resistorladder are removed: The INL is not improved by mismatch can-cellation.

B. Analysis and Design Correction

The analysis of the prototype showed that parasitic resistorsof output buses combined with the code-dependent outputimpedance were responsible for the limited INL capability ofthe chip. Indeed, these buses, made very long to collect allDAC output currents coming out of all branches, hada parasitic resistance reaching almost 8 from one end to theother. The effect of these buses can be obtained with a completesimulation when including parasitic elements, but extractingall parasitic resistors for simulations is usually not possiblebecause of the excessive number of nodes added to the originalnetlist. A more practical solution (which also requires somehuman expertise) is to include only the sensitive parasitic ele-ments: in this case, the output bus resistors. Fig. 25(a) shows thelinearity curves of the DAC, as simulated using the equivalentmodel proposed, with a reference bus resistors added, as shown



Fig. 24. Linearity curves as measured on the first DAC prototype, (a) before any trimming and (b) after most significant mismatch correction.

Fig. 25. Linearity curves of the (a) first prototype and (b) improved DAC circuit as obtained with a fast simulation using the simplified DAC model.

Fig. 26. Linearity curves as measured on the improved DAC prototype, (a) before any trimming and (b) after trimming.

in Fig. 20. Note that this simulation gives a good approximationof the chip result (cf. Fig. 24), although the bus resistors areprobably a bad model of the bus layout solution and neitherswitch resistance nor resistor mismatch is considered.

The layout of this chip was later modified to reduce the outputpath resistance down to approximately 1 . Again, using theequivalent model, the expected typical linearity curves can becomputed and are shown in Fig. 25(b). Fig. 26 shows the lin-earity curves measured on the improved prototype chip [5]. Al-though the output impedance effect can still be observed intrimmed curves, nonlinearities are now dominated by mismatcherrors which can be trimmed out to reduce the INL down to0.6 LSB.

VII. CONCLUSION

Expressions of output and input impedances have beenderived to extend Zurada and Goodman’s current-modeequivalent circuit to segmented architectures. A new model hasalso been proposed for the voltage-mode designs. Expressionshave again been derived to fit segmented architectures as well.Simulation and chip measurements have shown that thesemodels can offer an accurate representation for fast simula-tion or higher level analysis. This is certainly a benefit foraccurate system simulation in the trend for higher integration.These models were used to demonstrate the importance ofconsidering the network impedance when designing high-res-



TABLE IBINARY VOLTAGE-MODE SPECIAL CODES

TABLE IISEGMENTED (A OR B) VOLTAGE-MODE SPECIAL CODES

TABLE IIIBINARY CURRENT-MODE SPECIAL CODES

TABLE IVSEGMENTED (A OR B) CURRENT-MODE SPECIAL CODES

olution DACs. The measurements of a trimmable 14-bit DACchip were compared to the model simulation results to showhow the code-dependent output impedance prevents reachingthe targeted resolution.

APPENDIX IUSEFUL PROPERTIES

Several expressions were simplified using the followinggeometric series property:

(53)

In particular, (11), (21), and (38) were obtained withand . Another useful version of this property is obtainedwhen and

(54)

APPENDIX IISPECIAL CASES

Several input codes are of special interest since theycreate configurations of extreme impedance and/or current.

Tables I–IV list some of these codes1 for the differentconfigurations modeled.

Using the provided code values, limits to models and equa-tions can be generated with a symbolic computing software. Forexample, the maximum input current of an -bit voltage-modebinary ladder is

(55)

Although it is interesting to note that the expression is closedfor any value of , the formula is not simple and becomes evenmore complex for segmented cases. For this reason, we haveonly provided the list of special codes. With these tables andthe equations that compose the model, the interested reader cangenerate any needed result.

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[15] H. Asazawa, “D/A converter for minimizing nonlinear error,” U.S.Patent 5 119 095, Jun. 2, 1992.

[16] M. Meunier, Y. Gagnon, Y. Savaria, A. Lacourse, and M. Cadotte, “Anovel laser trimming technique for microelectronics,” Appl. Surf. Sci.,vol. 186, no. 1–4, pp. 52–56, Jan. 2002.

1Separation between thermometer and binary bits is shown, but all bits aregiven binary encoded.



David Marche received the B.Ing., M.Sc.A., andPh.D. degrees in electrical engineering from theÉcole Polytechnique de Montréal, Montréal, QC,Canada, in 1993, 1996, and 2009, respectively.

As a Software Engineer and an Analog Designerwith OPMAXX, Portland, OR, and later with LTRIMTechnologies, Laval, QC, Canada, he has participatedin the design of several analog and mixed-signal in-tegrated circuits and in the development of optimiza-tion and test software. Since 2007, he has been withthe École Polytechnique de Montréal, Montréal, QC,

Canada.

Yvon Savaria (S’77–M’86–SM’97–F’08) receivedthe B.Ing. and M.Sc.A. degrees in electrical engi-neering from the École Polytechnique de Montréal,Montréal, QC, Canada, in 1980 and 1982, respec-tively, and the Ph.D. degree in electrical engineeringfrom McGill University, Montreal, QC, Canada, in1985.

Since 1985, he has been with the École Polytech-nique de Montréal, where he is currently a Professorand the Chairman of the Department of ElectricalEngineering. He has been working as a Consultant or

was sponsored for carrying out research by CNRC, Design Workshop, Dolphin,

DREO, Genesis, Gennum, Hyperchip, LTRIM, Miranda, MiroTech, Nortel,Octasic, PMC-Sierra, Technocap, Tundra, and VXP. He has carried out workin several areas related to microelectronic circuits and microsystems, such astesting, verification, validation, clocking methods, defect and fault tolerance,high-speed interconnects and circuit design techniques, computer-aided design(CAD) methods, reconfigurable computing and applications of microelec-tronics to telecommunications, image processing, video processing, radarsignal processing, and digital signal processing acceleration. He has authoredor coauthored 80 journal papers and 322 conference papers. He holds 15patents. He was the thesis advisor of 122 graduate students who completedtheir studies.

Dr. Savaria is a member of the Regroupement Stratégique en Microélectron-ique du Québec of the Ordre des Ingénieurs du Québec. He is the chairman ofthe Board of CMC Microsystems. He was the program cochairman of the 1992edition and the chairman of the 1993 edition of the IEEE Workshop on Defectand Fault Tolerance in VLSI Systems. He was the program cochairman of Ap-plication-Specific Systems, Architecture and Processors (ASAP) 2006 and thegeneral cochairman of ASAP 2007. He was awarded with a Canada ResearchChair on the design and architectures of advanced microelectronic systems in2001. He wasalso the recipient of a Synergy Award of the Natural Sciences andEngineering Research Council of Canada in 2006.


modeling r-2r segmented-ladder dacs

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