modeling stress, defect evolution, and junction leakage...victor moroz october 8th, 2008 nccavs...
TRANSCRIPT
![Page 1: Modeling Stress, Defect Evolution, and Junction Leakage...Victor Moroz October 8th, 2008 NCCAVS JUNCTION TECHNOLOGY GROUP 2 Outline 3 Outline 4 Stress in Transistors in Production](https://reader033.vdocument.in/reader033/viewer/2022060903/609f1fdc33acb12463646123/html5/thumbnails/1.jpg)
1
Modeling Stress, Defect
Evolution, and Junction Leakage
Victor Moroz
October 8th, 2008
NCCAVSJUNCTION TECHNOLOGY GROUP
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2
Outline
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Outline
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Stress in Transistors in Production
0
0.5
1
1.5
2
2.5
3
1990 1995 2000 2005 2010
Str
ess,
GP
a
Year
Channel stress
Max residual stresss
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5
Stress in Transistors in Production
0
0.5
1
1.5
2
2.5
3
1990 1995 2000 2005 2010
Str
ess,
GP
a
Year
Channel stress
Max residual stresss
Scaling
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6
Stress in Transistors in Production
0
0.5
1
1.5
2
2.5
3
1990 1995 2000 2005 2010
Str
ess,
GP
a
Year
Channel stress
Max residual stresss
Scaling
SiGe-induced
(PMOS only,
NMOS stress
is ~half)
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7
Stress in Transistors in Production
0
0.5
1
1.5
2
2.5
3
1990 1995 2000 2005 2010
Str
ess,
GP
a
Year
Channel stress
Max residual stresss
Scaling
SiGe-induced
Silicide
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8
Stress in Transistors in Production
0
0.5
1
1.5
2
2.5
3
1990 1995 2000 2005 2010
Str
ess,
GP
a
Year
Channel stress
Max residual stresss
Scaling
SiGe-induced
Silicide
Inside
SiGe
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9
Outline
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10
Stress in Transistors in Production
0
0.5
1
1.5
2
2.5
3
3.5
1990 1995 2000 2005 2010
Str
ess,
GP
a
Year
Channel stress
Max residual stresss
Peak stress
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11
Stress in Transistors in Production
0
0.5
1
1.5
2
2.5
3
3.5
1990 1995 2000 2005 2010
Str
ess,
GP
a
Year
Channel stress
Max residual stresss
Peak stress
![Page 12: Modeling Stress, Defect Evolution, and Junction Leakage...Victor Moroz October 8th, 2008 NCCAVS JUNCTION TECHNOLOGY GROUP 2 Outline 3 Outline 4 Stress in Transistors in Production](https://reader033.vdocument.in/reader033/viewer/2022060903/609f1fdc33acb12463646123/html5/thumbnails/12.jpg)
12
Stress in Transistors in Production
0
0.5
1
1.5
2
2.5
3
3.5
1990 1995 2000 2005 2010
Str
ess,
GP
a
Year
Channel stress
Max residual stresss
Peak stress
SiGe
+thermal mismatch
+temperature gradient
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13
Outline
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• Mechanical strength of Si is ~5 GPa
• Defect formation happens much earlier
– Depends on impurities like oxygen
– Depends on thermal history
• Some stresses are more damaging than
others, like shear stress in a dislocation
slip plane
• Tensile stress is worse than compressive
How Much Stress Is Too Much?
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15
Stress in Transistors in Production
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
1990 1995 2000 2005 2010
Str
ess,
GP
a
Year
Channel stress
Max residual stresss
Peak stress
![Page 16: Modeling Stress, Defect Evolution, and Junction Leakage...Victor Moroz October 8th, 2008 NCCAVS JUNCTION TECHNOLOGY GROUP 2 Outline 3 Outline 4 Stress in Transistors in Production](https://reader033.vdocument.in/reader033/viewer/2022060903/609f1fdc33acb12463646123/html5/thumbnails/16.jpg)
16
Numonyx: STI-Induced Dislocations
Polignano et al, TED’07
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eSiGe eSiGe
cCESL
Stress-Induced Dislocations
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18
Outline
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19
Junction Leakage vs Bandgap
J/Jref = exp(ΔEg/2kT)
Thermal generation-recombination current exponentially
decreases with band gap increase:
The band gap in turn depends on stress and impurities like Ge
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20
Outline
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21
Band Structure vs Stress (Simplified)
EC
EV
Stress
Compressive TensileZero
NominalShrank
Shrank
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22
Bandgap vs Stress
1.06
1.07
1.08
1.09
1.1
1.11
1.12
1.13
-1000 -500 0 500 1000
Si B
an
d G
ap
, eV
Hydrostatic Pressure, MPa
Close to symmetric,
~50 mV/GPa
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23
Example: S/D Junction Inside 20% SiGe
• Compressive stress shrinks Eg by 90mV
• 20% germanium adds another 80mV
• Total band gap narrowing is 80mV + 90mV
= 170mV
• This increases junction leakage by ~30x
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24
Stress Impact on Junction Leakage
100 200 300
Depth 1
Depth 2
Depth 3
Off-s
tate
Cu
rre
nt [A
/µm
)
On-state Current (µA/µm)
10-7
10-8
10-9
10-10
10-11
10-12
SiGe
Depth
1
-12
-8
Lo
g(B
ulk
Le
aka
ge
Cu
rre
nt [A
])
-10
-6
SiGe
Depth
2
SiGe
Depth
3
Ref
Depth 1 < Depth 2 < Depth 3
Junction
outside SiGe
Junction
inside SiGe
Nouri et al, IEDM’04
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25
Junction Leakage: Typical Observation
What happened?
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
0 1000 2000 3000
Ju
ncti
on
Leakag
e C
urr
en
t, A
Stress, MPa
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26
Junction Leakage: Typical Observation
Stress-induced
bandgap
narrowing
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
0 1000 2000 3000
Ju
ncti
on
Leakag
e C
urr
en
t, A
Stress, MPa
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27
Junction Leakage: Typical Observation
Stress-induced
bandgap
narrowing
Stress-induced
defects relax
the stress
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
0 1000 2000 3000
Ju
ncti
on
Leakag
e C
urr
en
t, A
Stress, MPa
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28
Junction Leakage: Alternative Behavior
What happened?
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
0 1000 2000 3000
Ju
ncti
on
Leakag
e C
urr
en
t, A
Stress, MPa
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29
Junction Leakage: Alternative Behavior
What happened?
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
0 1000 2000 3000
Ju
ncti
on
Leakag
e C
urr
en
t, A
Stress, MPa
Stress-induced
defects create
deep energy levels
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30
Harmful Stress and Defects
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31
Safe Dislocations
TEM image of a 50nm SOI
transistor from AMD Athlon 64
2700 chip, showing harmless
dislocations under the spacers
Source: Chipworks
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32
Safe Dislocations
TEM image of a 42nm tran-
sistor from Intel’s Presler chip,
showing harmless dislocations
under the spacers
Source: Chipworks
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33
Safe Dislocations
TEM image of a 55nm transis-
tor from Matsushita’s DVD SOC
chip, showing dislocations under
the silicide that are apparently
harmless
Source: Chipworks
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34
Outline
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35
3D Stress Modeling for Typical W’s
2D is not enough.
All typical Xtors
require 3D
Moroz et al, Solid State Technology’04
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36
2 Inverters in Different Neighborhoods
Stand-alone
Surrounded
by neighbors
0.6 mm
1.8
mm
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37
Stress-Induced Mobility Variation (%)
Things to notice:
•pMOS difference 17%
•nMOS difference 9%
•nMOS/pMOS ratio
difference 26%
Mobility change
-27
+3
-18
-14
Stand-alone Dense n’hood
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-40
-20
0
20
40
60
80
100
120
140
160
180
dense sparse
Str
es
s-i
nd
uc
ed
mo
bil
ity c
ha
ng
e (
%)
Adjacent layout
nMOS
pMOS
pMOS + SiGe
The Importance of Neighborhood
Introduction of eSiGe S/D:
• Improves hole mobility
• Reverses the trend
• Still exhibits layout sensitivity-44%
-9%
+17%
Increased harmful compressive
STI stress
Increased beneficial
compressive STI stress
Beneficial strong compressive
SiGe stress is partially relaxed
by relatively soft STI
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39
Competition of Two Ring Oscillators
0.0
0.2
0.4
0.6
0.8
1.0
25 35 45 55Time (ps)
Sta
ge 3
Ou
tpu
t (V
)Sparse
Dense
The ring oscillator in dense layout neighbor-
hood outruns the one in sparse layout by >10%
Moroz et al, ISQED’06
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40
Outline
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41
Non-Si Materials
• Qualitatively, the impact of stress on non-silicon semiconductors is
similar to silicon.
• One important difference is that silicon is the most rigid of
semiconductors of interest. That means that the same applied force
leads to the larger strain in non-silicon semiconductors compared to
silicon. For example, silicon has Youngs modulus of 165 GPa,
whereas GaAs has Youngs modulus of only 85 GPa. The same
stress corresponds to twice as big of a strain in GaAs compared to
Si.
• The reason this is important is that it is strain that determines the
band structure of a semiconductor.
• The flip side of the lower Youngs modulus is that the material is not
as strong and suffers from defects and cracks at a lower stress
level.
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42
Conclusions
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43
The Upcoming Book
These and other related effects are
described in the book coming out
on October 17, 2008