modern vlsi design 2e: chapter4 copyright 1998 prentice hall ptr
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![Page 1: Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR](https://reader035.vdocument.in/reader035/viewer/2022062516/56649d415503460f94a1c80d/html5/thumbnails/1.jpg)
Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Fanout
Fanout adds capacitance.
source
sink
sink
sink
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Ways to drive large fanout
Increase sizes of driver transistors. Must take into account rules for driving large loads.
Add intermediate buffers. This may require/allow restructuring of the logic.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Buffers
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Wire capacitance
Use layers with lower capacitance. Redesign layout to reduce length of wires
with excessive delay.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Placement and wire capacitance
unbalanced load
more balanced
dvr
g1
g2
g3
g4
dvr
g1
g2
g3
g4
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Path delay
Combinational network delay is measured over paths through network.
Can trace a causality chain from inputs to worst-case output.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Critical path
Critical path = path which creates longest delay.
Can trace transitions which cause delays that are elements of the critical delay path.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Delay model
Nodes represent gates. Assign delays to edges - signal may have
different delay to different sinks. Lump gate and wire delay into a single
value.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Critical path through delay graph
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Reducing critical path length
To reduce circuit delay, must speed up the critical patheducing delay off the path doesn’t help.
There may be more than one path of the same delay. Must speed up all equivalent paths to speed up circuit.
Must speed up cutset through critical path.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Transistor sizing
Effective resistance depends on transistor W/L - less delay means wider transistors.
For equal pullup and pulldown times, W/L of pullup and pulldown obey Kp/Kn.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Logic transformations
Can rewrite by using subexpressions. Flattening logic increases gate fanin. Logic rewrites may affect gate placement.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
False paths
Logic gates are not simple nodes - some input changes don’t cause output changes.
A false path is a path which cannot be exercised due to Boolean gate conditions.
False paths cause pessimistic delay estimates.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
False path example
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Logic optimization
Logic synthesis programs transform Boolean expressions into logic gate networks in a particular library.
Optimization goals: minimize area, meet delay constraint.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Technology-independent optimizations
Works on Boolean expression equivalent. Estimates size based on number of literals. Uses factorization, resubstitution, minimizat
ion, etc. to optimize logic. Technology-independent phase uses simple
delay models.
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Modern VLSI Design 2e: Chapter4 Copyright 1998 Prentice Hall PTR
Technology-dependent optimizations
Maps Boolean expressions into a particular cell library.
Mapping may take into account area, delay. May perform some optimizations on
addition to simple mapping. Allows more accurate delay models.