modern vlsi design 4e: chapter 4 copyright 2008 wayne wolf topics n interconnect design. n...
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Topics
Interconnect design. Crosstalk. Power optimization.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Interconnect
Even assuming logic structure is fixed, we can:– change wire topology;– resize wires;– add buffers;– size transistors.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Multipoint nets
Two-point nets are easy to design. Multipoint nets are harder:
– How do we connect all the pins using two-point connections?
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Styles of wiring trees
source
sink 2
sink 1
Spanning tree
Steiner treeSteiner point
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Sized Steiner tree
source
sink 2
sink 1
Feeds both branches
Smaller currents in each branch
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Buffer insertion in wiring trees
More complex than placing buffers along a transmission line:– complex topology;– unbalanced trees;– differing timing requirements at the leaves.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Van Ginneken algorithm
Given:– placements of sources and sinks;– routing of wiring tree.
Place buffers within tree to minimize the departure time at the source to meet all the sink arrival times:– Tsource = min i (T i -D i)
– T i = arrival time at node i, D i = delay to node I.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Delay calculation
Use Elmore model to compute delay along path from source to sink.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Recursive delay calculation
Recursively compute Elmore delay through the tree.– Start at sinks, work back to source.– r, c are unit resistance/capacitance of wire.
– Lk is total capacitive load of subtree rooted at node k.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Modifying the tree
Add a wire of length l at node k:– Tk’ = Tk - r/Lk - 0.5rcl.
– Lk’ = Lk + cl.
Buffer node k:– Tk’ = Tk - Dbuf - Rbuf Lk.
– Lk’ = Cbuf.
Join two subtrees m and n at node k:– Tk’ = (Tm , Tn).
– Lk’ = Lm + Ln.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Crosstalk
Capacitive coupling introduces crosstalk. Crosstalk slows down signals to static gates,
can cause hard errors in storage nodes. Crosstalk can be controlled by
methodological and optimization techniques.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Interleaved power/ground
VDD
VSS
VDD
VSS
VDD
VSS
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Twizzled wires
a
b
c
d
b
d
a
c
a
b
c
d
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Coupling and crosstalk
Crosstalk current depends on capacitance, voltage ramp.
w1 w2
Cc
ic
t
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Crosstalk analysis
Assume worst-case voltage swings, signal slopes.
Measure coupling capacitance based on geometrical alignment/overlap.
Some nodes are particularly sensitive to crosstalk:– dynamic;– asynchronous.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Coupling situations
sig1a x r
better worse
bus[0]
bus[1]
bus[2]
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Layer-to-layer coupling
Long parallel runs on adjacent layers are also bad.
bus[0]
siga
SiO2
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Methodological solutions
Add ground wires between signal wires:– coupling to VSS, a stable signal, dominates;
– can use VSS to distribute power, so long as power line is relatively stable.
Extreme case—add ground plane. Costs an entire layer, may be overkill.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Ground wires
VSS
sig1
VSS
sig2
VSS
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Crosstalk and signal routing
Can route wires to minimize required adjacency regions.
Take advantage of natural holes in routing areas to decouple signals.
Minimizes need for ground signals.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Assumptions
Take into account coupling only to wires in adjacent tracks.
Ignore coupling of vertical wires. Assume that coupling/crosstalk is
proportional to adjacency length.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Crosstalk example
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Crosstalk analysis
Want to estimate delays induced by crosstalk.
Effect of coupling capacitance Cc depends on relative transitions.– Aggressor changes, victim does not: Cc.
– Aggressor, victim move in opposite directions: 2Cc.
– Aggressor, victim move in same direction: 0.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Crosstalk analysis, cont’d.
Coupling effects depend on relative switching time of nets.
Must use iterative algorithm to solve for coupling capacitances and delays.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Power optimization
Glitches cause unnecessary power consumption.
Logic network design helps control power consumption:– minimizing capacitance;– eliminating unnecessary glitches.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Glitching example
Gate network:
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Glitching example behavior
NOR gate produces 0 output at beginning and end:– beginning: bottom input is 1;– end: NAND output is 1;
Difference in delay between application of primary inputs and generation of new NAND output causes glitch.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Adder chain glitching
bad good
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Explanation
Unbalanced chain has signals arriving at different times at each adder.
A glitch downstream propagates all the way upstream.
Balanced tree introduces multiple glitches simultaneously, reducing total glitch activity.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Signal probabilities
Glitching behavior can be characterized by signal probabilities.
Transition probabilities can be computed from signal probabilities if clock cycles are assumed to be independent.
Some primary inputs may have non-standard signal probabilities— control signal may be activated only occasionally.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Delay-independent probabilities
Compute output probabilities of primitive functions:– PNOT = 1 - Pin
– POR = 1 - Pi)
– PAND = Pi
Can compute output probabilities of reconvergent fanout-free networks by traversing tree.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Delay-dependent probabilities
More accurate estimation of glitching. Glitch accuracy depends on accuracy of delay model.
Can use simulation-style algorithms to propagate glitches.
Can use statistical models coupled with delay models.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Power estimation tools
Power estimator approximates power consumption from:– gate network;– primary input transition probabilities;– capacitive loading.
May be switch/logic simulation based or use statistical models.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Factorization for low power
Proper factorization reduces glitching.
bad good
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Factorization techniques
In example, a has high transition probability, b and c low probabilities.
Reduce number of logic levels through which high-probability signals must travel in order to reduce propagation of glitches.
Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Layout for low power
Place and route to minimize capacitance of nodes with high glitching activity.
Feed back wiring capacitance values to power analysis for better estimates.