Module 1

Process steps in IC fabrication: Silicon wafer preparation-Diffusion of impuritiesphysical mechanism-ion implantation- Annealing process- Oxidation processlithography-Chemical Vapour Deposition -epitaxial growth –reactorsmetallization-patterning-wire bonding –packaging

PROCESS OF IC FABRICATION

Various processing steps used to fabricate ICs are:

1. Diffusion (ion implantation)2. Oxidation3. Photolithography4. Chemical vapour deposition (including epitaxy)5. Metallization

The fabrication of IC starts with single-crystal Si wafers and the above steps are used to produce ICs. The ICs are in wafer form with tens, hundreds or even thousands of discrete devices on the same Si wafer. The wafer is then divided up to obtain the individual dice or chips. These chips are encapsulated or packaged with a wide variety of packages and packaging methods.

Growth of Si crystals

Commonly available natural sources of Si are silica and silicates. 95% of semiconductor devices are made up of Si. The raw material for the preparation of Si-crystal is Electronics-grade Si (EGS), which is a polycrystalline material of high purity. The major impurities in the EGS are boron, carbon and residual donors.

Production of EGS is a multistep process as shown below.

A metallurgical-grade silicon (MGS) is produced in an arc furnace, which is charged with quartzite, a relatively pure form of sand (SiO2), and carbon in the form of coal, coke, and wood chips. The MGS is drawn off and solidified at a purity of 98%. This is still not suitable for manufacturing semiconductor devices. The overall reaction in the furnace being SiC+Si02 Si + SiO+ CO (solid) (solid) (liquid) (gas) (gas)

• The MGS is purverized mechanically and reacted with anhydrous hydrogen chloride (HCl) to form Trichlorosilane (SiHCl3), according to the reaction :

Si + 3 HC1 SiHCl3+H2 (solid) (gas) (gas) (gas)

• The reaction takes place at a nominal temperature of 300°C using a catalyst. Here silicon tetrachloride (SiCI4) and the chlorides of impurities are formed. At this point the purification process occurs. Trichlorosilane is a liquid at room temperature, because its boiling point is 32°C. Therefore purification is done by fractional distillation. The purified SiHCl3 is subjected to chemical vapour deposition (CVD)to be discussed later. The chemical reaction is a hydrogen reduction of SiHCl3.

2SiHC13+ 2H2 2Si+ 6HCl

This reaction takes place in a CVD reactor in which a resistance heated Si-rod serves as nucleation point for the deposition of Si. This results rods of EGS which are up to 0.2m or more in diameter and several meter in length.

Crystal structure

EGS are not suitable for IC manufacturing, because it does not represent an ideal crystal due to the following reasons:

i) The Si wafer formed from EGS has finite boundaries; thus atoms at the surfaces are incompletely bonded.

ii) The atoms are displaced from their ideal locations by thermal agitation.iii) The crystals have the following defects:

1. Point defect2. Line defect (dislocation)3. Area or planar defect4. Volume defect

These defects may be the influence of optical, electrical and mechanical properties of Si

Crystal Growing

Growing crystals involves a phase change form solid, liquid, or gas phases to crystalline solid phase. Most commonly used crystal growth process is Czochralski growth process.

The number of sites on the face of the crystal determines the speed of growth and the specifics of heat transfer at the interface. The following figure shows the transport process and temperature gradients involved.

The heat transfer condition about the interface can be modeled by the following equation.

H dm/dt + σl dT/dxM AM= σs dT/dxN AN……………………………. (1)

where H is the latent heat of fusion, dm/dt: is the mass solidification rate, T is the temperature, σl

and σs are the thermal conductivities of the liquid and solid respectively, dT/dxM and dT/dxN are the thermal gradients at point M and N which are near the interface in the liquid and solid, respectively, and AM and AN are the areas of the isotherms at positionsM and N respectively. From Eq. (1) the maximum pull rate of a crystal under the condition of zero thermal gradient in the melt, i.e., dT/dxM = 0, can be obtained. The maximum pull rate is given by

Pmax = σs dT/Hd dxN……………………………. (2) Pmax is the maximum pull rate or pull speed and d is the density of solid silicon. The pull rate affects the impurities going into the crystal during growth and decides the defects generated. Generally, when the temperature gradient in the melt is small, the heat transferred to the crystal is the latent heat of fusion. Therefore, the pull rate generally varies inversely with the diameter. In practice the pull rates obtained are 30 to 50% slower than the maximum theoretical values.

Crystal growth apparatus

This apparatus is used for growing single crystal highly refined EGS. The apparatus is shown below.

The apparatus consists i) Furnace

ii) Crystal pulling mechanism

iii) Ambient control facilityiv) Control system

The furnace consists crucible, susceptor and a rotational mechanism, heating element and power supply. The crucible is most important, since it contains melt. It should be chemically uncreative with molten Si. Materials like Si3Ni4 and fused silica (SiO2) are used for crucible, because

they have high melting point. The susceptor is used to support the silica crucible and provide better thermal conditions. Usually graphite is used for this, because of its high temperature properties and provide prevent from contamination of the crystal from impurities. There is chamber housing for the furnace, which provides easy access to the furnace components for maintenance and cleaning. The furnace structure must be prevent contamination from the atmosphere and the hottest parts in the apparatus are water cooled. There is also insulation between heater and chamber wall. To melt RF heating (for small melt sizes) or resistance heating (for large) is used.

The crystal-pulling mechanism consists of seed shaft, rotation mechanism and seed chunk. This mechanism controls two parameters of growth process: pull rate and crystal rotation. This should have minimum vibration and great precision. The seed holder and pulling mechanism must have a precise orientation perpendicular to the melt source. The crystal leaves from the furnace through a purge tube, where ambient gas is directed along the surface of the crystal to cool it. From the purge tube, crystal enters to an upper chamber.

The ambient control of the apparatus consist gas source, flow control, purge tube, and exhaust system. The crystal growth must be conducted in inert gas or vacuum, it is because i) the hot graphite parts must be protected from oxygen to prevent erosion and ii) the gas around the process should not react with the molten Si.

The control system consists microprocessors, sensors, and outputs and provides control of process parameters like temperature, crystal diameter, pull rate and rotation speed.

For the growth process, the polycrystalline Si (EGS) with appropriate amount of dopants is put into the crucible, which is then placed inside the furnace. Then it is heated to temperature excess to Si melting point 1420oC. A small single-crystal rod of Si called seed crystal is then dipped into the Si melt. The conduction of heat up the seed crystal produce a reduction in the temperature of the melt in contact with the seed crystal to slightly below the Si melting point. The Si will then freeze into the end of the seed crystal and the seed crystal is slowly pulled up out of the melt with a controlled rate, then the Si on the end of the seed crystal have a crystallographic nature. Also both of the crucible and seed crystal must rotate in opposite direction during the crystal pulling process, thus crystalline ingots of circular cross section is produced.

Si wafer preparation

Ingot trimming and slicing: The extreme opposite ends f Si ingot are cut off and the ingot surface is ground to produce constant and exact diameter D, which is usually 100, 125 or 150mm. A crystallographic orientation flat is also ground along the length of the ingot. The ingot is then sliced using larger diameter stainless steel saw blade made up of diamonds at the cutting edge. This will produce circular slices or wafers about 600 to 1000μm thickness as shown below.

The orientation flat is useful as reference plane for various device fabrication process.

Wafer polishing: The surface of Si wafer is damaged during slicing, so number of polishing steps is essential for the following reasons:

1) To remove the damaged Si from the swan surface.2) To produce a highly planar surface, which is essential for photo-lithographic process.3) To improve parallel.

Si wafer is of 600 to 1000μm thickness and is quite rough. So it is lapped to remove saw marks and to produce a flat surface. The initial surface damage is of the order of 75μm and after lapping it is still exists to a depth of around 15μm. This damage is removed by chemical etching using acid mixture consists nitric acid to oxide the surface.

The wafer is then polished mechanically on a wheel to mirror like finish, using Al abrasive powders of decreasing grit size. There still exists a surface damage of around 2μm deep. Finally it is removed by an additional chemical etching stage. Usually one side of the wafer is final mirror like finish and other side is being given just a lapping operation to ensure flatness and parallelism. After polishing wafers are thoroughly cleaned and dried and are ready for the various processing steps.

Wafer Cleaning: Different stages of wafer cleaning are:

Chemical cleaning: Cleaning of wafers is used to remove organic films, heavy metals and particulates. Commonly used mixtures are NH4OH-H2O2, HCl-H2O2 and H2SO4-H2O2. All these solutions are efficient to remove metallic impurities, but HCl-H2O2 is best

Gettering Treatment: These are used to remove the impurities, which are transition group elements, located at interstitial or substitutional lattice sites. Various technology for gettering treatment are:

i. Intentionally damaging the back surface of the wafer using mechanical abrasion methods.

ii. Damage created in wafer using focused heat beam obtained from Nd-YAG laser.

iii. Intrinsic gattering: in which an impurity oxygen cause defect generation.

Diffusion of Impurities

This process is using to form junction, i.e., transition of p type semiconductor to n type semiconductor. This operation is performed at high temperature furnace and the impurity atoms are introduced onto the surface of a Si wafer and diffuse into the lattice because of their tendency to move from regions of high concentration to low concentration. The temperature is usually 900 to 1100oC

Physical mechanisms of diffusion: There are mainly two types of physical mechanisms by which the impurities can diffuse into lattice. They are:

i) Substitutional Diffusion: At high temperature most of the atoms move from there lattice site, leaving vacancies into which impurity can move. The impurity thus diffuses by this type of vacancy motion and occupies lattice position in the crystal after it is cooled. Here impurity atoms diffuse by moving from lattice site to a neighboring one by substituting for a Si atom as shown below.

This mechanism is applicable to diffusants like boron, phosphorus, and arsenic, because they are too big to fit into interstices or voids and they enter the Si crystal by substituting Si atom.

ii) Interstitial Diffusion: Here the impurity atom does not replace the Si atom, but it moves into the interstitial voids in the lattice. The main type of impurities diffusing by such mechanism is Gold, Copper and nickel, because they do not substitute Si atom. Diffusion of impurity atom by this mechanism is shown below.

Fick’s Laws governing diffusion process

The diffusion rate of impurities into the semiconductor lattice depends on the following:

i) Diffusion mechanismii) Temperatureiii) Physical property of lattice environmentiv) Concentration gradient of impuritiesv) Geometry of parent semiconductor

The behavior of diffusion particles is governed by Fick’s law, which is solved for appropriate boundary conditions, gives rise to various dopant distributions called profiles.

Fick assumed that in a dilute liquid or gaseous solution, in the absence of convection, the transfer of solute atoms per unit area in one-dimensional flow can be described by the following equation F=-D∂N(x,t)/ ∂x-----(3) , where F is the rate of transfer of solute atom per unit area or the diffusion flux density, N is the concentration of solute atoms and x is the axis in the direction of solute flow, t is the diffusion time and the D is diffusion constant.. The above equation is called Fick’s first law and states that the local rate of transfer of solute per unit area per unit time is proportional to the concentration gradient of the solute. The proportionality constant is diffusion constant and –ve sign appears due to opposite direction of matter flow and concentration gradient.

Fick’s first law is applicable to dopant impurities used in Si. Generally doping impurities are not charged, nor they move in an electric field, so the drift velocity associated with the above equation can be omitted

Fick's second Law of diffusion. The change of solute concentration with time must be the same as the local decrease of the diffusion flux, in the absence of a source or a sink. This follows from the law of conservation of matter. Therefore we can write down the following equation ∂N(x,t)/ ∂t =-∂F(x,t)/ ∂x………………….………………………..(4) Substituting Eq. (4) into Eq. (3), yields

∂N(x,t)/ ∂t =∂/∂x(D∂N(x,t)/ ∂x)……………………………….(5) When the concentration of the solute is low, the diffusion constant at a given temperature can be considered as a constant, and Eq. (5) becomes ∂N(x,t)/ ∂t =D∂2 N(x,t)/ ∂x2)……………………………….(6) Eq. (4.6) is often referred to as Fick's second Law of diffusion.

The solution of this equation gives the impurity concentration, N, at some distance x from the origin, usually the surface of the semiconductor, as shown in Fig. 7.

Applying boundary conditions on equation for Fick’s second law of diffusion there are two types of solution and that solutions provides two types of impurity distribution (diffusion profiles) namely:

i) Constant source (erfc) diffusion Such type impurity distribution, the impurity concentration at the

semiconductor surface is maintained at a constant level throughout the diffusion cycle. i.e , N(o, t) = constant = Ns . Then the solution of Fick’s second law in the plane x = 0, from Ns to zero with the boundary conditions N(o, t) = constant = Ns and N(x,t) = 0

the resulting concentration at any given point within the silicon material can be written as N(x,t)=Nserfc(x/2√Dt)

. The graphs of this function are shown below.

By this profile the surface concentration is always held at Ns and falls to lower value away from the surface. This can be varied according to the diffusion time. This profile is always used in the fabrication of monolithic ICs for the isolation and the emitter diffusion.

i) Limited source diffusion (Gaussian diffusion) Here a predetermined amount of impurity is introduced into the crystal.

The diffusion takes place by two steps:

i. Pre-deposition step: In this a fixed number of impurity atoms are deposited on the Si wafer during a short time.

ii. Drive-in-step: Here the impurity source is turned off and the amount of impurities already deposited during first step are allowed to diffuse into Si wafer.

With this type of diffusion the depth of penetration of impurities during the pre-deposition step is negligible as compared with the final junction depth after drive-in-step. Thus initial impurity

concentration N(x,o) is assumed as a delta function on the surface. Applying boundary condition to Fick’s second law and solving the equation, the solution

N(x, t)= (Q/A /√πDt) е- x2/ 4Dt, where Q/A is the initial deposited quantity of impurity concentration. This impurity profile is called Gaussian distribution and its plots are shown below.

These type of distribution is mainly used for forming linear graded junction and moderately high sheet resistivity required areas. Usually transistor base regions are fabricated by this distribution.

Diffusion Systems

All types of diffusion system use diffusion furnace. It is a resistance-heated tube of length 2 to 3m with hollow opening into which a quartz tube about 100, 150mm in diameter is placed as shown below.

The temperature of the furnace is kept about 1000oC and it can be controlled very accurately to maintain a uniform temperature over a hot zone along the furnace.. The Si wafers to be processed are stacked up vertically into the sots in a quartz carrier inserted into the furnace tube.

Diffusion of p-type impurity: Boron is always used as acceptor impurity in Si. B2H2 (Diborane) is a gaseous source of boron and can be directly introduced into the furnace. A number of other gases are directed into the furnace and the principle gas flow in the furnace is N2, which acts as relatively inert gas acts carrier gas. A small amount of oxygen and very small amount of a source of boron will make rest of the gas flow. This is shown below.

The following reactions will be occurring simultaneously at the surface of the Si wafers

Si+02 Si02, (silica glass) 2B2H6+ 302 B2O3 (boron glass) +6H2

This process is the chemical vapour deposition (CVD) of a glassy layer on the Si surface, which is mixture of silica glass (SiO2) and boron glass called borosilica glass (BSG). It is a viscous liquid at diffusion temperature and the boron atoms move around easily.

Boron Tribromide (BBr3) source is used as liquid source and in this case a controlled flow of carrier gas (N2) is bubbled through BBr3 with oxygen again produces BSG at the surfaces of the wafers due to the following reaction 4BBr3+302 ----B2O3+2Br2

Diffusion of n-type impurities: For phosphorus diffusion, phosphine (PH3) and phosphorus oxychloride (POCl3) can be used. In the case of POCl3 the following reactions occurring at the Si wafer.

Si+02- SiO2 (silica glass) 4 POCl3 + 302- 2P205 + 6Cl2(Phosphorus glass)

This will result a production of glassy layer on the silicon wafer that is the mixture of silica glass and phosphorus glass called phosphorosilica glass (PSG), which is viscous liquid at diffusion temperature. Thus, phosphorus concentration is maintained at the surface of the Si wafer as a solid solubility. The rest of the process for the diffusion is similar to p-type diffusion.

Ion Implantation

This is an alternative to deposition diffusion and is used to produce a shallow surface region of dopant atoms deposited into the Si wafer. Here a beam of impurity ions is accelerated to kinetic energies in the range of several tens of kV and is directed to the surface of the Si. When the ions enter into the crystal, they give up energy to the lattice in collisions and finally come to rest at some average penetration depth called projected range expressed in μm. This range depends on impurity and its implantation energy and in the range few hundred Ao to 1μm.The distribution of impurity by this method is Gaussian distribution.

The ion implantation system is shown below.

A gas containing the desired impurity is ionized within ion source. The ions are generated and repelled from their source in a diverging beam that is focused before it passes through a mass separator that directs only ions of the desired species through a narrow aperture. A lens focus the beam which then passes through an accelerator that brings the ions to their require energy before they strike the target and become implanted in the exposed area of the Si wafers. The accelerating voltages ranges from 20kV to 250kV.

The repetitive scanning in a raster pattern provides uniform doping in the wafer surface. The target chamber commonly includes automatic wafer handling facilities to speed up the process of implanting many wafers per hour.

Properties of Ion Implantation: The depth of penetration of any ion will increase with accelerating voltage and the penetration depth will generally ranges from 0.1 to 1μm. The following table show various projected range Rp, for various accelerating voltages for boron and phosphorus ions

Energy (kV)

Rp of boron (μm)

Rp of phosphorus (μm)

20 0.067 0.026100 0.30 0.123200 0.52 0.254300 0.70 0.386

Impurity distribution of implanted ions as a function of distance x from the Si surface will be a Gaussian distribution is given by N (x) = Np exp ( - (x- Rp) 2 /2Δ Rp2)

where x = distance into substrate from surface Rp = projected range Δ Rp = straggle (standard deviation) of the projected range Np = peak concentration of implanted ions.

The ion implantation profile is shown below.

Annealing Process:

After ions implanted they are in interstitial position in Si crystal structure and the surface region where implantation takes place will be heavily damaged due to the high velocity ion beam. These problems can be solved by annealing process. This problem involves the heating of the wafers to some temperature, usually in the range of 1000oC for 30 minutes time.

There are laser beam and electron beam annealing employed, such techniques surface region of the wafer is heated and re-crystallized. The ion implantation process is often followed by a annealing process, which is a conventional type drive-in diffusion.

Advantages of ion implantation:

It provide more precise control over the density of dopants deposited on the wafer and hence sheet resistance. Precise quantity of impurity can be introduced into the Si wafer. The ion implantation can be done at relatively low temperature.

Oxidation Process

SiO2 layer is one of the important layer in the IC fabrication technology. Oxidation process is used to for SiO2 layer on the Si wafer. The uses of this layer are:

1. It acts as a diffusion mask to provide selective diffusion into Si wafer.2. It is used as surface passivation, ie creating SiO2 layer on the surface acts as a protection of

the junction from the moisture and other atmospheric contaminants.3. It serves as insulator on the wafer surface.4. It acts as active gate electrode for the MOS device structure.5. It is used to isolate one device from other.6. It provide electrical isolation of multilevel metallization used in VLSI.

Oxide layer growth and its properties: SiO2 layer is formed by thermal oxidation at high temperature in a stream of oxygen. The reaction is Si + 02-SiO2 (solid). The oxidation furnace is used for this reaction and it is similar to diffusion furnace. The thickness of the oxide layer depends on the temperature of the furnace, length of the oxidation time and the flow rate of the oxygen.

The rate of oxidation can be increased by adding water to the oxygen source in the furnace.

Si +2H2O SiO2 +2H2

The time and temperature required to produce a particular layer thickness are obtained from empirically determined design curves and are shown below.

The initial growth rate of the oxide is limited by the chemical reaction takes place. After the

first 100 to 300 of oxide has been produced and the growth rate will be limited by the rate of the diffusion of oxidant through the oxide layer as shown below.

The rate of oxide layer will be inversely proportional to the thickness of the layer, then

dx /dt = C/ x, where x is the oxide thickness and C is a constant of proportionality. Simplifying this equation and solving it we get x =√2Ct. , ie the thickness of oxide layer is proportional to time

The rate of oxide growth using H2O as the oxidant will be four times faster than the rate obtained with O2.

Lithography

PN junction on the Si wafer is usually formed in a selected location. Thus oxide layer must be removed from that area and this process is performed with lithography. Then various windows are cut through the oxide layer and diffusion can take place with these areas.

Lithography is the technique used for making art from a flat, special stone or metal plate. For IC manufacturing it is analogous to the lithography of the art world. Here an art corresponding to the circuits are formed in microscopically.

There are different types of lithography in IC fabrication:

1. Photolithography2. Electron-beam lithography3. X-ray lithography and4. Ion-beam lithography

Photolithographic Process Steps:

1. Photoresist application (Spinning):A drop of light sensitive liquid called photoresist is applied to the centre of

the oxidized Si wafer that is held in a vacuum chuck. The wafer is then accelerated rapidly to a rotational velocity in the range of 3000 to 7000 RPM for some 30 to 60 seconds. Thus the solution spreads in a thin, uniform coat and spins off excess liquid.

The thickness of these coat ranges 5000 to 10000 shown below.

2. Prebake:The Si wafers coated with photoresist are put into an oven at about 80 oC for

30 to 60 minutes to drive off the solvents in the photoresist and to harden it into semisolid film.

3. Alignment and exposure:The coated wafer is then placed in an apparatus called a mask aligner in very

close proximity (about 25 to 125μm) to a photo mask. The relative position of the photomasks are adjusted such that the photomask is correctly lined up with reference marks.

The photomask is a glass plate of 125mm square and about 2mm thick. It has a photographic emulsion pattern on one side. The pattern has clear and opaque areas. After proper alignment the wafer is brought into direct contact with photomask.

A highly collimated UV ray is then turned on the areas of the Si wafer that are not covered by the opaque areas of the photomask are exposed to UV radiation as shown below.

4. Development:There are two types of photoresist: negative and positive photoresist. In –ve

photoresist the area of the photoresist that are exposed to the UV radiation become polymerized. This polymerization process increases the length of reaction and makes the resist tougher and it will become insoluble in the developer solution. The resultant photoresist pattern after this process will be a replication of photomask pattern and a typical example is show below.

In opposite type process, exposure of UV ray results depolymerization of the photoresist. And it makes the exposed areas of the resist readily soluble in the developer solution.

5. Postbake:After development and rinsing the wafers are usually given a postbake in an oven at

a temperature of about 150oC for 30 to 60 minutes to toughen the remaining resist on the wafer.

6. Oxide Etching:The remaining resist is hardened and acts as a convenient mask through which the

oxide layer can be etched away to expose areas of semiconductor underneath. These areas are ready for impurity diffusion.

For etching oxide the wafers are immersed with a hydrofluoric acid solution. This solution will etch SiO2 but will not attack the underlying Si, nor it will attack the photoresist layer to any extent. The wafers are exposed to the etching solution long enough to remove the SiO2 completely in the areas of the wafer that are not covered by the photoresist as shown below.

7. Photoresist Stripping:After oxide etching, the remaining resist is finally removed or stripped off with a

mixture of sulphuric acid and hydrogen peroxide and with the help of abrasion process. Finally washing and drying completes the required window in the oxide layer as shown below and the Si wafer is ready for next diffusion.

Photoresist materials:

To get good result high quality photoresist materials are required. The principal constituents of a photoresist solution is a polymer, a sensitizer and a suitable solvent system. Polyvinyl cinnamate is usually used as polymer and it have excellent film forming and coating properties. Carbonyl compounds are used as sensitizers and it absorbs energy and initiates chemical changes in the resist. Aliphetic esters are used as solvents and are used to keep the polymers in solution are mixture of organic liquids. Some other solvents are thinners and developers.

Characteristics of good photoresist are uniform film formation, good adhesion to the substrate, resolution and resistance to wet and dry etch process.

Photomask fabrication

Photolithography is used to produce windows in the oxide layer of the Si wafer, for this photomask is required. Using these masks ICs are fabricated by batch processing.

The number of wafers processed at one time is called lot size and may vary between 20 to 200 wafers. The number of ICs per wafer is function of the size of the IC and the diameter of the wafer. The IC chip is in square shape and the wafer is in circular, then the Number of chips (dice) = π r2 / A —1.77 d/√A , where D is the diameter of wafer, A is area of the chip and r is the radius of the wafer.

The pattern for the mask is designed from the circuit layout. VLSI circuit contains thousands to several hundred thousand components, and the mask layout is formed with the help of computer. The mask determines the location of all windows in the oxide layer. A typical mask making is shown below.

Master mask is first prepared and is the replica of the basic portion of the final mask associated with one individual IC, but it is 250 x full size. These large size avoid large tolerance errors. This master mask is reduced to 25 x photographic reduction and finally reduced to 10 x reduction.

Various printing technologies used in photolithography are:

1. Contact printing:Photomask is pressed against the resist contact wafer and exposed

by UV ray. It provide a resolution of less than 1μm line width.

2. Proximity printing:It is also called shadow printing, there is a gap between mask and

wafer in the range of 20 to 50μm. One of the advantage is longer life of mask. By this method mask and wafer are both placed in an equipment called projection aligner. The resolution of this process is usually 2 to 4μm.

3. Projection printing:Here image is projected via a system of lenses onto the wafer. The

mask can be used number of times and resolution is higher than proximity printing.

Fine Line Lithography

Electron-beam lithography

It is a type of fine-line lithography, provides better resolution than photolithography. This process uses small wavelength of 10-50keV electron beam. The resolution of electron beam lithography system is not limited by diffraction, but by electron scattering in the resist and by the various aberration of the electron optics.

The formation of bonds between polymer chain when –ve resist is exposed to electron beam. However, bond breaking occurs in +ve resist when it is exposed.

Typical resists used for this process are PMMA (Polymethyl methacrylate) and MP-2440.

Projection printing and proximity printing are used for electron beam lithography. For photo masks, flat surface of thin layer of chrome must be etched with a liquid etchant, the resist thickness of 0.2 to 0.4μm is used.

X-ray lithography

It has the better resolution than electron-beam type. Here diffraction effects are reduced by short wavelength of X-ray. In this X-ray source illuminates the mask, which casts shadow on to a resist covered wafer. The mask and resist material for X-ray lithography are mainly determined by the absorption spectra of these materials in the X-ray region.

or diceElectron resist can also be referred as X-ray resist. The absorption coefficient

//

//

where

Proximity printing is always used for this type lithography. It is shown below.

The blanking of shadow can be evaluated by // //

Where //

//

The mask for X-ray lithography consists an absorber on a transmissive membrane substrate. The absorber is usually gold which have large // //

The transmissive membrane substrate is a polymer such as polymide and polyethylene teraphthalate, Si, SiC, Si3N4, Al2O3 and a Si3N4 – SiO2 – Si3N4 sandwich structure.

Ion- beam lithography.

It provides higher resolution using an ion-beam, which has less scattering. Also resists are more sensitive to ions than electrons. One of the advantage of ion-beam is that there is the possibility of wafer processing without resists if it is used to implant or sputter selected areas of the wafer.

It employs a scanning focused- beam or a masked-beam. The source of ionized material is gas-surrounding a pointed tungsten tip or a liquid metal that flows to the tip from a reservoir. Electrostatic lens is used for focusing ion beams.

Comparison of various lithography

Photolithography: Simple, convienient and reasonably high throughput. The practical resolution is limited by 0.5μm or lower. The main limitation of photo-lithography resolution are: 1) due to optical material, 2) small depth of focus and 3) the difficulty to obtain low diffraction imaging over a large field.

Electron-beam lithography: The system with high throughput are not needed for custom ICs. They require fine definition, flexibility etc. These system is complicated and low throughput.

X-ray and ion-beam lithography are better for high volume production of advanced circuits with dimensions beyond the optical limit.

Chemical Vapour Deposition (CVD)

It is used to deposit solid material onto a heated substrate via decomposition or chemical reaction of compounds contained in the gas passing over the substrate. Materials like Silicon nitride, SiO2, polycrystalline Si and single crystal Si are formed by CVD. This process is also called epitaxial layer deposition or Vapour-phase epitaxy.

In this process, materials to be deposited enter a reaction chamber in the gaseous or vapour phase and react near the surface of the substrates. The chemical reactors produce atoms or molecules that are deposited on the substrate surface.

Different materials that can be deposited via CVD are:

1. Si epitaxial layer on a single crystal Si substrate (homo epitaxy)2. Si epitaxial layer on a sapphire substrate (hetro epitaxy)3. SiO2 deposition4. Si nitride deposition

Epitaxial deposition

Epitaxy means the arrangement of atoms upon a crystal substrate, so that the resultant structure is an exact extension of the substrate crystal structure. The results of epitaxial deposition and crystal growing is same, but the difference is: in epitaxy a thin film of single crystal Si is grown from a vapour phase, but in crystal growing a single crystal is grown from the liquid phase. The epitaxial process does not involve no portion of the system at a temperature any where near the melting point of the system.