Module I

Overview of Computer Architecture and Organization

Multiple Bus Hierarchies

• Two Approaches :1. Traditional Bus Architecture2. High Performance Architecture

Traditional Bus Architecture• Local Bus: Connects processor to cache and

local devices• Cache is connected to system bus to connect

with main memory• Expansion Bus Interface buffers data transfer

between system bus and I/O controllers.– Network to WANs and LANs– SCSI for peripherals– Serial Port for printers and scanners– Modem for Internet

Traditional Bus Architecture

High Performance Architecture• Local bus connects processor to cache• System bus connects cache to main memory• Cache controller is integrated to bridge that

connects to high speed bus• High speed bus supports– High Speed LANs – Video & Graphic Controllers– SCSI and FireWire(P1394)

• Low Speed devices are connected via expansion bus

High Performance Architecture

SCSI

Fire Wire

Elements of Bus Design

• The parameters that classify buses are1. Bus Types2. Method of Arbitration3. Timing4. Bus Width5. Data Transfer Type

Bus Types

• Dedicated and Multiplexed• Dedicated – Bus line is permanently assigned to a function– It uses multiple buses – Adv: High throughput and less bus contention– Disadv: increased size and cost

Bus Types

• Multiplexed:– Address and data may be transmitted over same

set of lines– Adv: use of few lines saves space and cost– Disadv: complex circuitry is needed and less

performance

Method of Arbitration

• Centralized and Distributed• Centralized :– A single hardware called bus controller allocates

time on bus• Distributed :– Each module contains access control logic and

modules act together to share the bus

Timing

• Synchronous and Asynchronous• Synchronous:– Occurrence of events are controlled by clock– All events start at the beginning of clock cycle– Adv: Simple to implement and test– Disadv: less flexible – cannot take advantage of

device performance

Synchronous

Timing

• Asynchronous:– Occurrence of one event on bus follows the

occurrence of previous event– Adv: fast and slow device can share the bus– Disadv: Difficult to implement

Asynchronous

Bus Width

• Address Bus and Data Bus• Address Bus:– Wider address bus greater range of locations

• Data Bus– Wider data bus greater number of bits per unit

time

Data Transfer Type

Multiplexed Address/Data Bus

Dedicated Address/Data Bus

Read Modify Write

• Read followed by immediate write to the same address

• Used to protect shared memory resources

Read After Write

• Write is immediately followed by Read• It is for checking purpose

Block Data Transfer

• One address cycle is followed by n data cycles