RESEARCH NEWS

JAN-FEB 2008 | VOLUME 11 | NUMBER 1-2 9

Improving the performance of

transistors by downscaling is much

less straightforward with organic

thin-film transistors (TFTs) because

it has to be balanced by maintaining

compatibility with large-area flexible

electronics manufacturing. Graphical

printing processes have poor resolution

compared with the lithographic

methods used for Si integrated circuits.

Now scientists from the University

of Cambridge, UK, have used a

self-aligned printing technique to

downscale printed TFTs [Noh et al.,

Nat. Nanotechnol. (2007) doi:10.1038/

nnano.2007.365]. The features that

control transistor switching speed

– channel length, gate dielectric

thickness, and gate to source/drain

overlap – can be shrunk from tens of

microns down to 100–400 nm.

“Our work shows that in this way it

is possible to realize printed TFTs that

can, in principle, operate at megahertz

frequencies,” says Henning Sirringhaus.

Switching speeds are improved by

several orders of magnitude, devices

can operate below 5 V, and carrier

mobilities are ~0.1–0.2 cm2V–1s–1.

“This is the best performance reported

to date for inkjet printed polymer

transistors,” the researchers claim.

The self-aligned gate process

developed by the group is key. The

surface of the first printed electrode

is modified with a hydrophobic

monolayer that repels the ink of the

second electrode, resulting in a small

but controlled gap between the two

electrodes. When a photosensitive

dielectric on the top side is illuminated

though the back of the substrate, the

two electrodes, the source and drain,

act as a shadow mask for positioning

the gate electrode.

“The method they are using is simple

and can be easily scaled up,” says

Zhenan Bao from Stanford University.

Pauline Rigby

Moore’s law for organic TFTsELECTRONIC MATERIALS

Conducting in the graphene orchestraELECTRONIC MATERIALS

Graphene’s unique band structure has motivated much

research toward a unified theory of graphene carrier

transport. One of the outstanding mysteries, however,

is graphene’s residual conductivity. With a report by

researchers at the University of Maryland, a fuller

theoretical picture shows that the concentration of

unavoidable impurities explains graphene’s transport

properties [Adam et al., Proc. Nat. Acad. Sci. USA (2007)

104, 18392].

Until now, the theory was that near the Dirac point

(a singularity in the band structure where the density

of states vanishes and carriers are massless Dirac

fermions) graphene’s charge carrier transport is ballistic

and the conductivity minimum is a fixed quantity.

But the new research shows unequivocally that the

conductivity is a function of the concentration of

impurities in the sample.

“Since we knew that the exfoliation technique used

to obtain graphene involves extracting graphene onto

a SiO2 substrate and that the high density mobility

is limited by dirt in the substrate and not in the

graphene itself, we wanted to see if this would also

explain the residual minimum conductivity,” says

Shaffique Adam. “The basic idea is that the disorder

induces carriers that in turn screen the impurities

making them appear weaker.” Their theoretical

framework to determine the residual density of carriers

quantitatively solves the mystery of the residual

conductivity.

The work shows that the mobility below room

temperature in current samples is set entirely by

disorder in the substrate. Thus, changing the substrate

or reducing impurities is the clear road to higher

mobility – a promising idea for future graphene-based

transistors. “By going to cleaner samples or suspended

graphene,” says Adam, “we anticipate a whole host

of new interesting physics that is the subject of our

current research.”

D. Jason Palmer

A schematic of the model where charged impurities

in the SiO2 substrate give rise to puddles of electrons

and holes whose carrier density needs to be calculated

self-consistently. The researchers demonstrate that

this residual density is responsible for the minimum

conductivity. Also shown is a comparison between

theory and experiment for a representative sample,

where the only fitting parameter is the impurity

concentration.

Surface layers allow accurate doping

A novel process for implanting dopant atoms in

semiconductor materials with nanometer precision could be

an enabling technology for the continued miniaturization of

Si microelectronics [Ho et al., Nat. Mater. (2007) doi:10.1038/

nmat2058].

As transistors shrink in size, it becomes increasingly important

to control their doping reliably, particularly for ultrashallow

source and drain regions. Ion implantation and solid source

diffusion are the standard methods for implanting dopants

in semiconductors, but at small scales these methods are

not sufficiently precise to put dopants exactly where they

are needed. In addition, ion implantation induces significant

crystal damage.

Now a team of electrical engineers led by Ali Javey at

the University of California, Berkeley, has developed an

alternative doping method based on surface chemistry. “We

have developed a novel and generic approach for controlled

nanoscale doping of semiconductors by utilizing the rich

surface chemistry of crystalline materials combined with a

self-limiting monolayer formation reaction,” explains Javey.

They use dopant-containing reagent molecules that form

well-ordered, covalently-bonded thin films on the surface

of Si. The molecules are then driven into the Si by rapidly

annealing the samples at high temperature. By controlling the

heat treatment conditions, it is possible to control the depth

to which the dopants penetrate. “The process is highly generic

for both planar and nonplanar (such as nanowire) structures

with the dopant dose and profile being well controlled

through molecular precursor design and the thermal annealing

conditions,” says Javey.

The new approach addresses a critical need for a robust

nanoscale doping technique that can avoid the limitations of

conventional methods, claim the researchers.

“The method was demonstrated for standard Si substrates as

well as Si-on-insulator and bottom-up nanowire materials, and

can be readily implemented to other types of semiconductor

substrate with the appropriate surface chemistry,” says Javey.

Pauline Rigby

ELECTRONIC MATERIALS

MT111_2p7_15.indd 9MT111_2p7_15.indd 9 10/12/2007 15:59:4310/12/2007 15:59:43