more moore and more than moore meeting for 3dhfsion/tin10 hfsion/tin vt tuning by gate stack...

INSTITUTE FOR ENERGY EFFICIENCYSanta Barbara, California, December 2, 2011

More MOORE and MORE THAN MOORE MEETING FOR 3D

S.Deleonibus, CEA-LETI, MINATEC Campus,

17 rue des Martyrs , 38054 Grenoble Cedex 09 France.

Tel : 33 (0)4 38 78 59 73 ; Fax: 33 (0)4 38 78 51 83; email: [email protected]

© CEA. All rights reserved

S.Deleonibus CEA-LETI December 2011 | 2

CEA – LETI organization

15,000 Employees

3 billion € Budget

15,000 Employees

3 billion € Budget

French Nuclear Agency

Technological Research

Fundamental Research

Electronuclear Energy Res.

Defense

3,200 Researchers3,200 Researchers

New technology for Energy &

Nanomaterials

Software oriented system

Micro NanoTechnology &

integration in System

1,600 Researchers1,600 Researchers

* Grenoble

* Grenoble

* Saclay



LETI: Mission and Focus

Basic ResearchPublications

Applied ResearchPatents

Pilot LinePrototypes

Mass ProductionProducts

� A single mission :

Create innovation

& transfer it to industry

� A clear focus :

µ-nanotechnologies, with critical mass in Si

Advanced devices for new applications



LETI in a few numbers - 2010

Microelectronics

Microsystems

Biology & Health

Photonics

Wireless & Smart devices

Energy & Environment

200 and 300mm Si capabities8,000 m² clean roomsContinuous operation

1 600 researchers1 000 permanent LETI staff

300 M€ budget> 73% from contract~ 40 M€ CapEx

350 new patents in 2010Portfolio > 1,500 patents32 start-ups



Since 2005: A complete set of research platforms…

interacting daily with R & D platforms worldwide (ST Crolles, IBM Albany, …)

CEA LETI (1600 CEA researchers)collaborating

in MINATEC campus (>4000 researchers)

300mmCMOS Integration

& adv. modules

200mm‘CMOS’ new concepts

& Beyond CMOS

More Than Moore200mm

NanoscaleCharacterization

Design

MicroTechsfor bio

Education

Incubation

Advanced Research 100-200mm



Budget : 1 Billion€with investment : 150 M€

10 000 researchers10 000 students

Micro Nano-Technologies

NouvellesTechnologiespour l’Energie

BioTechnologies

Sciencesde base

Sciencesde base



BioTechnologies

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Micro/nano-Technologies

New EnergyTechnologiesBio-Technologies

Basic research



BioTechnologies

Sciencesde base

Sciencesde base



BioTechnologies

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base



Basic research



BioTechnologies

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base



BioTechnologies

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base



Basic research



BioTechnologies

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base



BioTechnologies

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base

Sciencesde base



Basic research

> 5 000 publications/year> 500 patents/year



Outline

• Introduction : Trends and Hot Topics in Nanoelectronics

• Nanoelectronics scaling and use of the 3rddimension to continue Moore’s law.

• Interfacing the Multiphysics World (More Than Moore) thanks to functional diversification

•Building new systems and their packaging with a 3D tool box at a wafer level.

• Conclusions



Semiconductor Market applications successive waves

Source : Semico Research Corp. May 2004 IPI Report

Quality of life, Social, Environment, Health, Energy, …associated to ICT



� Currently, 3 % of the world-wide energy is consumed by the ICT

infrastructure

� which causes about 2 % of the world-wide CO2 emissions

� comparable to the world-wide CO2 emissions by airplanes or ¼ of the world-

wide CO2 emissions by cars

� ICT: 10% of electrical energy in industrialized nations� 900 Bill.. kWh / year = Central and South Americas

� The transmitted data volume increases approximately by a factor of 10

every 5 years

Source: TU Dresden

Ecological Footprint of ICTs reported by Intergovernmental Panel Climate Change(IPCC)

For ICTs, keep in mind: P = Pstat + Pdyn Pstat= VddxIoff and Pdyn=CVdd

2 f



Scaling: a success story…thanks to innovation

1,00E+00

1,00E+01

1,00E+02

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018

Date

Num

ber

oftr

ansi

stor

s pe

rch

ip

100µm

10µm

1µm

0,10µm

10 nm

Crit

ica

lDim

ensi

on

4004

8080

808680286

i386

i486Pentium

Pentium II

Pentium III

Pentium IV

Itanium

1k4k

16k

64k

256k

1M4M

16M

64M128M

256M512M

1G2G

4G

microp

roce

ssors

dynam

icmem

ories

(DRAM

)

contacts « plugs »(3 lev met)

vias « plugs »,CMP(4 lev met)

FSG(6 lev met)

damascene(5 lev met)

Cu (7 lev met)

Cu+H(M)SQ (9 lev met)

polymers+ALD (10 lev met)

ULK(11 lev met)

poly gate

polycide

1 billionOffice

PC

Main Frame

C.T.V.

VCRDefense

Home PC

Portable Internet

Convergence

10 millions

STI, salicide

DigitalCamera

HiK +metal gate

1,00E+00

1,00E+01

1,00E+02

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018

Date

Num

ber

oftr

ansi

stor

s pe

rch

ip

100µm

10µm

1µm

0,10µm

10 nm

Crit

ica

lDim

ensi

on

4004

8080

808680286

i386

i486Pentium

Pentium II

Pentium III

Pentium IV

Itanium

1k4k

16k

64k

256k

1M4M

16M

64M128M

256M512M

1G2G

4G

microp

roce

ssors

dynam

icmem

ories

(DRAM

)

contacts « plugs »(3 lev met)

vias « plugs »,CMP(4 lev met)

FSG(6 lev met)

damascene(5 lev met)

Cu (7 lev met)

Cu+H(M)SQ (9 lev met)

polymers+ALD (10 lev met)

ULK(11 lev met)

poly gate

polycide

1 billionOffice

PC

Main Frame

C.T.V.

VCRDefense

Home PC

Portable Internet

Convergence

10 millions

STI, salicide

DigitalCamera

HiK +metal gate

Moore’s law: 2Xdevices/year

Electronic Device Architectures for the Nano-CMOS EraFrom Ultimate CMOS Scaling to Beyond CMOS DevicesEditor: S.Deleonibus, Pan Stanford Publishing, Oct 2008



Three major product families(ITRS aware of CMOS scaling limits)

� High Performance (HP) t=CV/I� Connection to power network

� Low Operating Power (LOP)� Intermittent Nomadic Function

� Low Stand-by Power (LSTP) Pstat= VddxIoff� Permanent Nomadic Function

Nomadic consumer and professional products: largest market share continuously increasing

Pdyn=CVdd2 f

Ptot=Pstat+ Pdyn



« More, More than, Beyond Moore »

Tomorrow’s top added value markets

ITRS 2009 & 2011

High growth with ‘More than Moore’ technologies:they require expertise in all technical domains and in-

depth knowledge of the targeted markets



EUV (λ = 13.5nm)

• 60% reflectivity for several hundreds of Si / Mo stacksw roughness precision < 3Å

• Placement of mirror and mask

• Photoresist

from S.A. Campbell, The Science and Engineering of Microelectronic Fabrication, Oxford University Press 2001 Engineering Test Stand (VNL/EUV-LLC)

>100 M$ 100Wph !!



System made of 13,000 electron

beams working in parallel (MAPPER)

(1)Key numbers 22nm node:

HVM pre-alpha

#beams and data channels 13,000 110

Spotsize: 25 nm 35 nm

Beam current: 13 nA 0.3 nA

Datarate/channel 3.5 Gbs 20 MHz

Acceleration voltage 5 kV 5 kV

Nominal dose 30 µC/cm2 30 µC/cm2

Throughput @ nominal dose 10 wph 0.002 wph

Pixel size @ nominal dose 3.5nm 2.25 nm

Wafer movement Scanning Static

Electron source

Collimator lens

Aperture array

Beam Blanker array

Beam Deflector arrayProjection lens array

Condensor lens array

Beam Stop array

Electron source

Collimator lens

Aperture array

Beam Blanker array

Beam Deflector arrayProjection lens array

Condensor lens array

Beam Stop array



1 mMAPPER single column tool. Upgrade to

13,000 beam for 10WPH

Interface to track1 m

MAPPER single column tool. Upgrade to 13,000 beam for 10WPH

Interface to track

Interface to trackCluster 100WPH

System made of 13,000 electron

beams working in parallel (MAPPER)

(2)



Hot Topics in MOSFET technology� Introduction of HiK and metal gate allows continued scaling and relaxes

SiO2 gate leakage current related issues

- Ig added to SCE, DIBL, subthreshold leakage(LETI IEDM 2002, Intel IEDM 2005)

� Statistical dopant variability

- number of dopants in the active area decreases with scaling

- random distribution of channel dopants

Poisson’s law. Standard deviation:

S.Deleonibus et al. ESSDERC 1999

Major interest for LowDoped channels

21

=Volume

Ndopingσ

0.01

0.1

1

10

100

1000

104

0.01 0.1 1

σσ σσ N/N

Nom

bre

d'im

pure

tés

Lg (µm)

Statistical fluctuations of threshold voltage: 150 mV decayfor VT=200mV( Lg=25nm) !!



Outline





• Conclusions



32nm Low Power FDSOIUndoped channels

C.Fenouillet Beranger et al., IEDM 2007, VLSI Symp 2010

V.Barral et al., IEDM2007

VDD=1V Ioff=6pA/µm

0.248µm2 SNM (1.2V)=140mV 0.179µm2 SNM (1.2V)=230mV

6T SRAM

10 nm BOx8 nm TSi 10 nm BOx8 nm TSi

Range = ±4 Å!

0000

+5+5+5+5

----5555

1 9 17

25

33

41

49

57

65

73

81

89

97

105

113

121

129

137

Wafer #

-10

-5

0

5

10

SO

I Thi

ckne

ssD

evia

tion

to ta

rget

(Å

)SOI Thickness

Max

Mean

Min

XUT+/- 5 Å - SOI thickness deviation

1 9 17

25

33

41

49

57

65

73

81

89

97

105

113

121

129

137

Wafer #

-10

-5

0

5

10

SO

I Thi

ckne

ssD

evia

tion

to ta

rget

(Å

)SOI Thickness

Max

Mean

Min

XUT+/- 5 Å - SOI thickness deviation

300mm wafers



0.5

1

1.5

2

2.5

3

10 20 30 40 50 60

AV

t (m

V.u

m)

Gate length L (nm)

FinFETs

Planar FDSOI

Wfin

=10nm

UTBSOILETI

square : Vd=50mV

circle : Vd=1V

Wfin

=20nm

Wfin

=15nmW

fin=20nm

[14]

[13]

[1]

[12]

[13]

[15]

[15]

[16]

0

20

40

60

80

100

120

-105 -8

7-6

9-5

1-3

3-1

5 0 15 33 51 69 87 105

σ∆Vt=34.5mV

σVt=24.5mV

AVt=0.95mV.µm

Cou

nt

Vt shift ∆Vt (mV)

0

20

40

60

80

100

120

-105 -8

7-6

9-5

1-3

3-1

5 0 15 33 51 69 87 105

σ∆Vt=34.5mV

σVt=24.5mV

AVt=0.95mV.µm

Cou

nt

Vt shift ∆Vt (mV)

Best trade-off between VT variations and gate length scaling compared to bulk MOSFETs and FinFETs

L=25nmW=60nm

(σVt=σ∆Vt/√2 to compare measurements on pairs and on arrays of transistors in the literature)

O.WeberO.WeberO.WeberO.Weber et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008WL

AVtVt =σ

Record-high VT matching performance

FDSOI Undoped channels vs.FinFET



Multi VT solutions for SOC design

UTBOX + Back bias ; Gate stack engineering

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9

VTP (V)

VTN

(V)

HfO2/TiN

HfO2/Al 203/TiN

HfO2/Al203+/TiN

HfSiON/TiN5

HfSiON/Al 203+/TiN

HfSiON/TaAlN/TaN

HfSiON/TaN/TaAlN

HfSiON/TiN10

HfSiON/TiN

VT tuning by gate stack engineering

F.Andrieu et al. , VLSI 2010 Honolulu O.Faynot et al., IEDM 2010 San Francisco, invited talk

BOX = 10nm and VBB/ Ground PlaneN and PMOS: VT modulation of ≤200mV



Merits of FDSOI

Reachable Scaling rules(TSi, TBOx)

Delay vs. Power x Delay22% improvement/bulk (20nm)

O.Faynot et al, IEDM 2010, invited talk

L.Clavelier et al, IEDM 2010, invited talk



Thin Films Devices Relaxing optimization

scaling rule

by architecture

TSi= ¼ Lg

TSi= 1 to 2 Lg

Planar Double-gate

Planar or Finfet

Trigate/nanowire

tsource

Gate

tsource

Gate

Gate source

t

Gate

SourceL

w

ThinSOI

Bulk or thick SOI

TSi= ½ Lg

w

TSi=2.5nmStrain global & local

Lg=10nm

Barral et al. IEDM2007

Andrieu et al VLSI2006

Bernard et al. VLSI 2008

Dupré et al. IEDM 2008

Ernst et al. IEDM 2008

Jahan et al. VLSI2005

Vinet et al. EDL 2005

4.8 nm

3.4 nm

4.8 nm

3.4 nm



Si/Si0.8Ge0.2superlatticeepitaxy on SOI

Anisotropicetchingof these layers

Isotropicetchingof SiGe or Si

HfO2 (3nm)TiN (10nm)Poly-Si (200nm)

Gate depositions

S/D implantationSpacer formationActivation annealSalicidation

BOX

SiSiGe

SiSiGe

SiSiGeSiN

BOX BOX BOX

Gate

BOX

Gate

Gate etching

StandardBack-Endof-LineProcesses

500 nm

Source Drain

Gate

Top view of our device

Nanowires

Stacked Multichannels and MultiNanowires

« Top-Down » approach: device fabrication



0

1

2

3

4

5

6

0 1 2Layout width (a.u.)

Con

duct

ance

(a.

u.)

1 nanowire

planar

0

1

2

3

4

5

6


Con

duct

ance

(a.

u.)

1 nanowire

3 nanowires

0

1

2

3

4

5

6


Con

duct

ance

(a.

u.)

Finfet

Tunable width

See for details:T. Ernst et al, IEDM’06,’08 SSDM’07, ICIDT’08E. Bernard et al. VLSI’08, ESSDER’07C. Dupré et al, IEEE SOI Conference 07

Layout width1 2

vvv

0

1

2

3

4

5

6


Con

duct

ance

(a.

u.)

3 multichannels(MC)

W W

pitch

Design flexibility to tune the conductance


« Top-Down » approach




« Top-Down » approach

LETI: Dupré et al. IEDM 2008, San Francisco(CA)Ernst et al., Invited talk IEDM 2008, San Francisco(CA) Bernard et al, VLSI Symposium 2008 Honolulu K.Tachi et al., IEDM 2010, San Francisco

LETI top down approach for Low Power and High performance

10-12

10-10

10-8

10-6

10-4

10-2

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2D

rain

Cur

rent

ID (

A/µ

m)

Gate Voltage VG (V)

VD=1.2VV

D=1.2V

NWFET

P N

VD=50mV

ION

=6.5mA/µm

IOFF

=27nA/µm

SS=68mV/decDIBL=15mV/VV

T=0.5V

C.E.T.=1.8nm

VD=50mV

ION

=3.3mA/µm

IOFF

=0.5nA/µm

SS=65mV/decDIBL=7mV/VV

T=-0.62V

-CV/I outperforms Planar in loaded environment-Improved voltage gain (8GHz) wrt Planar-Gate separation possible -Transport properties in small nanowires



Pervasion of Nanowire technology

20nm

Poly SiSiO2Si3N4SiO2

3D NAND Flash Memories

Q=870 resonatorGauge width = 80 nm

15 nm oscillator

Zeptogram mass resolution

Mass detection

60

70

80

90

100

110

120

130

0 2000 4000 6000 8000 10000 12000

Time (s)

Con

duct

ance

(nS

)

pH 7

pH 4pH 5

pH 6

pH 3

pH 2

60

70

80

90

100

110

120

130

0 2000 4000 6000 8000 10000 12000

Time (s)

Con

duct

ance

(nS

)

pH 7

pH 4pH 5

pH 6

pH 3

pH 2

Metaln-doped Si Hole ElectronPassivation

Buffer solutionat pH<7

Buffer solutionat 7<pH<10

Buffer solutionat pH>10

Metaln-doped Si Hole ElectronPassivation

Buffer solutionat pH<7

Buffer solutionat 7<pH<10

Buffer solutionat pH>10

T.Ernst et al., IEDM 2008 Hubert et al., IEDM 2009

Chemical sensing



Tunnel FET Operation principle

N & P operation modes

� A single TFET device can operate

either in n or p channel mode

� N mode : VSD>0 & VGD>0

� P mode: VDS<0 & VGS<0

Source N+

Drain P+

Si

BOx

Gate

VD<0VS=0

VG<0 P mode

EFn EFp

VG > 0

V G =0

Source N+

VS>0V

Drain P+

VD=0

EC

EV

N mode

EFn EFp

VG < 0

V G =0

Source N+

VS=0V

Drain P+

VD<0

EC

EVP mode

Vth

VG

Log ID

IOFF

ideal switch

TFETMOSFET

Vth

VG

Log ID

IOFF

ideal switch

TFETMOSFET



SOI TFETs co-integrated with CMOSFETs

L=100nm; T=300K

•P mode: VDS<0 & VGS<0 •N mode: VSD>0 & VGD>0

Experimental demonstrationof Tunnel FET operations:

F.Mayer et al., IEDM 2008, C.LeRoyer et al., ULIS 2009

SOI TFET w. LDDn

BOx

S D

GP mode N mode

LDDHDD

50nm

NiSi NiSi

NiSi

Source

HDD

Gate

tSi

TiNHfO2

Poly

LG

1st spacer

2nd spacer

NiSi

SiN protection layer

Drain

LDDHDD

50nm

NiSi NiSi

NiSi

Source

HDD

Gate

tSi

TiNHfO2

Poly

LG

1st spacer

2nd spacer

NiSi

SiN protection layer

Drain



TFET for Ultra Low Power outperforms CMOS Offset/drain reduces Ioff(ambipolar current)

LETI: Mayer et al, IEDM 2008 Intel: U.E. Avci et al, VLSI Tech Symp 2011

EPFL: K. Boucart & A. M. Ionescu, ESSDERC 2006TUM: M. Schlosser et al. IEEE TED, Jan. 2009

Multigate improves Ion



CoCo--Integrating Heterogeneous orientation or materialsIntegrating Heterogeneous orientation or materials3D sequential process3D sequential process

(100)

First First heterogeneousheterogeneous orientation in 3D Si orientation in 3D Si sequentialsequential integrationintegrationEnabledEnabled by use of wafer by use of wafer bondingbonding by by keepingkeeping lowlow thermal budgetthermal budget

(110)

0.0 0.2 0.4 0.6 0.8 1.00

50

100pMOS

Reference TiN/ HfO2/ Si (100)

TiN/HfO2/Si(110) <100>

µe

ff,

ho

le (

cm

2/

V.s

)

Eeff (MV/cm)

P.Batude et al., Best student Paper Award, IEDM 2009

Ge

-4T SRAM - cold end process(bonding). Opportunities for other SC(Ge,III-V,...) - improved layout (40% area SRAM cell) -dynamically controlled VT:

improved RNM and SNM



Tsi 10 nm

Tsi ~10 nm

LG~50 nm

THFO2 2.5 nmTiN

LG~50 nm

Sequential 3D: towards nanoscale devices

First demonstration of 3D sequential structure down to LG 50 nm

P.Batude et al, 2011 VLSI Tech SympP.Batude et al., IEDM 2011, Invited talk



-2 -1 0 10.00

0.01

0.02

0.03

Top FET

Bottom FET

EOT= 1.45nm

EOT= 1.15nm

Capaci

tance

(F/µ

m2)

Gate Voltage VG(V)

BOX

HfOHfO22= 2.5nm= 2.5nm

Specific interest of low temperature process

The low temp. process (600°C) leads to a reduced EOTExplained by a reduction of interfacial oxide growthP.Batude et al, 2011 VLSI Tech Symp



~ 1 node gain with same design rules for Front end levels

topGeOI pMOS

2µm

nMOSGate

nMOSSource

pMOSGate

pMOSSource

bottomSOI nMOS

topGeOI pMOS

2µm

nMOSGate

nMOSSource

pMOSGate

pMOSSource

bottomSOI nMOS

Y-H. Son et al, VLSI 07, Jung et al, IEDM 2006

� Nanoelectronics & Photonicsapplications withSi-Ge Co-integration

�SRAM on top SOI logic, I/Os, analogon bottom bulk

�…

� SRAMs � FLASH

Sequential 3D: Potential and Demonstrated ApplicationsSequential 3D: Potential and Demonstrated Applicatio ns

High density logic applicationsHigh density logic applications Highly miniaturized Highly miniaturized CMOS imagers pixelsCMOS imagers pixels

Heterogeneous integrationHeterogeneous integration 3D memories3D memories

P. Coudrain et al, IEDM 08,

P. Batude et al,VLSI09

P.Batude et al., IEDM 2009, Best Student Paper Award



Logic + Stacked NVM: High bandwith, Reduced Power consumption,…Reconfigurabilityex: 32 nm node : > 1TB/s per 1mm2

Resistive switchesToshiba, Stanford Univ.: K.Abe et al, ICICDT 2008

3D-Xbar Memory stacked on Logic: towards NV

Logic

proven in 2D withMagnetic Tunnel Junctions, FeRAM Tohoku Univ., Hitachi: S.Matsunaga et al., Appl.Phys.Express(2008);

ROHM



More Moore

More thanMoore

Dual channel

xsSOI(N)/ Ge(P)

Advanced Devices and Systems

Future Vision

UTBOX

22nm 16nm

sSOI

2010 20132009 2014 2016

FDSOI

11nm

Std SOI

HP options

Nanowire

3D Nanowires

3D stacked devices3D

Logic

2012 2015

3D

III-V/Ge Heat sink C

Memory storing (SRAM, NVM) -

ZDRAM

3D stacked Mixed functions: NV Logic +sensors/polymers

X bar

3D Sensing/Actuation Bio, Mechanical & Chemical –(functionalization, NEMS, Single electronics, RF, opto,… )

Diversified Logic(association to Memory, Passives, Sensors,…)

Beyond CMOS (e-wavesconfinement, Spin electronics)

Si

FeFe

Si

FeFe

Low stress, HiD

Car

bon

elec

tron

ics(

CN

T,G

raph

ene,

Dia

mon

d)

Transfer to Industry Development

< 11nm



2.1x1060.721.4212.9554008500GaAs

4

2,7

5,0 @77K

0.6

0,60

0,86

vsat(107cm/s)

1x1012cm -2

(1x1015)

10-27

2x1016

6X1011

2x1013

2x1010

ni(cm-3)(m*em*h /m

2)T3/2

exp(-Eg/2kT)

0.1716.91.885077000InSb

Semi-metal

5.71000104-105104-105Graphene(CNT) sp2

5.7

13.9

16

11.9

Rel. K

5.47

0.74

0.66

1.12

Eg(eV)

200018002200C-Diamondsp3

530012 000InGa0.47As0.53

59.919003900Ge

1415001400Si

sth (W/m/K)µp (cm2V-1s-1)

µn

(cm2V-1s-1)Material

2.1x1060.721.4212.9554008500GaAs

4

2,7

5,0 @77K

0.6

0,60

0,86

vsat(107cm/s)

1x1012cm -2

(1x1015)

10-27

2x1016

6X1011

2x1013

2x1010

ni(cm-3)(m*em*h /m

2)T3/2

exp(-Eg/2kT)

0.1716.91.885077000InSb

Semi-metal

5.71000104-105104-105Graphene(CNT) sp2

5.7

13.9

16

11.9

Rel. K

5.47

0.74

0.66

1.12

Eg(eV)

200018002200C-Diamondsp3

530012 000InGa0.47As0.53

59.919003900Ge

1415001400Si

sth (W/m/K)µp (cm2V-1s-1)

µn

(cm2V-1s-1)Material

Highest µn but Worst µn/µp!!

Well established high quality material(>40yrs experience) Oxidizable !

Silicon compatible Available in all fabsGaAs lattice constant matching

Opto/Power RF applications Ge compatible HP N channel

Highestσσσσth

Most compact logic, Interconnect

High short channeleffect immunity

Passive layer combine w BOx

(thermal shunt)

Poor short channeleffect immunity

BTBT TFET/ννννW

Opportunities for other materials on SiliconElectronic Device Architectures for the Nano-CMOS EraFrom Ultimate CMOS Scaling to Beyond CMOS DevicesEditor: S.Deleonibus, Pan Stanford Publishing, July 2008



Outline





• Conclusions



NEMS scaling laws. Is it worth scaling?

k3 [rough estimate]energy consumption

k-4mass responsivity

k-1resonant frequency

kstiffness

k3mass

Scaling ruleParameter

twlM eff ⋅⋅∝

3

3

l

tweff ⋅∝κ

20 l

t

Mf

eff

eff ∝∝κ

effeff M

f

M

f

200 −=

∂∂=ℜ

2

21

MaxeffP xE ⋅≈ κ

txMax ∝and

- resolution increases- sensitivity decreases (SBR,SNR) => arrays, actuation,…- figures of merit pressure and vacuum quality dependent

( )20/10 DReff

Q

Mm −⋅=δ

SNRP

SDR

act

noise 1=∝ ∑

ML Roukes et. al. APL (2005)



Nanowire used for mass detection

- First 200 mm wafers with 3.5 millions NEMS - Association Nanowire/Resonator ; Cantilever arrays

CMOS compatible

Capacitive actuation & detection Capacitive actuation & piezo-resistive detection with nanowires

Thermo-elastic actuation & piezo-resistive detection.

15 nm oscillator

Hzzgm /5.0≈δ

Q=870 resonatorGauge width = 80 nm

LETI: T.Ernst et al., IEDM 2008, Invited talkL. Duraffourg et. al, APL 92, 174106 (2008)

E Mille et al, Nanotechnology, 165504, (2010)

NEMS array



M&NEMS co integrated devices platform for 3D sensing

i

P.Robert et al, 2009 IEEE SensorsD.Ettelt et al, 2011 Transducers

3-axis accelerometer∆∆∆∆R/R<5x10-4 ( ±1g) Linearity <0.3% ( 0 and 200MPa)S<1mm2 (3 axis)

3-axis gyroscopeF0 ≈ 20.3 kHzQ > 100.000 S=0.8mm² / axis

3D magnetometer Resol 20-80 nT/ √Hz Lin 4.5 mTS=0.25 mm²/axis

microphone

pressure sensor

NanobeamsArea ÷4 vs SoA



NEMS switch

from AB. Kaul et al., Nano Letters 6(5) 942-947 (2006)

“high” speed

rf

from Q.Li et al.,IEEE Nano 6(2) 256-262 (2007)

bistable

memory

high on/offlow power

logic

from D. Tsamados et al. Solid-State Elec. 52 1374 (2008)



Outline





• Conclusions



Heterogenous Integration On Silicon

80 µm diameter TSV imagers packaging

1 µm diameter High AR TSV stacked ICs

12µm1µm

Si

Si

12µm1µm

Si

Si

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Copper/Copper bonding

Oxide/Oxide bonding

Wafer level packaged MEMS

Packaging is taken into accountat the 3D wafer level

System On Wafer: Heterogeneous co- Integrated Systems (Parallel 3D)

Embedded passives (Passives, filters, spin

torque osc,…)

Stacked Memories + Logic, Sensors,,…

Optical Interconnects

Energy source converter

MEMS

Stacked ICs

Coolingoption

Commercial products- image on board VGA camera, - mixed nodes & modes, - high density TSV

Cross talks:-delay, matching,

-power dissipation(global temp. increase, hot spots, reliability, …)

Multiphysics

New Progress Laws- application specific

Via belt technology

MEMS + IC stack

Ultra flat 3D

Chip stacking(TSV)

Active Silicon interposer


S.Deleonibus CEA-LETI December 2011 | 44Image-on-Board

Active Silicon interposer

Die to Die Copper pillars

Die to substrate

copper pillars

Thinned wafer (~100 µm)

Diam 60µmThick 120 µm

Via Last TSV (Aspect Ratio 2-3)

3D Integration: from imagers to advanced 3D ICs

Memory, Processors, Memory, Processors, Memory, Processors, Memory, Processors, ImagersImagersImagersImagers

withwithwithwith highhighhighhigh densitydensitydensitydensity TSV, NEMSTSV, NEMSTSV, NEMSTSV, NEMS…………

3D-IC

Metal1

ØTSV~3µm Thin Si~15µm

ØTSV~3µm Thin Si~15µm

3D highdensity

withTSV

2001

2008

VGA cameras (300kpixels)

withTSV

2001

2008

2001

2008

VGA cameras (300kpixels)

ST ST ST ST –––– LETI collaborationLETI collaborationLETI collaborationLETI collaboration Stack structure

170µm

30µm

120µm

80µm

400µm

Pitch 120µm

Pitch 50µm

Stack structure

170µm

30µm

120µm

80µm

400µm

Pitch 120µm

Pitch 50µm

Mixed Signal Digital/Analog ST ST ST ST –––– LETI collaborationLETI collaborationLETI collaborationLETI collaboration



Photonics Integration on Silicon. The building blocks.

Grating coupler

Waveguide

In-plane coupler

Optical modulator

MUX & DEMUX

Laser source

Optical switch

Photodetector

LETI: L.Fulbert ESSDERC 2011, Invited talk



COMPUTING

& STORAGE

Application Drivers

MOBILE MOBILE

WIRELESS

WIRELESSHEALTH

AUTOMOTIVE

CONSUMER

CONSUMER

FormForm FactorFactor

CostCost

PerformancePerformanceNokia N82, 5Mpixel

Video capture, coding, transmission

Ultra small TV Tuner , Sharp

One Chip SetTopBox(STM)

Computer control using thoughts

Quad Core Intel

Intel's Teraflop Chip

128 GB SSD, Toshiba

Full tranceiver on Chip, Antenna+RF+

Baseband, Leti

Great focus on packaging & integration



Conclusion :Nanoelectronics CMOS fromDevices to Systems Perspectives

� Si CMOS: Nanoelectronics Base platform beyond ITRS

� Durable Low Power solutions: health, environment, quality of life, energy, IST,…

� Low Power consumption: major challenge (sub 1V VDD CMOS).

=> Device/ system architecture optimization:

Thin Films Gate All Around nanowires, low slopes,layout, 3D

=> Opportunities for new materials on Silicon

(Ge, revised low BG III-V, Carbon,…) to co-integrate from LSTP to HP.

� Heterogeneous 3D co-Integration on Si, Low Power: Monolithic/Sequential 3rd

dimension in device. New active materials Reconfigurability with NVM ; NV Logic

System On Wafer: 2 to 3D heterogeneity functions & chips

Thank you for your attention

Merci de votre attention



Electronic Device Architectures for the Nano-CMOS Era

From Ultimate CMOS Scaling to Beyond CMOS Devicesedited by Simon Deleonibus (CEA-LETI, France) Cloth July 2008 978-981-4241-28-1

�� Discusses the scaling limits of CMOS, the leverage brought by new materials, processes and device architectures (HiK and metal gate, SOI, GeOI, Multigate transistors, and others), the fundamental physical limits of switching based on electronic devices and new applications based on few electrons operation

�� Weighs the limits of copper interconnects against the challenges of implementation of optical interconnects

�� Reviews different memory architecture opportunities through the strong low-power requirement of mobile nomadic systems, due to the increasing role of these devices in future circuits

�� Discusses new paths added to CMOS architectures based on single-electron transistors, molecular devices, carbon nanotubes, and spin electronic FETs

Available at Amazon.com or any good bookstores.

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