mos interface processing and properties utilizing ba ...neil/sic_workshop... · 2015 arl-workshop,...

MOS interface processing and properties

utilizing Ba-interface layers

Daniel J. Lichtenwalner, Vipindas Pala, Brett Hull, Scott Allen,

& John W. Palmour

Power R&D, Cree, Inc. Durham, NC 27703

Partial funding from the Army Research Laboratory, Adelphi, MD

2015 ARL-workshop, University of Maryland – August 13, 2015

OUTLINE

1. Motivation

1. Channel resistance

2. MOS interface passivation

2. Experimental: interface modification

3. MOSFET channel properties

1. Field-Effect Mobility & interface charge

2. DMOS RDS(on), switching

4. MOSFET gate oxide properties

1. Electrical properties

2. Material characterization

5. Summary

2 Lichtenwalner, Cree, Inc. - ARL-workshop, UMD Aug. 13, 2015

• Cree Gen3 1200V devices projected to have Ron,sp ~2.7 mOhm-cm2

• With current ‘NO’ process (FE mob~18), RCH ~1 mOhm-cm2

• Doubling the channel mobility would reduce Ron,sp by ~16%

1.1 Motivation: Channel resistance


Subs Subs

Drift-related

Drift-related

Ohmic Ohmic

MOS chan

0.95 MOS chan0.45

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Gen3 hi-mob Gen3

Ro

n,s

p (

mO

hm

-cm

2)

1200V Gen3 Hi-mob benefit2.7 mOhm-cm2 2.2 mOhm-cm2

The Ideal Passivation:

• Concentration ≥ NIT (~1013 cm-2)

• All at the interface

• Thermally stable

GROUP I elements:

H, Na: interface passivation, & interface

sheet charge; but mobile

GROUP V elements:

N, P, As, Sb: mix of interface passivation

& counter-doping

Other elements:

Group II: Sr, Ba (Cree)

Group III: La (V. Misra group, NCSU)

lowering of DIT observed

General trend: (demonstrated by Na)

Un-passivated thermal oxide: mobility~0

DIT passivation ~smooth mobility curve

Counter-doping (or sheet charge) ~peaked

mobility curve, lower VT

1.2 MOS interface – passivation approaches


See: Liu, Tuttle, Dhar, Appl. Phys. Rev. 2, 021307 (2015)

Tuttle et al., JAP 109 (2011)

Lateral & Vertical MOSFETs:

• Al-doped p-type SiC (0001)

channel

• Thin evaporated Ba (or Sr)

passivation layer

• Deposited SiO2 gate oxide

• Oxide annealed in O2/N2

• Poly-Si gate (B-doped)

• Ni ohmic

Electrical Measurements:

• ID-VD

• ID-Vg vs Temp

(VT, F.E. mobility)

• Quasi-static gate C-V

(Tox, Vfb, VT, Qf)

• Gate Ig-Vg

(CB, VB F-N barrier height, EBD)

Materials Analysis:

• Spectroscopic Ellipsometry

• SIMS

• AFM

2. Experimental: Si-face, 4H-SiC MOSFETs


P-epi SiC

N+ N+

Gate

SiO2

IL

D S

Significant Mobility enhancement with

alkaline earth elements Sr and Ba.

• 5E15 p-doping level

Id-Vg for lateral MOSFET with Ba-

based interface layer:

• Low gate leakage

• VT ~1.2 V

3.1 MOSFET Field Effect mobility


0

20

40

60

80

100

1.0E-14

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

0 4 8 12 16

Mo

bil

ity (c

m2/V

s)

Cu

rre

nt

(A)

Gate Voltage (V)

10-4

10-6

10-8

10-10

10-12

10-14

IG

ID

mobility

0

20

40

60

80

100

120

0 4 8 12 16

Mo

bil

ity (c

m2/V

. s)

Gate Voltage (V)

Ba IL

Sr IL

'NO'

no ILCa IL

Ba-IL vs ‘NO’, 5E15 doping:

• NO-anneal: coulomb scattering

effects (high DIT near CB)

• Ba IL: phonon scattering

dominates (low DIT near CB)

Peak mobility vs doping:

• Mobility decreases with doping; as

expected

• mobility with Ba-IL remains above

the value with NO anneal

3.1 MOSFET F.E. mobility: Temperature & doping


0

20

40

60

80

100

-4 0 4 8 12 16

Mo

bilit

y (

cm

2/V

. s)

Gate Voltage (V)

25oC

100oC150oC

150oC

25oC

Ba IL

'NO'

0

20

40

60

80

100

120

1E+15 1E+16 1E+17 1E+18 1E+19

Mo

bilit

y (

cm

2/V

. s)

Doping (atoms/cm3)

Ba IL

'NO'

1015 1016 1017 1018 1019

DIT & Qf from fit to C-V:

• NIT = (-) 4.5×1010 cm-2

• Qf(eff) = (+) 2.0×1012 cm-2

DIT: thermal vs NO anneal vs Ba IL

• Ba IL clearly provides DIT

reduction, slightly better than ‘NO’

process.

3.1 MOS interface charge (C-V of n-Cap)*


1E+09

1E+10

1E+11

1E+12

1E+13

2.2 2.4 2.6 2.8 3.0 3.2 3.4

DIT

(cm

-2 e

V-1

)

E - EVB (eV)

thermal oxide

thermal+NO

Ba IL

EF Ec

1013

1012

1011

1010

109

*underestimates true DIT; see A. V. Penumatcha, S. Swandono, & J. A. Cooper, IEEE TED 60, 923–926 (2013).

• 1200V DMOS:

High-mob vs ‘NO’ control

• Ba IL provides ~0.5 mW-cm2 reduction in RON,SP

• 1200V DMOS: High-mob

• Low RON,SP with VG below 20V

3.2 1200V 15A DMOS Ron,sp


1.5

2.0

2.5

3.0

3.5

10 12 14 16 18 20 22R

on

,SP

(mW

-cm

2)

Gate Voltage (V)

BEST 15A Gen3 DMOS with high-mobility

High-mob switching:

800VD, 15A VG -5 to +20V, TJ = 25 °C

RG(ext) = 6.8 Ω, L = 856 μH

Packaged devices compared:

Gen3: Control vs Hi-mob

3.2 1200V 15A DMOS: packaged device switching

-5

0

5

10

15

20

25

30

-200

0

200

400

600

800

1,000

1,200

-1E-06 -6E-07 -2E-07 2E-07 6E-07 1E-06

Ids

(A)

Vd

s(V

)

Time (s)

Packaged 1200V 15A Hi-mob device

Vds

Ids

High-mobility oxide process does not adversely affect switching loss


0

50

100

150

200

250

300

0 5 10 15 20E

ne

rgy

(u

J)Drain Current (A)

Switching loss - 800Vd, -5/+20Vg

Hi-mob

Control

Etotal

Eon

Eoff

Lichtenwalner, Cree, Inc. - ARL-workshop, UMD Aug. 13, 2015 11

4. MOSFET gate oxide properties

CB barrier:

NO: 2.84eV

Ba IL: 2.80eV

VB barrier:

NO: 3.05eV

Ba IL: 2.79eV

FN plot: slope (B) = 6.83E7*(mox/m)1/2*PhiB3/2

mox(e)=0.42*m; mox(h)=0.58*M (Chanana, APL (2011)).

4.1 MOS gate oxide: effective FN barrier height


Ideal SiO2 on SiC:

J. Robertson, B. Falabretti,

Mat. Sci. & Eng. B

135, 267 (2006).

Measured Oxide I-V:

FN Barrier heights ~good with Ba-IL; but VB offset lower.

0E+00

2E-06

4E-06

6E-06

8E-06

1E-05

0 500 1,000 1,500 2,000

Dra

in C

urr

en

t (A

)

Drain Voltage (V)

1200V 15A hi-mob DMOS blocking

0E+00

2E-06

4E-06

6E-06

8E-06

1E-05

0 500 1,000 1,500D

rain

Cu

rre

nt

(A)

Drain Voltage (V)

1200V 15A hi-mob DMOS blocking

• Many devices block to the

avalanche limit of the drift layer

• Some devices have early

blocking failure

4.1 High-mobility: 1200V DMOSFET blocking

• Blocking failures mainly due to gate oxide breakdown

• The high-mobility process requires optimization

~1200V

~1650V


Ramped VG large n-Caps (2x2 mm2)

Qty>100

control

thermal

oxide+NO

• High-mob oxide: ~15% lower EBD

• High-mob oxide: more extrinsic

failures

4.1 MOS gate oxide: Breakdown Field

High-

mobility

oxide

Need for continued study to improve oxide reliability


4.1 High-mobility: NBTI / PBTI VT stability

High-mobility 1200V packaged devices: 150C, -15VG & +15VG stress, 100hrs

No NBTI VT shift some PBTI VT shift


High-mobility oxide process may introduce some positive threshold shift;

further study needed

1E-12

1E-09

1E-06

1E-03

1E+00

-2 -1 0 1 2 3 4 5 6 7 8

Cu

rre

nt

(A)

Gate Voltage (V)

Pkgd hi-mob DMOS PBTI 15V 150C

CJ06W3 #12 2272

t=100hr

t= 0

0

1

2

3

4

5

6

0 20 40 60 80 100

VT

(V)

stress time (hr)

150oC: NBTI -15Vg, PBTI +15Vg

PBTI DVT ~1V

NBTI DVT <0.1V

1E-12

1E-09

1E-06

1E-03

1E+00

-4 -2 0 2 4 6

Cu

rre

nt

(A)

Gate Voltage (V)

Pkgd hi-mob DMOS NBTI -15V 150C

CJ06W3 #1 2272

t= 0

t=100hr

4.2 Materials characterization: oxidation (ellipsometry)

• Ba & Sr IL enhances oxidation rates of both Si and SiC

• Can be fit with Deal-Grove model, with appropriate parabolic and linear rate

constants

• The Ba (and Sr) greatly increase the linear rate constant, consistent with an

increased interface reaction rate

Lines: Deal-Grove fits (JAP 36, 3770 (1965))


0

50

100

150

200

0 150 300 450 600

SiO

2g

row

th (

nm

)

PDA time (min)

950°C anneal, 20% O2

SiC: Ba IL

SiC: no IL

Si: Ba IL

Si: no IL

SiC: Sr IL

Deal-Grove Paralinear oxidation rate

model:

Xox+A*Xox = B*(t+t)

Where:

B = parabolic rate constant

(diffusion-limited)

B/A = linear rate constant

(interface-reaction-limited)

4.2 Materials characterization: Ba depth profile (SIMS)

• 30nm SiO2/Ba IL/SiC: as-fabricated VS after enhanced oxidation

• Approximate Ba concentration, as sensitivity factor in SiO2 & SiC uncertain

900 ºC 1hr O2/N2 anneal 950 ºC 10hr O2/N2 anneal


1E+14

1E+15

1E+16

1E+17

1E+18

1E+19

1E+20

1E+21

1E+22

1E+23

1E+24

0.00 0.05 0.10 0.15 0.20

Co

nc

(c

m-3

)

Depth (μm)

16 O

28 Si

12 C

138 Ba

1024

1022

1020

1018

1016

1014

depSiO2 SiC

900 oC 1hr 20% O2 anneal

1E+14

1E+15

1E+16

1E+17

1E+18

1E+19

1E+20

1E+21

1E+22

1E+23

1E+24

0.00 0.05 0.10 0.15 0.20C

on

c (

cm

-3)

Depth (μm)

16 O

28 Si

12 C

138 Ba

1024

1022

1020

1018

1016

1014

dep MEO SiO2 SiO2 SiC

1024

1022

1020

1018

1016

1014950 oC 10hr 20% O2 anneal

• Ba is concentrated/stays mainly at the interface, <30ppm in the oxide

4.2 Materials characterization: oxide morphology (AFM)

AFM images of SiC after gate oxidation reveal:

• SiC step-bunching

in some samples

• SiO2 crystallites

Size = f(Temp)

Either could affect oxide breakdown


20x20 um2

1175C, 2hrs, RMS 1.75 nm

20x20 um2

1250C, 1.7hr, RMS 1.75 nm

5. Summary

• Alkaline earth elements Sr and Ba are effective for Si-face SiC mobility enhancement

• Ba IL provides DIT values slightly lower than that of NO anneals

• VT is stable under NBTI stress; while electron trapping occurs with PBTI (no mobile ions)

• FN tunneling shows that the CB offset is unchanged, while the VB offset is slightly

reduced, with Ba at the interface

• SiO2 oxide breakdown strength is reduced with Ba from ~11.5 MV/cm to ~10 MV/cm,

with more extrinsic failures indicating oxide defects

• Optimizing the oxide strength and oxide reliability are keys for this or other

passivation approaches supplanting the ‘NO’ anneal process


mos interface processing and properties utilizing ba ...neil/sic_workshop... · 2015 arl-workshop,...

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