mos mismatch caused by cmp metal

302 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 14, NO. 4, NOVEMBER 2001

Characterization of Systematic MOSFET CurrentFactor Mismatch Caused by Metal CMP Dummy

StructuresHans P. Tuinhout and Maarten Vertregt, Member, IEEE

AbstractThis paper presents a study on techniques for char-acterization of metaloxidesemiconductor field-effect transistor(MOSFET) transconductance mismatch, using matched pairs withintentional 1% dimensional offsets. The relevance of this kind ofwork is demonstrated by the introduction of a new mismatch phe-nomenon that can be attributed to mechanical strain, associatedwith metal dummy structures that are required for backend chem-ical mechanical polishing (CMP) processing steps.

Index TermsMicroelectronic test structure, MOSFET mea-surement method, systematic parametric mismatch.

I. INTRODUCTION

TRANSISTOR size reduction and the continuing evo-lution toward mixed signal system-on-a-chip solutionsthat require integrated high-precision analog small-signalprocessing, have considerably intensified the attention formetaloxidesemiconductor field-effect transistor (MOSFET)matching in modern complimentary metaloxidesemicon-ductor (CMOS) technologies [1][7]. Matching, short forstatistical device behavior differences between supposedlyidentical components, is usually attributed to random variationsof microscopic physical quantities, like edge roughness, fluc-tuation of the number of dopant atoms or interface states, etc.[3], [4]. Usually these stochastic variations are characterizedthrough the standard deviations of mismatch distributions ofthe main MOSFET compact model parameters ( and

). Besides these random fluctuations, several physicaleffects are causing so-called systematic mismatch, meaning thatthe median (or the average) of the mismatch distribution devi-ates significantly from zero. Causes for systematic mismatchobservations are for example: photomask offsets, topographyrelated offsets [5] and local mechanical stress asymmetries [6],[7]. Although systematic mismatch effects are often relativelysmall (from a few percent down to a fraction of a percent),their impact on the performance of high precision analogelectronic circuits can be quite significant. Applications likehigh-resolution A/D and D/A converters (10 bits and higher)suffer (yield loss) from levels of component inequality down toas low as the 0.01% range. Apart from the efforts that need togo into the fabrication of devices with these low mismatches,

Manuscript received November 14, 2000.The authors are with Philips Research The Netherlands, 5656 AA

Eindhoven, The Netherlands (e-mail: [email protected];[email protected]).

Publisher Item Identifier S 0894-6507(01)09764-0.

Fig. 1. Example of a measured distribution of the relative current factormismatch = for a population of 90 W=L = 10=10 m N-channeltransistors. Statistical estimators: Median = 0.15%, Standard deviation =0.18%.

this poses stringent demands on measurement techniques forcharacterization of these mismatch effects.

Fig. 1 presents a typical example of a measured histogramof the relative current factor mismatch for a populationof m N-channel transistors. The MOSFETcurrent factor is defined in the usual manner as ,in which represents the mobility, the gate-oxide capaci-tance and and the (effective) transistor width and lengthrespectively. Even an inexperienced statistical eye will haveno difficulty to identify a systematic mismatch in this distribu-tion, which is confirmed by the calculated statistical estimators(for this example yielding a median value of 0.15%). How-ever, the inevitable dilemma that one is faced with at this pointis the question whether this perceived systematic mismatch isdue to the fabrication process, or perhaps caused by the mea-surement. Note that a 0.15% mismatch on a 10 m large devicecan be explained by as little as 15 nm dimensional offset on sil-icon. On the other hand, this systematic mismatch could havealso been caused by a 0.15% offset in one of the current metersor, alternatively, a 150- V voltage offset in one of the 100-mVdrain voltage sources that are used for the linear region param-eter extraction algorithm. These are numbers that generally fallwell within the overall specifications of the technology underinvestigation as well as of the used measurement equipment.

Whereas most of the matching literature focuses on tech-niques for characterization of the random component of

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TUINHOUT AND VERTREGT: CHARACTERIZATION OF SYSTEMATIC MOSFET CURRENT FACTOR MISMATCH 303

Fig. 2. Schematic drawing of CS/CG matched pair test structure layout. Thetwo drains of each pair are padded out separately.

mismatch distributions, this paper (along with [5] and [7])presents a study on the limits of systematic mismatch charac-terization of, in this case, the MOSFET transconductance (orrather current factor ). A very useful tool for this study proveda set of MOSFET matched pair test structures in which twoof the pairs were designed with intentional 1% dimensionaloffsets. Techniques for calibrating measurements systems andalgorithms using known deviations around a target value arequite common in the world of advanced metrology. Obviouslythe approach as used in this paper does not provide an officialabsolute measurement accuracy as the test structures are notcalibrated using traceable standards from a certified institute.Nevertheless, offset test structures as the ones proposed in thispaper prove very useful for assessing whether the observedsmall systematic mismatches could be due to measurementsystem limitations, or that they can indeed be attributed tophysical phenomena.

In the following sections, our test structures are described,a measurement method explained, some results discussed andseveral measurement method improvements suggested. The rel-evance of this type of work is demonstrated through the intro-duction of a new systematic mismatch phenomenon. We showthat metal dummy patterns as used for backend chemical me-chanical polishing (CMP) can have significant detrimental im-pact on matching of MOSFETs.

II. TEST STRUCTURE

Fig. 2 presents a schematic drawing of the used MOSFETmatched pair test structure layout. The pairs are of a Common-Source/Common-Gate (CS/CG) layout configuration. The twodrains of each pair are padded out separately. This layout ap-proach was applied for a full suite of transistor geometries ina 0.18- m CMOS technology. The complete set of test struc-tures consists of 45 different matched pairs (Fig. 3), rangingfrom standard n- and p-channel pairs with varying geometries tospecials like the intentional offset pairs discussed in this paper.Fig. 4 shows a photomicrograph of the heart of amatched pair transistor test structure (after processing up to thesecond metal level). The most striking (confusing) features ofmodern CMOS test structures are the so-called CMP dummystructures (tiles). In Fig. 4 they are visible for the mask layersactive and poly (small stacked squares) as well as for tungstenmetal-1 (large dark-grey squares) and aluminum metal-2 (largelight-grey squares). CMP dummy structures are automaticallygenerated and placed during the mask post-processing in orderto create sufficient layer coverage to assure homogeneous CMPpad pressure over the entire (test) chip area. However, to pre-vent possible matching degradation associated with incomplete

Fig. 3. Composite photograph of full suite of matched pair test structures. Theset of 45 matched pairs is placed twice on a multiproject chip. (The rest of thetest chip is not shown.)

Fig. 4. Photomicrograph of NC 10/10 MOSFET matched pair. Circlesindicate the positions of the two transistors T (left) and T (right). CMPdummy structures (tiles) are visible for the mask layers active and poly (smallstacked squares, Metal-1 (Tungsten; large dark-grey squares) and Metal-2(Aluminum; large light-grey squares).

H passivation [6], some of the metal dummies were removedin the test structure areas where they coincided with a transistorgate.

The MOSFET mismatch-measurement-algorithm verifica-tion study reported in this paper was carried out using threeversions of a standard n-channel pair. In two ofthe three pairs, a 0.1 m dimensional offset was deliberatelyintroduced in one of the transistors of the pair. This shouldresult in either a 1% or a 1% systematic offset of thecurrent factor mismatch distribution. Table I lists the designdimensions of the three pairs as well as their names by whichthey are identified in this paper.

To reduce the statistical uncertainty for calculation of the sta-tistical estimators and for populations derived from a single



TABLE IOFFSET PAIRS: LAYOUT DIMENSIONS

wafer, the entire set of transistor matching test structures wasplaced twice on each reticle. In this paper these two positionsare denoted as the #1 and #2 positions respectively (see Fig. 3).In total, all populations for the experiments discussed in thispaper hence consisted of 2 45 ( 90) pairs, coming from the45 reticle placements that were spread out evenly over the entire200-mm wafer.

III. MEASUREMENT ALGORITHM

The MOSFET mismatch measurements are performed usinga dedicated dc matching characterization station, based on anHP4156A high-precision semiconductor parameter analyzerand a low-noise Cascade-Microtech semi-automatic waferprober. Both transistors of each pair are probed simultane-ously but are measured time-sequentially using a three-pointlinear-region direct-extraction technique [8], [9]. This algo-rithm yields three parameters for each transistor of the pair: athreshold voltage , a current factor and a mobility reduc-tion factor (Fig. 5). The parameter absorbs the source/drainresistances as well as needle/probe/cable series resistances.The current factor mismatch (equal to the transconductancemismatch), is defined as:

To reduce measurement system induced uncertainties andnoise as much as possible, no switching matrix is used inthis mismatch characterization system. This avoids additionalswitch relay resistances fluctuations and offsets due to thermalvoltage differences. Moreover, as this measurement station isalso used for matching characterization of high-performancepoly-emitter BJTs, it was decided to define test structures andmeasurement methods in such a way that no switching matrixwould be required for the matching characterization studies(switching matrices tend to make BJT measurements moreprone to device oscillations).

Fig. 6 gives the measurement circuit that we used. As a resultof relying on a measurement setup without switching matrix, thedrains of the two MOSFETs must be connected to two separate(but fixed) SMUs (and needles, manipulators, cables, etc.).

The CS/CG matched pair test structure configuration and as-sociated measurement circuit is usually chosen for its optimummeasurement system performance with respect to characteri-zation of threshold voltage mismatch. The CS/CG layout as-sures that the main (sweeping) voltage variable for the thresholdvoltage measurement is identical for both transistors of

Fig. 5. Example of linear region MOSFET measurements (V = 0:1 V,V = 0 V). Circles: Drain current. Triangles: Transconductance(dI =dV ). Encircled (three) drain currents are used for parameterextraction. Interpretation of resulting parameters V , and are indicated inthe graph.

Fig. 6. Used measurement circuit for CS/CG MOSFET matched pairmismatch characterization. Note: substrate (chuck or well) is connected toSMU5.

the pair. By measuring the main transistor currents andin the (common) source connection (SMU2) rather than

using the two drain SMUs, systematic mismatch observationsdue to offset, gain differences or ranging artifacts between thecurrent meters in SMU3 and SMU4 are avoided.

Time-sequentiality of the measurements of the two transistorsthat are probed simultaneously is realized through alternatingthe drain biases. When transistor is measured, is setto 0.1 V while is equal to zero. When is measured,

is at 0.1 V while virtually switching off by settingto zero. In reality setting to zero is not a very effectivetechnique for switching off an MOS transistor. The transistorthat is supposed to be switched off is obviously biased with the



same gate voltage as its twin in the CS/CG pair. Hence, due tothe voltage offset of the zero volts SMU, a substantial current(order of pico-Amps or even nano-Amps) will flow through thistransistor, which will add to the main transistor current in the(common) source connection. This is a fundamental limitationof this approach. The choice between measuring the two draincurrents (simultaneously) in separate SMUs or measuring them(sequentially) in the common source SMU depends on the hard-ware specifications and the calibration accuracy of the avail-able measurement system. In practice we have seen no evidenceof possible systematic mismatch contributions of the describedtime-sequential measurement technique. Nevertheless, some al-ternative techniques are discussed in the discussion section ofthis paper.

All transistors of a particular population are measured usingthe same three fixed gate voltages (e.g., V,

V and V, see Fig. 5). This means thatthe gate overdrive voltages may vary slightly dueto the threshold voltage spread across the wafer. In the reportedexperiment, the effect of this variation is negligible, as the stan-dard deviation of the variation across the wafer was found tobe less than 1 mV for these devices. The mostimportant criterion for the selection of the three gate voltagesis that the lowest point should at least be located at (or slightlyabove) the peak-transconductance point (Fig. 5). This assuresthat the transistor operates in the (linear) modeling regime thatis used for the parameter calculations. This is quite similar towhat was suggested by Hamer in [8].

For most studies on MOSFET matching, the system andmethod described above proves to be more than adequate.The short-term repeatability performance for determination of

and current factor mismatch standard deviations (and ) are typically better than 50 V and 0.02%,respectively. This is for instance visualized in Fig. 7, whichdisplays results of measuring the mismatch distribution fora particular population of (standard) 10/10 pairs two times.Along the horizontal axes, the individual mismatch observa-tions are depicted as determined initially, whereas the verticalaxes corresponds to the results for exactly the same populationmeasured approximately one hour later. The correlation speaksfor itself while the scatter gives an impression of the normalshort-term repeatability levels as mentioned above.

IV. RESULTS AND DISCUSSION

The main purpose of the study as reported in this work wasto identify how useful the standard algorithm as discussed inthe previous section is for identification of systematic transcon-ductance mismatch occurrences. As will become clear duringthe remainder of this paper, the example of Fig. 1 is in facta classical example of a double distribution coming from twoslightly different populations, each with their own systematicmismatch component. The questions that we were faced withwere: how real are these systematic mismatch observations andwhat causes them?

During this study, we came to the conclusion that the mainweakness of the no-switching-matrix measurement approachdescribed in the previous section lies in the fact that the two

Fig. 7. Scatter plots of two measurement sequences (approximately one hourapart) of the same population of standard 10/10 matched pairs. Deviation fromthe perfect 1 : 1 correlation gives indication for the short-term repeatability ofthe chosen characterization approach.

transistors of the pair are not biased with exactly identical drainSMUs. Voltage forcing differences of up to 200 V are not un-common according to the specifications of the used parameteranalyzer system. When studying subtle systematic mismatch ef-fects, differences of this magnitude can be quite significant, asthe voltage forcing offset propagates linearly into the observedcurrent factor mismatch. Note that an offset of 200 V on anintended 100 mV bias would correspond to a 0.2% systematiccurrent factor mismatch!

For very detailed mismatch studies like the one presented inthis paper, the effects of this systematic SMU voltage differ-ence can be suppressed by measuring the mismatch distribu-tions twice: initially as depicted in Fig. 6, and then the entiremismatch distribution is remeasured after interchanging the twodrain probe positions, or alternatively by swapping the cables toSMU3 and SMU4 (the manual cable chaser switch matrix).

Let us assume that an observed mismatch consists oftwo independent components: a associated with the actualmismatch between the devices of the pair and a due to themeasurement system (for instance caused by the voltage sourceoffset difference suggested above). During the initial measure-ments of the population of pairs this results into mismatch obser-vations for each pair: .When we interchange the physical connections to the pair weget a second set of observations .As we can safely assume that the devices (and hence their mis-match) have not changed, the observed mismatch of the de-vice (as seen by the measurement system) should reverse sign

, whereas the contribution of the systemitself will remain unchanged (if the voltage offset between thetwo SMUs has not changed during the entire double measure-ment procedure): . Now it follows that



Fig. 8. Normal Scaled cumulative probability plot of (solid triangles; = 0:015% and = 0:17%) and (xs; = 0:093% and =0:01%).

Fig. 9. Cumulative probability plots for current factor mismatch for the threeoffset matched pair test structures (#1 reticle position). Estimators: see Table II.

subtracting the individual mismatch observations removes theSMU3/4 systematic offset contribution from the transistor mis-match observation: . Addingthe two observations and dividing by , yields the actual mea-surement systems offset, as .

An example of results obtained using this measurement com-pensation approach is shown in Fig. 8, where cumulative proba-bility plots are given of the resulting device mismatchesfor the standard 10/10 pairs at the #1 reticle positions, as wellas the calculated measurement system offset . The hori-zontal axis in this figure represents the cumulative probabilityexpressed in terms of sigmas. The used (NORMSINV) scalingtransforms the (sorted) mismatch observations to a straight linewhen the distribution is normal. Standard statistical estimatorcalculations yield % and

% for the transistor mismatch distribution and% and % for the measurement systems

offset distribution.From this example, we can conclude that the noise contribu-

tion of the measurement system is very small com-pared to the transistor current factor mismatch fluctuations. Themeasurement system induced offset , on the other hand(about 0.1%), can definitely not be neglected for this example.

Fig. 9 depicts the current factor mismatch results for thethree offset test structures when the double (cable swapping)measurement technique as described above is used. Thecumulative distributions for the three populations display

similar slopes (standard deviations). This is as expected as theeffective device areas are almost identical. The vertical axisintercepts of the three distributions indeed yield the designed

1% 0% and 1% systematic mismatches quite accurately.The statistical estimators resulting from these (twice measured)transconductance mismatch distributions are summarized inTable II. Values between brackets represent estimates for thestatistical uncertainties as determined using bootstrap analysis[10]. Apart from the good agreement between the designedand measured medians of the matching distributions, we seethat the median of measurement systems offset ranges from

0.093% to 0.101%. This contribution can be attributed to aoffset voltage difference between SMU3 and SMU4 of the

order of 100 V. Again it will be obvious that this offset wouldhave severely distorted any conclusion about the systematicmismatch of the pairs if not compensated for.

V. ALGORITHM IMPROVEMENTS

It will be evident that once the main limitations of the orig-inal method are pinpointed, several alternative measurementmethods spring to mind. After all, measuring every distributiontwice may be acceptable for an exploratory study, but is notvery practical when many devices are to be characterized.An example of an alternative method is based on a voltagetransformation scheme combined with SMU ground voltageoffset compensation. This approach is comparable to the oneused for accurate measurements of bipolar junction transistorsas described in [11]. For MOSFETs, this means that instead ofmeasuring the transistors with the drain at 0.1 V, we ground thedrain for the transistor under test and apply a negative sourcevoltage. Obviously one has to adapt all other biases for thisapproach: i.e., the substrate at 0.1 V while subtracting 0.1 Vfrom all intended gate biases. Setting its drain bias also to

0.1 can deactivate the transistor of the pair that is supposedto be inactive. The main advantage of this approach is thatthe secondary driving voltage is now also identical forboth transistors of the pair since it is determined by the forcingvoltage source of SMU2. Likewise to what was reported in[11], the voltage source inequality problem is now shifted tothe inequality of the zero value (COMMON) of the two drainSMUs. By placing extra needles on the two drain contact padsand connecting these with the internal differential voltmeter ofthe parameter analyzer (VMU1 and 2), we can monitor (andcompensate for) this offset voltage.

Fig. 10 shows a measured example of the voltage differencebetween SMU3 and SMU4 when they are both at COMMON(both transistors active!). This graph is compiled from offset ob-servations during the mismatch measurements of some 500 pairswhile testing the voltage transformation scheme as sketchedabove. As it took several hours to collect these measurements(this includes the mismatch measurements, aligning the wafer,adjusting probes etc.) the following conclusions can be drawnfrom this figure:

1) It is indeed not unlikely that offset voltages of theorder of 100 V are the major cause for the systematicoffset that was identified in the previous Section II.



TABLE IIMATCHING AND SYSTEM OFFSET RESULTS FOR OFFSET PAIRS AT #1 POSITION

Fig. 10. Voltage offset between SMU3 and SMU4 during verification ofvoltage transformation measurement algorithm (both SMUs grounded).

2) Apart from some outliers that are probably due to EMCdisturbances (power-line disturbances?), the noise as ob-served around the typical offset voltage is of the order ofabout 10 V.

3) A slow drift is observed of the order of 1020 V, pos-sibly related to a small temperature increase in the mea-surement laboratory that was observed during this test.

4) Both the drift and the noise are small enough to justifythat the (accurate, lengthy, long integration) voltage offsetmeasurements do not have to be repeated for each pair aswas done for Fig. 10: Once for each distribution of 4050pairs seems sufficient.

5) As the transconductance of a MOSFET is linearly pro-portional to its , the value that is obtained from theoffset voltage measurement can simply be used to correctthe mismatch observation. This brings the uncertainty dueto the measurement system down by at least an order ofmagnitude: From 100 to 200 V to a level of 10 to 20 V.This would correspond to a transconductance mismatchlevel of the order of 0.01% to 0.02%, which is the sameorder as the systems noise (Figs. 6 and 7).

In conclusion, we can say that the voltage transformationscheme combined with occasional monitoring the commonoffset drift of SMU3 and SMU4 proves a viable solution forcharacterising systematic mismatches down to a level of as lowas 0.1%.

An alternative approach to reduce the impact of some of thelimitations sketched above would be to start from an entirelydifferent matched pair test structure design. If we would use acommon source and common drain (CS/CD) test structure (with

separate Gate pads for each transistor of the pair), we wouldnot have to worry about the offsets of the Drain connection, butobviously this is now replaced by an uncertainty due to Gatevoltage differences. The advantages of this alternative type ofmatched pair test structure are:

1) The observed mismatch will be independent of theDrain and Source voltages and the main (Drain) currentsareby definitionmeasured with the same currentmeter.

2) As both the Source as well as the Drain pad are common,probe needle-to-pad resistance differences will notinfluence the mismatch observation. This is particularlyimportant for higher current mismatch measurements( 100 A). As the Gate current is (many) orders ofmagnitude lower than the Drain and Source currents,voltage drops in the Gate-pad-to-probe needle will benegligible.

3) It is much easier to switch off one of the transistors whilethe other one is measured, as the gate of the inactive tran-sistor can be biased well into the subthreshold regimeof the transistor. This is much better controlled than therather unpredictable Drain off-current that can flow in theCS/CG structure.

Whereas the CS/CG matched pair test structure approachallows the choice between a time-sequential measurement(using the current meter in the common Source connection)and a simultaneous measurement (using the two current metersof the two Drain SMUs), this freedom obviously does not existfor CS/CD matched pair test structures. CS/CG pairs must bemeasured time-sequential. The major concern of a time-se-quential type of measurement is associated with temperaturedrift between the measurements of the two devices. It shouldbe noted that for extremely sensitive mismatch measurements( 100 ppm), a temperature drift of the order of 0.01 Cbetween measurements of two devices may become noticeable.

Obviously, for applications where systematic thresholdvoltage mismatch measurements of the order of 100 V aredeemed critical, a voltage transformation scheme as sketchedabove, combined with monitoring the (common) voltage offsetsof the Gate SMUs can be used.

Finally, a word of caution about an alternative for the ear-lier mentioned fundamental limitation of our original CS/CGmeasurement algorithm. As discussed before, realizing time-se-quentiality of the current measurements by switching off one ofthe transistors through a 0 V is not very effective. In prin-ciple it is possible to assure that the current through the inactive



TABLE IIIMATCHING AND SYSTEM OFFSET RESULTS FOR OFFSET PAIRS AT #2 POSITION

transistor is negligible by programming its SMU as a zero (orvery low) current source. This assures that the currents throughthe inactive transistor are many orders of magnitude lower thanthe currents in the active transistor. We tested this approach buthad to abandon it as we found that this method resulted in anunacceptable number of destructed pairs. We did not investi-gate this in depth, but apparently the sequence of switchingon and off the various voltage and current sources in this ap-proach resulted in substantial spikes on the gates, which sufficedto blow-up the gate oxide of a significant number of pairs. Inpractice this meant that re-measuring a distribution became vir-tually impossible, and the quite attractive repeatability resultsas shown in Fig. 7 could not be reached with this alternativeapproach.

VI. A NEW MISMATCH PHENOMENON

One of the reasons for conducting this extensive study towardthe limitations of the existing MOSFET mismatch characteriza-tion algorithm was the observation of a more or less unexpectedsystematic mismatch phenomenon. Table III forms an introduc-tion to this effect. This table summarizes the statistical estima-tors for the set of dimensional offset transistor pairs, be it thatthey are taken from the #2 reticle positions, as opposed to thedata from Table II that were obtained from the #1 reticle posi-tions. These #1 and #2 reticle positions (see Fig. 3) were sup-posed to be identical. They were placed on the reticle to reducestatistical uncertainty and with an idea at the back of minds ofpossibly searching for evidence of systematic differences due toe-beam reticle writing artifacts.

Clearly, Table III reveals the same trends with respect to thestatistical estimators as Table II. The standard deviations arevery much comparable, while the system noise and offset arevirtually identical. Nevertheless, the data suggest that the me-dian values of the matching differ statistically significant fromthe data summarized in Table II. Since these results were col-lected from a different population (the other reticle position), theinitial explanation for this discrepancy was sought in a possibleoffset caused by mask dimension differences on the reticle. Thee-beam writing of the reticle is not necessarily identical as thepatterns related to both reticle positions are relatively far apart(a few mm). Moreover, the differences that are needed to ex-plain the observations (0.1% for 10/10 transistors) correspondto an offset on silicon of approximately 10 nm (or 40 nm onthe (4X) reticle). This is within the CD specifications of the ret-icles as used for this experiment. Nevertheless, this explanationhad to be abandoned as more transistor pairs from the same test

Fig. 11. Cumulative probability plots for current factor mismatch forN-channel (W=L = 2=1) transistors. Estimators: see Table IV.

TABLE IVMATCHING RESULTS FOR N-CHANNELW=L = 2=1 PAIRS

chip were investigated. Surprisingly it was found that these sys-tematic differences between the #1 and #2 reticle positions oc-curred for many pairs. Moreover, some pairs gave significantlylarger differences than others, seemingly without any consis-tency with respect to their dimensions and respective reticlepositions. A rather spectacular example of the systematic mis-match difference between the two reticle positions for n-channel

[ m/ m] pairs is shown in Fig. 11.The statistical estimators for the two current factor mismatch

distributions from Fig. 11 are summarized in Table IV. Thevalues between brackets again represent the statistical uncer-tainties due to the fairly limited sample size and were againestimated using the bootstrap technique.

These data were obtained using the original matching char-acterization algorithm without second measurement and inter-changing SMU3 and SMU4. As pointed out before, a system-atic mismatch of about 0.1% can be attributed to the offset of



Fig. 12. Photomicrograph of NC2/1 MOSFET matched pair (#1 reticleposition).

Fig. 13. Photomicrograph of NC2/1 MOSFET matched pair (#2 reticleposition).

the measurement system. However, in this case the two reticlepositions were measured alternating during one characterizationrun. This means that the systematic mismatch due to the systemcannot explain the difference between the systematic currentfactor mismatches of the two reticle positions. It will be evidentfrom Fig. 11 and Table IV that there is something quite pecu-liar with the matching of these devices. A closer look at the teststructures however, reveals an unexpected difference betweenthe two reticle positions (Figs. 12 and 13).

The two test structure realizations at the two reticle posi-tions are covered by different Metal-2 CMP dummy patterns.In essence the CMP dummy-filling algorithm of the chip-fin-ishing program causes this. This program starts by placing itsfirst square at a certain pattern (origin) point of the mask layer.Subsequently the program drops the dummy tiles at those pointswhere the filling of the particular mask layer is below a cer-tain density at a fixed grid. Obviously, the tiles are not allowedto interfere with the patterns already defined in the same layer.

Note for instance the (dark grey) Metal-1 dummy placement dif-ference between the transistors when comparing Fig. 4 (10/10transistors) and Fig. 12 (2/1 transistors). However, apparentlythe origin point is not the same for each mask layer and dummypattern, for the used dummy placement algorithm, which in thiscase results in slightly different Metal-2 dummy patterns for thetwo reticle positions.

As mentioned before, the process family that was used to fab-ricate these devices has in the past given matching problems dueto incomplete H passivation as well as mechanical stress offsetswhen transistors are covered with metal plates [6]. To avoid pos-sible problems, dummy tiles were removed (manually) wherethey coincided with a transistor. These seemingly arbitrary re-movals were intended to at least open-up paths for hydrogen todiffuse toward the transistors. Unfortunately (or perhaps fortu-nately!), this last-minute manual removal action resulted in asignificant environmental asymmetry between the two tran-sistors of the pairs. The asymmetries, resulting from these lastminute CMP dummy removals were recognized as they werecreated, be it that the extend of their impact came as an inter-esting surprise .

We demonstrated before in [6] that metal coverage can re-sult in significant matched pair asymmetries due to asymmetryof the (local) mechanical strain that can be caused by strained(ILD dielectric or Tungsten first metal) layers from the back-endprocess. Strain differences translate into mobility differences(and hence transconductance differences) through the piezo-re-sistance effect in silicon [6], [12]. That the systematic currentfactor mismatch difference between the #1 and #2 reticle posi-tions is due to mechanical strain was verified by checking thedistributions of the threshold voltage mismatch of these twopopulations. As no significant difference could be distinguishedbetween the threshold voltage distributions, we felt quite safe toconclude that we were indeed looking at a mobility related mis-match effect, although strictly speaking we realize that a com-plete proof of this conclusion is not given here. Further testsinvolving extensive back-end experiments and device (or sub-strate) orientation variations would be required to prove this.

Now let us go back to the much smaller, but nevertheless sta-tistically significant, median differences between Tables II andIII. Careful scrutiny of the 10/10 offset pair test structures in-deed reveals similar CMP dummy coverage asymmetries, be itless blatant than in the example of Figs. 11 and 12.

The careful reader of this paper will now understand the paththat this investigation followed. It was the initial histogram ofFig. 1, composed of the combined populations of the #1 and #2reticle positions, that initiated this work. The question whetherthe observed systematic mismatch component that was observedin Fig. 1 was due to the measurement algorithm or caused bythe process should be answered by: Both: We had to refine themeasurement method to get rid of measurement system inducedsystematic mismatches of the order of a few tenths of a percent,but after this we had to conclude that an unexpected mechan-ical strain related effect caused the major part of the observedsystematic mismatches. This work demonstrates that it is worth-while to improve mismatch measurement algorithms to an accu-racy level well below 0.1%. New mismatch effects are encoun-tered at these levels, which may originally seem small, but can



prove to be serious matching hazards in modern mixed-signalCMOS applications.

VII. CONCLUSIONThis study exemplifies the relevance of careful systematic

transconductance mismatch characterization. It demonstratesthat one cannot be careful enough in assuring identicality ofthe test structures (environment) as well as the characterizationhardware and measurement algorithms.

The paper discusses limits of MOSFET mismatch char-acterization. The commonly used CG/CS matched pair teststructure layout is discussed, together with the limitations of a(no switching matrix) parameter analyzer based measurementapproach.

By analyzing transistor pairs with intentional 1% and 1%dimensional offsets, limitations of the original measurement al-gorithm are established. Measurement algorithm improvementsare suggested and tested. These can bring the measurementsystem induced systematic transconductance mismatch con-tribution down to a level of the order of 0.01%, which opensup the possibility to study subtle sub 1% systematic mismatcheffects. As a demonstration of this improved characteriza-tion technique, a new systematic mismatch phenomenon isrevealed. It is shown that careless placement of the so-calledCMP dummy tiles can have significant detrimental effects onmatching of MOSFET transconductance.

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Hans P. Tuinhout received the M.Sc. degree in elec-trical engineering from the Delft University of Tech-nology, Delft, The Netherlands, in 1980.

Since then, he worked for the Philips ResearchLaboratories, Eindhoven, The Netherlands, onCMOS and BiCMOS process and device character-ization. His current research activities in the devicemodeling group at Philips Research are focused onaccurate dc parametric measurements, in particularfor characterizing statistical differences betweensupposedly identical (matched) IC components and

looking for techniques to interpret stochastic mismatch effects to improve per-formance and yield of digital and mixed signal integrated circuit technologies.

Maarten Vertregt (M89) received the M.Sc. degreein electrical engineering from the University ofTwente (UT), Enschede,The Netherlands, in 1985.

He started with Philips Research Laboratories,Eindhoven, The Netherlands, on the design of 1- and4-Mb SRAM memories. Subsequently, he worked onA/D conversion with embedded signal processing.Since 1996, he coordinates the design activitiesfor high-speed A/D conversion functions withinthe Mixed-Signal Circuits and Systems Group ofPhilips Research. His research interests are with the

migration of signal processing from the analog domain to the digital domain inrelation to both process technology scaling and new system demands.


mos mismatch caused by cmp metal

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