mosfet modeling for rf circuit design/mos-ak workshop 2004/sep.20 nobuyuki itoh/toshiba mosfet...

MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20Nobuyuki Itoh/Toshiba

MOSFET modeling for RF circuit design

Nobuyuki ItohSemiconductor Company

Toshiba Corporation


Recent Progress of MOSFET’s Performance

0.01

0.1

1

Siz

e [

um

]

Year

Design Rule

Minimum Gate Length

0.5um

0.35um

0.25um

0.18um

0.13um

90nm

65nm

45nm

30nm

0.20um

0.13um

70nm

50nm

30nm

20nm

15nm

90 95 00 05 10 1510

100

1000

1985 1990 1995 2000 2005 2010C

ut-

off

Fre

qu

en

cy [

GH

z]

Year

CMOS

BJT

CMOS VLSI Symp. 2004: fTmax=209GHz (Intel)fTmax=243GHz (IBM)

SiGe Bipolar BCTM 2004: fTmax=231GHz (Hitachi)fTmax=230GHz (ST micro)


Contents

STI STI

P-wellS/D Diffusion

Gate

Gate Insulator

N-well

P-sub

SiO2SiONFlicker Noise Increasing

STI StressFor Small Geometry

Device

Thermal Noise Increasing due to

Hot CarrierScalable Substrate

Network

VTH based modelor

Surface potential model


VTH based model or Surface potential model

STI STI

P-wellS/D Diffusion

Gate

Gate Insulator

N-well

P-sub

VTH based modelor

Surface potential model


Many Diff

erence

s

Two types of compact modelC

urr

en

t [A

] 2)( THgs VVI

)exp(T

THgs

mv

VVI

(a)

Vgs [V]

Drift current

Diffusion current

(b)

driftdiffds III

VT-Based Model(BSIM, MM9 etc.)

Surface Potential Model(HiSIM, EKV, MOS11 etc.)

By Ref.[1]


Difference btw simulation and measurement(1)

P

S

P

G

VkV

Vn

02

1

Large (W/L=10/10)

Short (W/L=10/0.14)

BSIM4

BSIM4

EKV

EKV Discontinuous!!

n-factor vs. Vgs


Difference btw simulation and measurement(2)

Large (W/L=10/10)

Short (W/L=10/0.14)

BSIM4

BSIM4

EKV

EKV

gm vs. ID


Basic analog characteristics

0.46

0.48

0.50

0.52

0.54

10-9 10-8 10-7 10-6 10-5 10-4 10-3

Cu

rren

t ra

tio

I bias [A]

BSIM4

EKV

By Ref.[2]


VTH based model or Surface potential model

Surface potential model seems better than VTH based model for analogue design.

but…

Surface potential model is not so popular right now


Flicker noise

STI STI

P-wellS/D Diffusion

Gate

Gate Insulator

N-well

P-sub

SiO2SiONFlicker Noise Increasing


Flicker Noise due to scaling

Scaling Thinner gate oxide Gate leakage increasing SiO2 to SiON

-150

-130

-110

-90

-70

-50

103 104 105 106 107

Ph

ase

nois

e [

dB

c/H

z]

Offset frequency [Hz]

3

1

f Flicker noise

2

1

fThermal noise

RF performance degradation

fWLC

KS

ggox

Fvg KF increasing

Flicker noise degradation

-160

-155

-150

-145

-140

-135

-130

102 103 104 105

Svd

[d

BV

/sq

rt(H

z)]

Frequency [Hz]

SiON

SiO2

↑

↓

~6dB

By Ref.[4]


Cause of flicker noise degradation

0

1

2

3

4

5

0 1 2 3 4 5Nit

rog

en

con

cen

trati

on

[%

]

Depth [nm]

Si substrateOxynitride

3.6X1014 atoms/cm2

1.6X1014

1.0X1014

Pure Oxide

N profile using NO annealing

10

10-9

Pure Ox

3.6X1014 atoms/cm2

1.8X1014 atoms/cm2

Svg

[V2 -m

2 /H

z]

Frequency [Hz]

10-11

10-13

10-15

10-17

100 1k 10k

N profile control is necessary!

Peak N density was large influence of flicker

noise

Peak is in Si surface

By Ref.[6]


N profile control

01234567

0 2 4 6 8 10N c

once

ntra

tion

[atm

.%]

depth [nm]

oxynitride Si-sub.

Vertical High Pressure (VHP) oxynitride process

By Ref.[4]

Remote-plasma nitridation

By Ref.[5]

104

Frequency (Hz)10

310

210-15

10-13

10-11

10-9

Svg

(V2 -m

2 /

Hz)

101

NO anneal

Nitrogen profile control

By Ref.[7]


Flicker noise

Flicker noise is always problem in recent scaled MOSFET

but…

It seems not problem for its modeling


STI stress

STI STI

P-wellS/D Diffusion

Gate

Gate Insulator

N-well

P-sub

STI StressFor Small Geometry

Device


STI Stress

Low Stress

High Stress

Electron mobility degradationHole mobility improvement

Mechanical Stress

By Ref.[8]


gm degradation due to STI stress

65.0

70.0

75.0

80.0

85.0

90.0

95.0

0 2 4 6 8 10 12

gm

.max [

mS

]

Gate finger width [m]

90nm Process w/Lg=70nm

0.13m Process w/Lg=0.11m

narrow channel eff ect

Wgtot

=100m

Low stressed gate

High stressed gate


Inverter performance due to STI stress

Mobility: largeCapacitance: small

Mobility: smallCapacitance: large

Mobility: smallCapacitance: small

Mobility: largeCapacitance: large

Stressed MOSFET Stress-free MOSFET

Which is better performance?


STI stress

STI stress was modeled by BSIM4.

but…

It is not confirmed practical layout yet.


Scalable substrate network

STI STI

P-wellS/D Diffusion

Gate

Gate Insulator

N-well

P-sub

Scalable Substrate Network


Normal BCIM3 model

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0.1 1 10 100

mag

Frequency [GHz]

real

imagmeasured

simulated

measured

simulated

-2.0

0.0

2.0

4.0

6.0

8.0

0.1 1 10 100m

ag

Frequency [GHz]

real

imag

measured simulated

measured

simulated

s11 s21


MOSFET’s Equivalent Circuit for RF

Gate

Drain

Source

Sub

WellBSIM3v3 model

Cgb

Rgb

Rsjsub

Rdjsub

Rp

Ddj

Dsj

Rg

To realize scalable model, device geometry has to keep scalability

)(

)(

2

1

,

,

fR

fR

WW

LL

gb

djsub

initgg

initgg

.

.

.

.

By Ref.[3]

Have to define target layout of MOEFETR is defined by distance btw channel to contact


Target Layout

NSUB

PSUB

……

……

NMOSFET

S D S D D S…

NWell

PWell

…

For Toshiba 0.13 m CMOS


Scalable Model (Lg dependence)

-15

-10

-5

0

5

10

15

0.1 1 10 100

s2

1m

ag

[d

B]

Frequency [GHz]

0.5m

0.35m

0.25m

s11

s22

s21

-60

-50

-40

-30

-20

-10

0

0.1 1 10 100

s1

2m

ag

[d

B]

Frequency [GHz]

0.5m0.35m0.25m

s12


Scalable Model (Wg dependence)

-60

-50

-40

-30

-20

-10

0

0.1 1 10 100

s1

2m

ag

[d

B]

Frequency [GHz]

50m

100m

200m

-15

-10

-5

0

5

10

15

0.1 1 10 100

s2

1m

ag

[d

B]

Frequency [GHz]

50m

100m

200m

s11

s22

s21

s12


Scalable Model (Vds dependence)

-10

-5

0

5

10

15

0.1 1 10 100

s2

1m

ag

[d

B]

Frequency [GHz]

Vds=2.5VVds=1.5V

Vds=1.0V

Vds=1.0V

Vds=1.5V

Vds=2.5V

-60

-50

-40

-30

-20

-10

0

0.1 1 10 100

s1

2m

ag

[d

B]

Frequency [GHz]

s11

s22

s21

s12


Scalable Model (Vgs dependence)

-10

-5

0

5

10

15

10-1 100 101 102

s2

1m

ag

[d

B]

Frequency [GHz]

Vgs=1.5V

Vgs=1.2V

Vgs=0.8V

-60

-50

-40

-30

-20

-10

0

0.1 1 10 100

s1

2m

ag

[d

B]

Frequency [GHz]

Vgs=0.8V

Vgs=1.2V

Vgs=1.5V

s11

s22

s21

s12


Scalable substrate network

Scalable substrate network was realized by in-house design tool.

but…

More accuracy and layout freedom is necessary


Thermal noise

STI STI

P-wellS/D Diffusion

Gate

Gate Insulator

N-well

P-sub

Thermal Noise Increasing due to

Hot Carrier


Expressions

thgsOX

g

gid VVC

L

WkTS 4

1

1

3

2 2

Linear Region =1 =1

Saturation Region =0 =2/3

Classical model

In the case of sub-micron MOSFET, is increasing due to hot carrier effect!

By Ref.[9]

dVVgLI

kTS

effDid

22

)(4

04 d

id

kTg

S

Recent model

Philips 1999

L

E

IQ

L

kTS

crit

Dinveff

effid

sinh

142 Infineon 2001

By Ref.[10]

By Ref.[11]


vs. Lg

0.0

1.0

2.0

3.0

4.0

5.0

6.0

0.01 0.10 1.00 10.00

Ref.10Ref.12Ref.13Ref.14Calculation

Gate Length [m]

In the case of sub-0.1-micron MOSFET, is larger than 4. 90nm 4.7 65nm 6.1in the estimation


Noise measurement for Sub-0.1-micron NMOS

Intrinsic device

Tuner Tuner

Network Analyzer

NoiseSource

NF meter

de-embeded capacitance by measurement gate resistance by calculation


Measurement data

1.0

2.0

3.0

4.0

5.0

1.00 2.00 3.00 4.00 5.00

0.04um0.06um0.07um0.11um

NF5

0 [

dB

]

Freqency [GHz]

Vds=1V, Wg=100m NF50:-NF50 is decrease due to small gate length.-But it has bottom at around Lg=70nm.-It may increasing dramatically


Empirical formula

0.0

1.0

2.0

3.0

4.0

5.0

6.0

0.01 0.10 1.00 10.00

Ref.10Ref.12Ref.13Ref.14This WorkCalculation

Gate Length [m]

=(K1+K

2sinh(L))/ L

eff

2

L

E

IQ

L

kTS

crit

Dinveff

effid

sinh

142

3

2sinh

1212

LKKLeff

Empirical equation


Difference between this work and others

0.0

1.0

2.0

3.0

4.0

5.0

6.0

0.01 0.10 1.00 10.00

Gate Length [m]


How affect to circuit performance estimation

LNA well known directly affect to circuit performance estimation

VCO Also affect to circuit performance estimation


VCO noise expression

Generate GenerateGenerate

Generate Generate

fggkTdi pdnddM )(2 ,0,0

2,

)(2 ,0,0 pdndGC ggF

20

22

4

eff

VCPi

CS kTR

KdvF

2

2 1

2

1

m

osc

osc

GMeffm V

FRkTL

iGM FF


Bipolar VCO

-140

-130

-120

-110

-100

-90

-80

-140 -130 -120 -110 -100 -90 -80

Calc

ula

ted

Ph

ase N

ois

e [

dB

c/

Hz]

Measured Phase Noise [dBc/ Hz]

Quit good correlation between measurement data and calculated data..

1MHz offset


Comparison of VCO noises

Adapt value which calculated by the empirical equation to several kinds of integrated MOSFET-VCO

=optimized:difference between measured and calculated is within +/- 2dB (average)

=0.67(fixed):difference between measured and calculated is large!

Need suitable value for thermal noise of MOSFET

-135

-130

-125

-135 -130 -125

Calc

ula

ted

Ph

ase N

ois

e [

dB

c/

Hz]

Measured Phase Noise [dBc/ Hz]

=0.67(fixed)

=optimized

1MHz offset


Summary

1. Surface potential model seems better than VTH based model for analog circuit design due to its continuous characteristics. It needs entire discussion which model has to be chosen.

2. Scalable substrate network model has already been realized for limited layout. But it might be need more layout freedom.

3. Flicker noise increasing of SiON gate insulator is problems for performance. But accuracy of model is not issue.

4. STI stress model has been not popular, yet. We need more experience.

5. Thermal noise model is still issue. is increasing due to scaling. It is the one of most important issues for RF analog designe.


Acknowledgments

Great Tanks to;

Dr. Sadayuki Yoshitomi

Ms. Hisayo S. Momose

Mr. Kenji Kojima

Mr. Tatsuya Ohguro

of Semiconductor Company, Toshiba Corporation


References

[1]. R.van Langevelde, et, al., "RF Performance and Modeling of CMOS Devices," Educational Sessions Workbook of CICC, September, 2003

[2]. M.Bucher, "Analytical MOS Transistor Modeling for Analog Circuit Simulation," The Doctor Thesis of EPFL, pp.140, Lausanne, 2000

[3]. N.Itoh, et. al., "Scalable Parasitic Components Model of CMOS for RF Circuit Design," IEICE Transaction of Fundamentals, vol. E86-A, No.2, pp.288-298, February, 2003.

[4]. H.Kimijima,et. al., "Improvement of 1/f noise by using VHP(Vertical High Pressure) oxynitride gate insulator for deep-sub micron RF and analog CMOS," Symp. VLSI Tech. Dig., pp.119-120, Kyoto, 1999.

[5]. M. Rodder et., al, SSDM 1998[6]. T.Ohguro, et. al., “The impact of oxynitride process, deuterium annealing and STI stress to 1/f noise of 0.11 m CMOS,”

Symp. VLSI Tech. Dig., 2003.[7]. T.Ohguro, et. al., “A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides,” Symp. VLSI Tech. Dig.,

2001.[8]. R.A.Bianchi, et. al., “Accurate Modeling of Trench Isolation Induced Mechanical Stress effects on MOSFET Electrical perfor

mance,” Proceedings of IEDM, 2002.[9]. Y.P. Tsividis, “Operation and Modeling of the MOS Transistor,” NewYork:McGraw-Hill, 1988.[10]. A.J.Scholten, et. al., “Accurate Thermal Noise Modeling for Deep-Submicron CMOS,” Proceedings of IEDM, 1999.[11]. G. Knoblinger, et. al., “A New Model for Thermal Channel Noise of Deep-Submicron MOSFETS and its Application in RF-C

MOS Design,” IEEE Journal of Solid-State Circuits, vol.36, No.5, pp.831-837, May, 2001.[12]. A.J.Scholten, et. al., “Compact modeling of drain and gate current for RF CMOS,” Proceedings of IEDM, pp129-132, 200

2.[13]. G. Knoblinger, et. al., “Thermal Channel Noise of Quarter and Sub-Quarter Micron NMOS FET’s,” Proceedings of ICMTS, p

p95-98, 2000.[14]. A.A. Abidi, “High-frequency noise measurements on FETs with small dimensions,” IEEE Trans. Electron Devices, vol.ED-3

3, pp1801-1805, Nov., 1986.

mosfet modeling for rf circuit design/mos-ak workshop 2004/sep.20 nobuyuki itoh/toshiba mosfet...

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