mosis service silicon photonics mpw access...oct 20, 2015 · mosis –summary by choosing mosis as...
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MOSIS Service Silicon Photonics MPW Access
Russ PiñaNankyung (Nan) Cockerham
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Multi-Project Wafer Service
Shared costs: mask, wafer, and foundry and packager interfaceMulti-project reticle
~ 50 different designs
Many designs on single die; cost to customer is approximately in direct proportion to area used
Your Chip
Is Here
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History and Capabilities
� Started by DARPA in 1981, to reduce the costs of prototype fabrication to their research community• Over 60,000 user designs managed
� Capabilities• People : Dedicated team for design, layout, test, packaging,
modeling, customer support, etc.• Test lab : Parametric test systems, 200 mm and 300 mm fully
automated wafer probers, etc.• Computing : High-capacity servers for design checking, pre-
fabrication processing• Software : Automated 24/7 web-based design submission and fully
automated layout checking, project status tracking
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Operations
MOSIS: Low-Cost Semiconductor Prototyping and Small-Volume Production Service
Low-Volume Circuit Designers-- Startup, Commercial,
Defense, University, etc.
Since 1981ITAR – USA VendorsDMEA Accredited/Trusted
• Design Kits, Doc• Design Check• Technical Q’s• Prototypes/Small Prod.• Flexibility on Die Size
Leading Foundry Access• Small Lots, Multi-Project Runs• TSMC, Global Foundries, …• CMOS, RFSOI, SiGe, Photonics
Dicing + Packaging• Flip-Chip, Plastic, …
ProcessMonitoring• In situ circuits
Circuit Designs
User Support
Cost-Effective Prototype and Small-Volume Chips
> 60,000 Completed Projects
Wafer + Device Testing• Parametric, Functional
MOSIS provides all these services to the Integrated Circuit design and fabrication community with integrated seamless interfaces
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MOSIS Customer Base
� Large/Medium Size firms (Fabless or IDMs)• Require leading-edge technologies not available in house• Require low-cost prototyping option
� Fabless semiconductor startups• Limited financial resources• Emerging market sectors requiring leading edge technologies
� Companies with DoD funding• Require leading-edge technologies, with USA source• Optional support for ITAR, Trusted designs
� Universities• Research and education
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Current Foundry Partners
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Silicon Photonics MPW Service
� In-House Expertise in Silicon Photonics� Involvement in U.S. National Photonics
Activities�Quick Response to Design Submission Issues�U.S. Based� Support During U.S. Work Day� Simplified PO Process
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IMEC Design Kit Access
MOSIS Customer Account
Submit Vendor Document Access
Complete MOSIS-imec DKLA
Access Design Kit via MOSIS Secure Document Server
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Process Options
ISIPP25G+: • Each order includes 20 duplicate dies• Extra dies can be purchased• Choice of implants• User metrology
PSV: • Each order includes 25 duplicate dies• Extra dies can be purchased• Choice of cladding (top oxide, side oxide, air)• Choice of Lithography dose (standard, high)• User metrology
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MPW Runs 2015
Technology ISIPP25G+ PSVRegistration 19-Oct-15 16-Nov-15DRC clean Deadline 16-Nov-15 30-Nov-15Estimated Ship Date May 2016 April 2016
Refer to MOSIS website for updates and status of these MPW runs:https://www.mosis.com/vendors/view/imec
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MOSIS Contact Information
• Website: www.mosis.com• Contacts:
– Wes Hansford, Director– Russ Piña, Engineering Manager– Nankyung (Nan) Suh Cockerham, Silicon Photonics Scientist
• [email protected]• 310-448-9400• Customer Support
– https://www.mosis.com/pages/account-login
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GFUS 7RFSOI for Photonics IC
Nan Cockerham – MOSISOctober 2015
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Options for Silicon Photonics
� Heterogeneous: III-V Actives + Silicon Passives• Leverage advantages of both processes
� Hybrid: Specialized SOI process without Electronics• Si photonics process offered by IMEC and IME
� Monolithic: Specialized SOI process with Electronics• 90 nm CMOS9WG process
� Standard SOI CMOS• GFUS (formerly IBM) 45 nm and 32 nm SOI process• GFUS (formerly IBM) 180 nm 7RFSOI process
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GF CSOI7RF Process Overview
� CSOI7RF Technology Details• 180 nm CMOS7RF based SOI technology• 7RF 1.5V and 2.5V FETs (1.5V as option, 2.5V as base)• 3-7 levels of metal (4 µm Al last metal)
� Wafer: SOI with 145 nm top silicon layer, 1 µm BOX on 1000 ohm-cm high resistivity silicon substrate to minimize the capacitive coupling to substrate
� Provides a base technology for RF switch designs for various wireless applications
� Competitive cost and performance solution to GaAs pHEMTand SOS technologies
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7RFSOI for Si Photonics
� Interweaving opto-electronic devices in a potential low cost production silicon process platform
� Realization of photonic functions next to CMOS transistors enables• More functions in complex electro-optical integrated systems• Improvement of photonic functions (or imperfections)
� Utilize photonics to enhance the performance of electronic IC• On-chip or chip-to-chip optical interconnects• Optical delays for radio-frequency filters, phased arrays, etc.
� Photonic device fabrication in 7RFSOI • Passive components (waveguides, delay lines, Y-junctions, couplers, grating couplers) • Active component
9 Forward and reversed biased p-n traveling wave and ring modulators 9 Thermal modulators 9 Photodiodes: on-chip metal-silicon, off-chip (packaging)
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Photonics in Unmodified CMOS
Lee, B.G.; Plouchart, J.; Rylyakov, A.V.; Jeong Hwan Song; Doany, F.E.; Schow, C.L., "Passive Photonics in an Unmodified CMOS Technology With No Post-Processing Required," in Photonics Technology Letters, IEEE , vol.25, no.4, pp.393-396, Feb.15, 2013
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Monolithic 8 x 8 OPA Transceiver
Hooman Abediasl, Hossein Hashemi, "Monolithic optical phased-array transceiver in a standard SOI CMOS process," Opt. Express 23, 6509-6519 (2015); http://www.opticsinfobase.org/oe/abstract.cfm?uri=oe-23-5-6509
� 180 nm GF 7RFSOI CMOS process
� Over 300 distinct optical components
� Over 74,000 distinct electrical components
� Optical Phased Array (OPA) consists of 64 optical variable thermo-optical tunable phase shifters, attenuators, nano-antennas
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MOSIS – Summary
By choosing MOSIS as their partner, customers speed their route to commercialization via:
• Access to broad range of production services9 MPWs -> Low Volume Production (50-500+ wafers)9 Foundry/Test/Packaging + can leverage network of IP/Design partners
• Expert interface to manage the business transactions9 NDAs/Design Kits/Invoices/shipping etc
• Strong technical support9 Over 30 years of experience (60,000 designs managed)9 Can provide direct answers to 98% of technical questions
• Close working relationship with imec9 Regular review meetings (e.g., quickly resolve technical issues)