mp_arm_ti_softcore.ppt

ARMProcesorové jadrá a procesory architektúry

WHAT IS ZIGBEE

Technological standard created for control and sensor networks

Based on the IEEE 802.15.4 standard Wireless personal area networks(WPANs) High level communication Frequency band up to 2.4GHz

ZIGBEE GENERAL CHARACTERISTICS

Data rates of 20 kbps and up to 250 kbps Support for Low Latency Devices CSMA-CA Channel Access Low Power Usage consumption 3 Frequencies bands with 27 channels Extremely low duty-cycle (<0.1%) Supports large number of nodes Very long battery life

ZIGBEE PROTOCOL STACK ARCHITECTURE

Defined in zigbee specification

Defined in 802.15.4 standard

PHY LAYER TASKS

MODES IN MAC LAYER

SUPER FRAME

NETWORK DEVICES

DATA TRANSFER MODELS

Peer to peerStar

mesh

Communication Mechanisms-I

Communication Mechanisms-II

Network layer

APPLICATION LAYER

ZIGBEE ROUTING IN A MESH NETWORK

S

aC

T

D

Discard route request B

UnicastBroadcastWithout routing capacity

Enabling the ARM Learning in INDIA

LPC2148 Programming

Using BLUEBOARD


AGENDA LPC214x Block Diagram Pin Diagram BlueBoard Schematic PIN Select Block General Purpose Input/Output First Program

Bus Structure


In LPC2148 three types of busses are used to connect the core with other peripherals on chip.

1. Local Bus to connect the onchip memory controllers and fast GPIO’s2. AMBA Advance High Performance Bus (AHB) for interrupt controller3. VLSI Peripheral Bus (VPB) for other onchip peripherals.

AHB acts as a bridge for VPB.VPB is mainly meant for connect slower peripherals then that of processor.VPB can dive the peripherals at ¼ CPU clock frequency.

Bus Structure


Memory MAP


To access any peripheral we need its address. The entire address space can be divided in to several sections.

Memory MAP


Memory Access Module


The MAM block in the LPC2148 maximizes the performance of the ARMprocessor when it is running code in Flash memory,

Two general methods for achieving code execution performance.Using RAM for code execution.Using Cache memory.

Memory Access Module


The MAM block in the LPC2148

Bootloader


A small piece of software executed after every reset. This software is used toload the new user program in to the flash memory using any communication channel like UART, USB, Ethernet or CAN.

For LPC2000 Series the Bootlader can be activated by maintaining low level on P0.14 while reset.

Bootloader


ISP

Philips microcontroller have a great feature called ISP (In System

Programming).

It enables the user to flash the microcontroller with an ease. In LPC2148 the ISP

mode can be activated by maintaining low level on P0.14 while reset.

Boot Process


ISP Commands


IAP


In-Application (IAP) programming is performing erase and write operation on the on-chip flash memory, as directed by the end-user application code.The bootloader code provides API to access flash memory from the user program. The API are called using their codes.

IAP Command Command Code in DecimalsPrepare sector(s) for write operation 50

Copy RAM to Flash 51

Erase sector(s) 52

Blank check sector(s) 53

Read Part ID 54

Read Boot code version 55

Compare 56

Reinvoke ISP 57

Phased Lock Loop


PLL is a closed loop control system to generate high frequency by multiplyingwith given factor to the input frequency.

Div

FoutFin

Basic PLL Block Diagram

Mul

In LPC2148 microcontrollers there are 2 PLLs which provides programmable frequencies to the CPU and USB system.The input clock frequency to PLL0 and PLL1 is in the range of 10MHz to 25 MHz only. It is multiplied up the range of 10MHz to 60MHz for CCLK and 48MHz for the USB cock using Current Controlled Oscillator (CCO).

PLL Programming


PLL RegistersGen. Name Description PLL0 PLL1

PLLCON PLL Control Register. Holding register forupdating PLL control bits

0xE01F C080PLL0CON

0xE01F C0A0PLL1CON

PLLCFG PLL Configuration Register. Holding register forupdating PLL configuration values

0 0xE01F C084PLL0CFG

0xE01F C0A4PLL1CFG

PLLSTAT PLL Status Register. Read-back register for PLLcontrol and configuration information

0xE01F C088PLL0STAT

0xE01F C0A8PLL1STAT

PLLFEED PLL Feed Register. This register enablesloading of the PLL control and configurationinformation from the PLLCON and PLLCFGregisters into the shadow registers that actuallyaffect PLL operation.

0xE01F C08CPLL0FEED

0xE01F C0ACPLL1FEED

Detail Register Bits LPC214X User Manual Page 27

PLL Programming


Programming Steps:1. Select the desired operating frequency for your system ( Processor operating frequency) CCLK.2. Check the oscillator connected to the controller on board. (FOSC) 3. Calculate the value of PLL multiplier “M”. CCLK = M × FOSC4. Find the value of PLL Divider “P” in such a way that is in the range of 156 MHz

to 320 MHz. 156 < FCCO < 320 = CCLK x 2 x P5. Write the values PLLCON and PLLCFG.6. Write the PLLFEED Values 0xAA and 0x55.7. Wait for PLL to lock.8. Connect the PLL.

VBP Divider


VLSI Bus connected to various peripherals can be operated at different speeds using the VBP Divider.

The VPB Divider serves two purposes: 1. Provides peripherals with desired PCLK via VPB bus, the VPB bus may be slowed down to one half or one fourth of the processor clock rate 2. VPB Divider allow power savings when an application does not require any peripherals to run at the full processor rate.

VBP Divider


VPBDIV registers least 2 significant bits can be changed for desired PCLK Peripherals on LPC2000 series can run at the full 60 MHz clock.

POWER CONTROL


LPC214x support two reduced power modes Idle mode and Power-down mode.

Idle Mode: The CPU stops execution is suspended until a Reset or Interrupt from peripheral occurs. Peripheral runs in idle mode and may generate interrupts to resume the CPU execution.

Power-Down Mode: The oscillator is shutdown and the chip receives no internal clocks. All the information of current execution state is preserved in this mode. A Reset signal or External Interrupt can terminate the power-down mode.

PCON Register:Bit 0 : When set to 1, causes the processor clock to be stopped.Bit 1 : When set to 1, causes the on-chip clock to be stopped.

In LPC214x the power down mode have dependency on USB Block

Peripheral Power Control


LPC2000 peripherals can be turned of individually using the PCONP Register bits setting,

to save the power. Few peripherals like GPIO, Watchdog timer, Pin connect block and System Control block

cannot be turned off. After reset the PCONP contains the value to enable all peripherals, so no need to

configure PCONP bits in-order to use any peripheral.

Page 37 LPC2148 User Manual

INTERRUPT SYSTEM


Interrupt System

• ARM PrimeCell™ Vectored Interrupt Controller

• 32 interrupt request inputs

• 16 vectored IRQ interrupts

• 16 priority levels dynamically assigned to interrupt requests

• Software interrupt generation


?

ZIGBEE GENERAL CHARACTERISTICS

Data rates of 20 kbps and up to 250 kbps Support for Low Latency Devices CSMA-CA Channel Access Low Power Usage consumption 3 Frequencies bands with 27 channels Extremely low duty-cycle (<0.1%) Supports large number of nodes Very long battery life

The ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings.

It was known as the Advanced RISC Machine.

ARM

Licencable architecture Companies that are currently or formerly

ARM licensees include Alcatel, Apple Inc., Atmel, Broadcom,

Cirrus Logic, Digital Equipment Corporation, Freescale, Intel (through DEC), LG, Marvell Technology Group, NEC, NVIDIA, NXP (previously Philips), Oki, Qualcomm, Samsung, Sharp, ST Microelectronics, Symbios Logic, Texas Instruments, VLSI Technology, Yamaha and ZiiLABS

ARM 7 applications

ARM9 applications

ARM11 applications

ARM CortexM applications• Dell E4300

Latitude Laptop• instant boot-up

for users and access to select applications, with multi-day battery lifetimes

ARM CortexA applications

ARM CortexR

Architectures overview

ARM7 (ARM7-TDMI-S)

ARM7TDMI-S

NXPLPC2148

LPC2148 development board

Development board schematic

ARM CortexR

TI MSP430Texas Instruments

MSP430 Mixed-signal microcontroller family 16-bit CPU Low cost, low power consumption Metering, wireless radio frequency

engineering (RF), battery-powered applications

MSP430x1xx - MSP430x5xx Series

MSP430 Architecture Von Neumann architecture 16 x 16bit registers (including PC, SP,

SR, constant generator) Simple instruction set 20bit address extension

Peripherals General-puropose I/O Analog-to-Digital Converter Brown Out Reset Comparator A, A+ Digital-to-Analog Converter Timers Direct Memory Access Controller ESP430 (integrated in FE42xx devices) LCD/LCD_A/LCD_B Op Amps Hardware multiplier

Programmable hardware in microcomputer systems

Programmable hardware Various sizes, technologies Customized hardware architectures Effective computing Customizable systems Backward compatibility insurance Reconfigurable systems Fault recovery / remote repair

Embedded architectures Main module

Specialized architecture Soft-core processor + peripherals

Coprocessor / Additional device Serial bus System bus External communication interface GPIO

Soft-core processors TSK3000A, MicroBlaze, Nios II,

OpenRISC ... Customizable, selectable features Suited for programmable chip

imlementations Various possibilities of use – worth

discussion

mp_arm_ti_softcore.ppt

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