mpc5604b/c microcontroller reference...

MPC5604B/C Microcontroller Reference Manual, Rev. 7

Freescale Semiconductor 1

MPC5604B/C MicrocontrollerReference Manual

Devices Supported:MPC5602BMPC5602CMPC5603BMPC5603CMPC5604BMPC5604C

MPC5604BCRMRev. 7

23 Jul 2010


2 Freescale Semiconductor



Chapter 1Overview

1.1 Introduction .....................................................................................................................................291.2 Features ...........................................................................................................................................29

1.2.1 MPC5604B family comparison ......................................................................................291.2.2 Block diagram ................................................................................................................321.2.3 Chip-level features ..........................................................................................................33

1.3 Packages ..........................................................................................................................................341.4 Developer support ...........................................................................................................................341.5 MPC5604B memory map ................................................................................................................34

Chapter 2Signal description

2.1 Introduction .....................................................................................................................................392.2 Package pinouts ...............................................................................................................................402.3 Pad configuration during reset phases .............................................................................................422.4 Voltage supply pins .........................................................................................................................432.5 Pad types .........................................................................................................................................432.6 System pins .....................................................................................................................................442.7 Functional ports A, B, C, D, E, F, G, H ...........................................................................................452.8 Nexus 2+ pins ..................................................................................................................................67

Chapter 3Clock description

3.1 Clock architecture ...........................................................................................................................693.2 Clock gating ....................................................................................................................................703.3 Fast external crystal oscillator (FXOSC) digital interface ..............................................................71

3.3.1 Main features ..................................................................................................................713.3.2 Functional description ....................................................................................................713.3.3 Register description ........................................................................................................73

3.4 Slow external crystal oscillator (SXOSC) digital interface ............................................................743.4.1 Introduction ....................................................................................................................743.4.2 Main features ..................................................................................................................743.4.3 Functional description ....................................................................................................743.4.4 Register description ........................................................................................................75

3.5 Slow internal RC oscillator (SIRC) digital interface ......................................................................763.5.1 Introduction ....................................................................................................................763.5.2 Functional description ....................................................................................................763.5.3 Register description ........................................................................................................77

3.6 Fast internal RC oscillator (FIRC) digital interface ........................................................................783.6.1 Introduction ....................................................................................................................783.6.2 Functional description ....................................................................................................783.6.3 Register description ........................................................................................................79

3.7 Frequency-modulated phase-locked loop (FMPLL) .......................................................................793.7.1 Introduction ....................................................................................................................79



3.7.2 Overview ........................................................................................................................803.7.3 Features ...........................................................................................................................803.7.4 Memory map ..................................................................................................................813.7.5 Register description ........................................................................................................81

3.7.5.1 Control Register (CR) ......................................................................................813.7.5.2 Modulation Register (MR) ...............................................................................84

3.7.6 Functional description ....................................................................................................853.7.6.1 Normal mode ....................................................................................................853.7.6.2 Progressive clock switching .............................................................................853.7.6.3 Normal mode with frequency modulation .......................................................863.7.6.4 Powerdown mode .............................................................................................87

3.7.7 Recommendations ..........................................................................................................873.8 Clock monitor unit (CMU) ..............................................................................................................87

3.8.1 Introduction ....................................................................................................................873.8.2 Main features ..................................................................................................................883.8.3 Block diagram ................................................................................................................883.8.4 Functional description ....................................................................................................89

3.8.4.1 Crystal clock monitor .......................................................................................903.8.4.2 FMPLL clock monitor .....................................................................................903.8.4.3 Frequency meter ...............................................................................................91

3.8.5 Memory map and register description ............................................................................913.8.5.1 Control Status Register (CMU_CSR) ..............................................................923.8.5.2 Frequency Display Register (CMU_FDR) ......................................................933.8.5.3 High Frequency Reference Register FMPLL (CMU_HFREFR) ....................933.8.5.4 Low Frequency Reference Register FMPLL (CMU_LFREFR) ......................943.8.5.5 Interrupt Status Register (CMU_ISR) ..............................................................943.8.5.6 Measurement Duration Register (CMU_MDR) ..............................................95

3.8.6 Register map ...................................................................................................................95

Chapter 4Clock Generation Module (MC_CGM)

4.1 Overview .........................................................................................................................................974.2 Features ...........................................................................................................................................984.3 Modes of Operation .........................................................................................................................99

4.3.1 Normal and Reset Modes of Operation ..........................................................................994.4 External Signal Description ............................................................................................................994.5 Memory Map and Register Definition ............................................................................................99

4.5.1 Register Descriptions ....................................................................................................1034.5.1.1 Output Clock Enable Register (CGM_OC_EN) ............................................1044.5.1.2 Output Clock Division Select Register (CGM_OCDS_SC) ..........................1044.5.1.3 System Clock Select Status Register (CGM_SC_SS) ...................................1054.5.1.4 System Clock Divider Configuration Registers (CGM_SC_DC02) ..........106

4.6 Functional Description ..................................................................................................................1074.6.1 System Clock Generation .............................................................................................107

4.6.1.1 System Clock Source Selection .....................................................................107



4.6.1.2 System Clock Disable ....................................................................................1074.6.1.3 System Clock Dividers ...................................................................................1074.6.1.4 Dividers Functional Description ....................................................................107

4.6.2 Output Clock Multiplexing ...........................................................................................1084.6.3 Output Clock Division Selection ..................................................................................109

Chapter 5Mode Entry Module (MC_ME)

5.1 Introduction ...................................................................................................................................1115.1.1 Overview ......................................................................................................................1115.1.2 Features .........................................................................................................................1135.1.3 Modes of Operation ......................................................................................................113

5.2 External Signal Description ..........................................................................................................1145.3 Memory Map and Register Definition ..........................................................................................114

5.3.1 Register Description .....................................................................................................1225.3.1.1 Global Status Register (ME_GS) ...................................................................1225.3.1.2 Mode Control Register (ME_MCTL) ............................................................1245.3.1.3 Mode Enable Register (ME_ME) ..................................................................1255.3.1.4 Interrupt Status Register (ME_IS) .................................................................1275.3.1.5 Interrupt Mask Register (ME_IM) .................................................................1285.3.1.6 Invalid Mode Transition Status Register (ME_IMTS) ..................................1295.3.1.7 Debug Mode Transition Status Register (ME_DMTS) ..................................1305.3.1.8 RESET Mode Configuration Register (ME_RESET_MC) ..........................1325.3.1.9 TEST Mode Configuration Register (ME_TEST_MC) ................................1335.3.1.10 SAFE Mode Configuration Register (ME_SAFE_MC) ...............................1335.3.1.11 DRUN Mode Configuration Register (ME_DRUN_MC) .............................1345.3.1.12 RUN03 Mode Configuration Registers (ME_RUN03_MC) .................1355.3.1.13 HALT0 Mode Configuration Register (ME_HALT0_MC) ...........................1355.3.1.14 STOP0 Mode Configuration Register (ME_STOP0_MC) ...........................1365.3.1.15 STANDBY0 Mode Configuration Register (ME_STANDBY0_MC) ..........1365.3.1.16 Peripheral Status Register 0 (ME_PS0) .........................................................1385.3.1.17 Peripheral Status Register 1 (ME_PS1) .........................................................1395.3.1.18 Peripheral Status Register 2 (ME_PS2) .........................................................1395.3.1.19 Peripheral Status Register 3 (ME_PS3) .........................................................1405.3.1.20 Run Peripheral Configuration Registers (ME_RUN_PC07) .....................1405.3.1.21 Low-Power Peripheral Configuration Registers (ME_LP_PC07) .............1415.3.1.22 Peripheral Control Registers (ME_PCTL0143) .........................................142

5.4 Functional Description ..................................................................................................................1435.4.1 Mode Transition Request ..............................................................................................1435.4.2 Modes Details ...............................................................................................................144

5.4.2.1 RESET Mode ................................................................................................1445.4.2.2 DRUN Mode ..................................................................................................1455.4.2.3 SAFE Mode ...................................................................................................1455.4.2.4 TEST Mode ...................................................................................................1465.4.2.5 RUN03 Modes ...........................................................................................147



5.4.2.6 HALT0 Mode .................................................................................................1475.4.2.7 STOP0 Mode ................................................................................................1485.4.2.8 STANDBY0 Mode .........................................................................................148

5.4.3 Mode Transition Process ..............................................................................................1495.4.3.1 Target Mode Request .....................................................................................1495.4.3.2 Target Mode Configuration Loading .............................................................1505.4.3.3 Peripheral Clocks Disable ..............................................................................1515.4.3.4 Processor Low-Power Mode Entry ................................................................1515.4.3.5 Processor and System Memory Clock Disable ..............................................1515.4.3.6 Clock Sources Switch-On ..............................................................................1525.4.3.7 Main Voltage Regulator Switch-On ...............................................................1525.4.3.8 Flash Modules Switch-On ..............................................................................1525.4.3.9 FMPLL Switch-On ........................................................................................1535.4.3.10 Power Domain #2 Switch-On ........................................................................1535.4.3.11 Pad Outputs-On ..............................................................................................1535.4.3.12 Peripheral Clocks Enable ...............................................................................1535.4.3.13 Processor and Memory Clock Enable ............................................................1535.4.3.14 Processor Low-Power Mode Exit ..................................................................1545.4.3.15 System Clock Switching ................................................................................1545.4.3.16 Power Domain #2 Switch-Off ........................................................................1555.4.3.17 Pad Switch-Off ...............................................................................................1555.4.3.18 FMPLL Switch-Off ........................................................................................1565.4.3.19 Clock Sources Switch-Off ..............................................................................1565.4.3.20 Flash Switch-Off ............................................................................................1565.4.3.21 Main Voltage Regulator Switch-Off ..............................................................1565.4.3.22 Current Mode Update .....................................................................................157

5.4.4 Protection of Mode Configuration Registers ................................................................1595.4.5 Mode Transition Interrupts ...........................................................................................159

5.4.5.1 Invalid Mode Configuration Interrupt ............................................................1595.4.5.2 Invalid Mode Transition Interrupt ..................................................................1605.4.5.3 SAFE Mode Transition Interrupt ...................................................................1615.4.5.4 Mode Transition Complete interrupt ..............................................................161

5.4.6 Peripheral Clock Gating ...............................................................................................1615.4.7 Application Example ....................................................................................................162

Chapter 6Boot Assist Module (BAM)

6.1 Overview .......................................................................................................................................1656.1.1 Features .........................................................................................................................1656.1.2 Boot modes ...................................................................................................................165

6.2 Memory map .................................................................................................................................1656.3 Functional description ...................................................................................................................166

6.3.1 Entering boot modes .....................................................................................................1666.3.2 Reset Configuration Half Word Source (RCHW) ........................................................1676.3.3 Single chip boot mode ..................................................................................................168



6.3.3.1 Boot and alternate boot ..................................................................................1696.3.4 Boot through BAM .......................................................................................................169

6.3.4.1 Executing BAM .............................................................................................1696.3.4.2 BAM software flow .......................................................................................1696.3.4.3 BAM resources ..............................................................................................1716.3.4.4 Download and execute the new code .............................................................1726.3.4.5 Download 64-bit password and password check ...........................................1726.3.4.6 Download start address, VLE bit and code size .............................................1736.3.4.7 Download data ...............................................................................................1746.3.4.8 Execute code ..................................................................................................174

6.3.5 Boot from UART ..........................................................................................................1756.3.5.1 Configuration .................................................................................................1756.3.5.2 Protocol ..........................................................................................................175

6.3.6 Boot from FlexCAN .....................................................................................................1766.3.6.1 Configuration .................................................................................................1766.3.6.2 Protocol ..........................................................................................................176

6.3.7 Interrupts .......................................................................................................................177

Chapter 7Reset Generation Module (MC_RGM)

7.1 Introduction ...................................................................................................................................1797.1.1 Overview ......................................................................................................................1797.1.2 Features .........................................................................................................................1807.1.3 Modes of Operation ......................................................................................................181

7.2 External Signal Description ..........................................................................................................1827.3 Memory Map and Register Definition ..........................................................................................182

7.3.1 Register Descriptions ....................................................................................................1847.3.1.1 Functional Event Status Register (RGM_FES) ..............................................1857.3.1.2 Destructive Event Status Register (RGM_DES) ............................................1867.3.1.3 Functional Event Reset Disable Register (RGM_FERD) ..............................1877.3.1.4 Destructive Event Reset Disable Register (RGM_DERD) ............................1897.3.1.5 Functional Event Alternate Request Register (RGM_FEAR) .......................1907.3.1.6 Destructive Event Alternate Request Register (RGM_DEAR) .....................1917.3.1.7 Functional Event Short Sequence Register (RGM_FESS) ............................1927.3.1.8 STANDBY0 Reset Sequence Register (RGM_STDBY) ...............................1947.3.1.9 Functional Bidirectional Reset Enable Register (RGM_FBRE) ....................194

7.4 Functional Description ..................................................................................................................1957.4.1 Reset State Machine .....................................................................................................195

7.4.1.1 PHASE0 Phase ..............................................................................................1977.4.1.2 PHASE1 Phase ..............................................................................................1987.4.1.3 PHASE2 Phase ..............................................................................................1987.4.1.4 PHASE3 Phase ..............................................................................................1987.4.1.5 IDLE Phase ....................................................................................................198

7.4.2 Destructive Resets ........................................................................................................1997.4.3 External Reset ...............................................................................................................199



7.4.4 Functional Resets ..........................................................................................................2007.4.5 STANDBY0 Entry Sequence .......................................................................................2007.4.6 Alternate Event Generation ..........................................................................................2007.4.7 Boot Mode Capturing ...................................................................................................201

Chapter 8System Integration Unit Lite (SIUL)

8.1 Introduction ...................................................................................................................................2038.2 Overview .......................................................................................................................................2038.3 Features .........................................................................................................................................2058.4 External signal description ............................................................................................................205

8.4.1 Detailed signal descriptions ..........................................................................................2068.4.1.1 General-purpose I/O pins (GPIO[0:122]) ......................................................2068.4.1.2 External interrupt request input pins (EIRQ[0:15]) .......................................206

8.5 Memory map and register description ...........................................................................................2078.5.1 SIUL memory map .......................................................................................................2078.5.2 Register protection ........................................................................................................2088.5.3 Register description ......................................................................................................209

8.5.3.1 MCU ID Register #1 (MIDR1) ......................................................................2098.5.3.2 MCU ID Register #2 (MIDR2) ......................................................................2108.5.3.3 Interrupt Status Flag Register (ISR) ...............................................................2118.5.3.4 Interrupt Request Enable Register (IRER) .....................................................2128.5.3.5 Interrupt Rising-Edge Event Enable Register (IREER) .................................2128.5.3.6 Interrupt Falling-Edge Event Enable Register (IFEER) ................................2138.5.3.7 Interrupt Filter Enable Register (IFER) .........................................................2148.5.3.8 Pad Configuration Registers (PCR0PCR122) ..............................................2148.5.3.9 Pad Selection for Multiplexed Inputs Registers (PSMI0_3PSMI28_31) ....2178.5.3.10 GPIO Pad Data Output Registers (GPDO0_3GPDO120_123) ...................2208.5.3.11 GPIO Pad Data Input Registers (GPDI0_3GPDI120_123) .........................2208.5.3.12 Parallel GPIO Pad Data Out Registers (PGPDO0 PGPDO3) .....................2218.5.3.13 Parallel GPIO Pad Data In Registers (PGPDI0 PGPDI3) ...........................2228.5.3.14 Masked Parallel GPIO Pad Data Out Register (MPGPDO0MPGPDO7) ....2238.5.3.15 Interrupt Filter Maximum Counter Registers (IFMC0IFMC15) .................2248.5.3.16 Interrupt Filter Clock Prescaler Register (IFCPR) .........................................225

8.6 Functional description ...................................................................................................................2268.6.1 Pad control ....................................................................................................................2268.6.2 General purpose input and output pads (GPIO) ...........................................................2268.6.3 External interrupts ........................................................................................................227

8.7 Pin muxing ....................................................................................................................................228

Chapter 9Power Control Unit (MC_PCU)

9.1 Introduction ...................................................................................................................................2299.1.1 Overview ......................................................................................................................2299.1.2 Features .........................................................................................................................230



9.1.3 Modes of Operation ......................................................................................................2309.2 External Signal Description ..........................................................................................................2319.3 Memory Map and Register Definition ..........................................................................................231

9.3.1 Register Descriptions ....................................................................................................2329.3.1.1 Power Domain #0 Configuration Register (PCU_PCONF0) ........................2339.3.1.2 Power Domain #1 Configuration Register (PCU_PCONF1) ........................2349.3.1.3 Power Domain #2 Configuration Register (PCU_PCONF2) ........................2359.3.1.4 Power Domain Status Register (PCU_PSTAT) ..............................................235

9.4 Functional Description ..................................................................................................................2369.4.1 General .........................................................................................................................2369.4.2 Reset / Power-On Reset ................................................................................................2369.4.3 MC_PCU Configuration ...............................................................................................2369.4.4 Mode Transitions ..........................................................................................................236

9.4.4.1 DRUN, SAFE, TEST, RUN03, HALT0, and STOP0 Mode Transition ..2369.4.4.2 STANDBY0 Mode Transition .......................................................................2379.4.4.3 Power Saving for Memories During STANDBY0 Mode ..............................238

9.5 Initialization Information ..............................................................................................................2399.6 Application Information ................................................................................................................239

9.6.1 STANDBY0 Mode Considerations ..............................................................................239

Chapter 10Interrupt Controller (INTC)

10.1 Introduction ...................................................................................................................................24110.2 Features .........................................................................................................................................24110.3 Block diagram ...............................................................................................................................24210.4 Modes of operation ........................................................................................................................243

10.4.1 Normal mode ................................................................................................................24310.4.1.1 Software vector mode ....................................................................................24310.4.1.2 Hardware vector mode ...................................................................................24410.4.1.3 Debug mode ...................................................................................................24410.4.1.4 Stop mode .......................................................................................................244

10.5 Memory map and register description ...........................................................................................24410.5.1 Module memory map ...................................................................................................24410.5.2 Register description ......................................................................................................245

10.5.2.1 INTC Module Configuration Register (INTC_MCR) ...................................24510.5.2.2 INTC Current Priority Register for Processor (INTC_CPR) .........................24610.5.2.3 INTC Interrupt Acknowledge Register (INTC_IACKR) ..............................24810.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR) ............................................24910.5.2.5 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3INTC_SSCIR4_7) 24910.5.2.6 INTC Priority Select Registers (INTC_PSR0_3INTC_PSR210) ................251

10.6 Functional description ...................................................................................................................25210.6.1 Interrupt request sources ...............................................................................................261

10.6.1.1 Peripheral interrupt requests ..........................................................................26110.6.1.2 Software configurable interrupt requests .......................................................262



10.6.1.3 Unique vector for each interrupt request source ............................................26210.6.2 Priority management ....................................................................................................262

10.6.2.1 Current priority and preemption ....................................................................26210.6.2.2 Last-In First-Out (LIFO) ................................................................................263

10.6.3 Handshaking with processor .........................................................................................26310.6.3.1 Software vector mode handshaking ...............................................................26310.6.3.2 Hardware vector mode handshaking ..............................................................265

10.7 Initialization/application information ............................................................................................26610.7.1 Initialization flow .........................................................................................................26610.7.2 Interrupt exception handler ...........................................................................................266

10.7.2.1 Software vector mode ....................................................................................26710.7.2.2 Hardware vector mode ...................................................................................267

10.7.3 ISR, RTOS, and task hierarchy .....................................................................................26810.7.4 Order of execution ........................................................................................................26910.7.5 Priority ceiling protocol ................................................................................................270

10.7.5.1 Elevating priority ...........................................................................................27010.7.5.2 Ensuring coherency ........................................................................................270

10.7.6 Selecting priorities according to request rates and deadlines .......................................27010.7.7 Software configurable interrupt requests ......................................................................271

10.7.7.1 Scheduling a lower priority portion of an ISR ...............................................27110.7.7.2 Scheduling an ISR on another processor .......................................................272

10.7.8 Lowering priority within an ISR ..................................................................................27210.7.9 Negating an interrupt request outside of its ISR ..........................................................272

10.7.9.1 Negating an interrupt request as a side effect of an ISR ................................27210.7.9.2 Negating multiple interrupt requests in one ISR ............................................27210.7.9.3 Proper setting of interrupt request priority .....................................................273

10.7.10 Examining LIFO contents ............................................................................................273

Chapter 11e200z0h Core

11.1 Overview .......................................................................................................................................27511.2 Features .........................................................................................................................................275

11.2.1 Microarchitecture summary ..........................................................................................27611.2.1.1 Block diagram ................................................................................................27711.2.1.2 Instruction unit features .................................................................................27711.2.1.3 Integer unit features .......................................................................................27811.2.1.4 Load/Store unit features .................................................................................27811.2.1.5 e200z0h system bus features ..........................................................................27811.2.1.6 Nexus 2+ features ...........................................................................................279

11.3 Core registers and programmers model .......................................................................................279

Chapter 12Peripheral bridge (PBRIDGE)

12.1 Introduction ...................................................................................................................................28312.1.1 Block diagram ..............................................................................................................283



12.1.2 Overview ......................................................................................................................28312.1.3 Features .........................................................................................................................28412.1.4 Modes of operation .......................................................................................................284

12.2 Functional description ...................................................................................................................28412.2.1 Access support ..............................................................................................................284

12.2.1.1 Peripheral write buffering ..............................................................................28412.2.1.2 Read cycles ....................................................................................................28412.2.1.3 Write cycles ....................................................................................................284

12.2.2 General operation .........................................................................................................285

Chapter 13Crossbar Switch (XBAR)

13.1 Introduction ...................................................................................................................................28713.2 Block diagram ...............................................................................................................................28713.3 Overview .......................................................................................................................................28813.4 Features .........................................................................................................................................28813.5 Modes of operation ........................................................................................................................288

13.5.1 Normal mode ................................................................................................................28813.5.2 Debug mode ..................................................................................................................288

13.6 Functional description ...................................................................................................................28813.6.1 Overview ......................................................................................................................28813.6.2 General operation .........................................................................................................28913.6.3 Master ports ..................................................................................................................28913.6.4 Slave ports ....................................................................................................................29013.6.5 Priority assignment .......................................................................................................29013.6.6 Arbitration ....................................................................................................................290

13.6.6.1 Fixed priority operation .................................................................................290

Chapter 14Memory Protection Unit (MPU)

14.1 Introduction ...................................................................................................................................29314.1.1 Overview ......................................................................................................................29314.1.2 Features .........................................................................................................................29414.1.3 Modes of operation .......................................................................................................29514.1.4 External signal description ...........................................................................................295

14.2 Memory map and register description ...........................................................................................29514.2.1 Memory map ................................................................................................................29614.2.2 Register description ......................................................................................................296

14.2.2.1 MPU Control/Error Status Register (MPU_CESR) .......................................29714.2.2.2 MPU Error Address Register, Slave Port n (MPU_EARn) ...........................29814.2.2.3 MPU Error Detail Register, Slave Port n (MPU_EDRn) ...............................29914.2.2.4 MPU Region Descriptor n (MPU_RGDn) .....................................................30014.2.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn) ...305

14.3 Functional description ...................................................................................................................30814.3.1 Access evaluation macro ..............................................................................................308



14.3.1.1 Access evaluation Hit determination ..........................................................30914.3.1.2 Access evaluation Privilege violation determination ..................................309

14.3.2 Putting it all together and AHB error terminations ......................................................31014.4 Initialization information ...............................................................................................................31114.5 Application information ................................................................................................................311

Chapter 15Error Correction Status Module (ECSM)

15.1 Introduction ...................................................................................................................................31315.2 Overview .......................................................................................................................................31315.3 Features .........................................................................................................................................31315.4 Memory map and register description ...........................................................................................313

15.4.1 Memory map ................................................................................................................31315.4.2 Register description ......................................................................................................315

15.4.2.1 Processor Core Type (PCT) register ..............................................................31615.4.2.2 Revision (REV) register .................................................................................31615.4.2.3 IPS Module Configuration (IMC) register .....................................................31715.4.2.4 Miscellaneous Wakeup Control Register (MWCR) .......................................31715.4.2.5 Miscellaneous Interrupt Register (MIR) ........................................................31915.4.2.6 Miscellaneous User-Defined Control Register (MUDCR) ............................32015.4.2.7 ECC registers .................................................................................................32115.4.2.8 Flash ECC Attributes (FEAT) register ...........................................................330

15.4.3 Spp_ips_reg_protection ................................................................................................338

Chapter 16IEEE 1149.1 Test Access Port Controller (JTAGC)

16.1 Introduction ...................................................................................................................................33916.2 Block Diagram ..............................................................................................................................33916.3 Overview .......................................................................................................................................33916.4 Features .........................................................................................................................................34016.5 Modes of Operation .......................................................................................................................340

16.5.1 Reset .............................................................................................................................34016.5.2 IEEE 1149.1-2001 Defined Test Modes .......................................................................340

16.5.2.1 Bypass Mode ..................................................................................................34116.5.2.2 TAP Sharing Mode .........................................................................................341

16.6 External Signal Description ..........................................................................................................34116.7 Memory Map and Register Description ........................................................................................341

16.7.1 Instruction Register ......................................................................................................34216.7.2 Bypass Register ............................................................................................................34216.7.3 Device Identification Register ......................................................................................34216.7.4 Boundary Scan Register ...............................................................................................343

16.8 Functional Description ..................................................................................................................34316.8.1 JTAGC Reset Configuration .........................................................................................34316.8.2 IEEE 1149.1-2001 (JTAG) Test Access Port ................................................................34316.8.3 TAP Controller State Machine .....................................................................................344



16.8.3.1 Selecting an IEEE 1149.1-2001 Register .......................................................34516.8.4 JTAGC Instructions ......................................................................................................345

16.8.4.1 BYPASS Instruction .......................................................................................34516.8.4.2 ACCESS_AUX_TAP_x Instructions .............................................................34616.8.4.3 EXTEST External Test Instruction ...........................................................34616.8.4.4 IDCODE Instruction ......................................................................................34616.8.4.5 SAMPLE Instruction ......................................................................................34616.8.4.6 SAMPLE/PRELOAD Instruction ..................................................................346

16.8.5 Boundary Scan ..............................................................................................................34716.9 e200z0 OnCE Controller ...............................................................................................................347

16.9.1 e200z0 OnCE Controller Block Diagram .....................................................................34716.9.2 e200z0 OnCE Controller Functional Description ........................................................348

16.9.2.1 Enabling the TAP Controller ..........................................................................34816.9.3 e200z0 OnCE Controller Register Description ............................................................348

16.9.3.1 OnCE Command Register (OCMD) ..............................................................34816.10 Initialization/Application Information ..........................................................................................350

Chapter 17Nexus Development Interface (NDI)

17.1 Introduction ...................................................................................................................................35117.2 Block Diagram ..............................................................................................................................35117.3 Features .........................................................................................................................................35217.4 Modes of Operation .......................................................................................................................353

17.4.1 Nexus Reset ..................................................................................................................35317.4.2 Operating Mode ............................................................................................................354

17.4.2.1 Disabled-Port Mode .......................................................................................35417.4.2.2 Censored Mode ..............................................................................................35417.4.2.3 Stop Mode ......................................................................................................354

17.5 External Signal Description ..........................................................................................................35417.5.1 Nexus Signal Reset States ............................................................................................354

17.6 Memory Map and Register Description ........................................................................................35417.6.1 Nexus Debug Interface Registers .................................................................................35517.6.2 Register Description .....................................................................................................356

17.6.2.1 Nexus Device ID (DID) Register ...................................................................35617.6.2.2 Port Configuration Register (PCR) ................................................................35617.6.2.3 Development Control Register 1, 2 (DC1, DC2) ...........................................35917.6.2.4 Development Status (DS) Register ................................................................36117.6.2.5 Read/Write Access Control/Status (RWCS) Register ....................................36217.6.2.6 Read/Write Access Address (RWA) Register ................................................36317.6.2.7 Read/Write Access Data (RWD) Register .....................................................36417.6.2.8 Watchpoint Trigger (WT) Register ................................................................364

17.7 Functional Description ..................................................................................................................36517.7.1 Enabling Nexus Clients for TAP Access ......................................................................36517.7.2 Configuring the NDI for Nexus Messaging .................................................................36617.7.3 Programmable MCKO Frequency ................................................................................366



17.7.4 Nexus Messaging ..........................................................................................................36717.7.5 EVTO Sharing ..............................................................................................................36717.7.6 Debug Mode Control ....................................................................................................367

17.7.6.1 EVTI Generated Break Request .....................................................................36717.7.7 Ownership Trace ...........................................................................................................367

17.7.7.1 Overview ........................................................................................................36717.7.7.2 Ownership Trace Messaging (OTM) .............................................................36717.7.7.3 OTM Error Messages .....................................................................................36817.7.7.4 OTM Flow ......................................................................................................369

Chapter 18Static RAM (SRAM)

18.1 Introduction ...................................................................................................................................37118.2 Low power configuration ..............................................................................................................37118.3 Register memory map ...................................................................................................................37118.4 SRAM ECC mechanism ................................................................................................................371

18.4.1 Access timing ...............................................................................................................37218.4.2 Reset effects on SRAM accesses ..................................................................................373

18.5 Functional description ...................................................................................................................37318.6 Initialization and application information .....................................................................................373

Chapter 19Flash memory

19.1 Introduction ...................................................................................................................................37519.2 Code Flash .....................................................................................................................................375

19.2.1 Introduction ..................................................................................................................37519.2.2 Main features ................................................................................................................37619.2.3 Block diagram ..............................................................................................................37619.2.4 Functional description ..................................................................................................377

19.2.4.1 Module structure ............................................................................................37719.2.4.2 Flash module sectorization .............................................................................37819.2.4.3 User mode operation ......................................................................................38019.2.4.4 Reset ...............................................................................................................38119.2.4.5 Power-down mode .........................................................................................38119.2.4.6 Low power mode ...........................................................................................382

19.2.5 Register description ......................................................................................................38219.2.6 Module Configuration Register (MCR) .......................................................................38419.2.7 Low/Mid address space block Locking register (LML) ...............................................389

19.2.7.1 Non-volatile Low/Mid address space block Locking register (NVLML) .....38919.2.8 High address space Block Locking register (HBL) ......................................................391

19.2.8.1 Non-volatile High address space Block Locking register (NVHBL) ............39119.2.9 Secondary Low/mid address space block Locking register (SLL) ...............................392

19.2.9.1 Non-volatile Secondary Low/mid address space block Locking register (NVSLL) 393

19.2.10 Low/Mid address space block Select register (LMS) ...................................................395



19.2.11 High address space Block Select register (HBS) .........................................................39619.2.12 Address Register (ADR) ...............................................................................................39719.2.13 Bus Interface Unit 0 register (BIU0) ............................................................................39819.2.14 Bus Interface Unit 1 register (BIU1) ............................................................................39919.2.15 Bus Interface Unit 2 register (BIU2) ............................................................................399

19.2.15.1 Non-volatile Bus Interface Unit 2 register (NVBIU2) ...................................40019.2.16 User Test 0 register (UT0) ............................................................................................40019.2.17 User Test 1 register (UT1) ............................................................................................40219.2.18 User Test 2 register (UT2) ............................................................................................40319.2.19 User Multiple Input Signature Register 0 (UMISR0) ..................................................40419.2.20 User Multiple Input Signature Register 1 (UMISR1) ..................................................40419.2.21 User Multiple Input Signature Register 2 (UMISR2) ..................................................40519.2.22 User Multiple Input Signature Register 3 (UMISR3) ..................................................40619.2.23 User Multiple Input Signature Register 4 (UMISR4) ..................................................40619.2.24 Non-volatile private censorship PassWord 0 register (NVPWD0) ..............................40719.2.25 Non-volatile private censorship PassWord 1 register (NVPWD1) ..............................40819.2.26 Non-volatile System Censoring Information 0 register (NVSCI0) ..............................40819.2.27 Non-volatile System Censoring Information 1 register (NVSCI1) ..............................40919.2.28 Non-volatile User Options register (NVUSRO) ...........................................................41019.2.29 Register map .................................................................................................................41119.2.30 Programming considerations ........................................................................................412

19.2.30.1 Modify operation ............................................................................................41219.2.30.2 Error correction code .....................................................................................42019.2.30.3 EEprom emulation .........................................................................................42119.2.30.4 Eprom Emulation ...........................................................................................42119.2.30.5 Protection strategy ..........................................................................................422

19.3 Data Flash ......................................................................................................................................42319.3.1 Introduction ..................................................................................................................42319.3.2 Main features ................................................................................................................42419.3.3 Block diagram ..............................................................................................................42419.3.4 Functional description ..................................................................................................425

19.3.4.1 Module structure ............................................................................................42519.3.4.2 Flash module sectorization .............................................................................426

19.3.5 User mode operation .....................................................................................................42719.3.5.1 Reset ...............................................................................................................42819.3.5.2 Power-down mode .........................................................................................42819.3.5.3 Low power mode ...........................................................................................429

19.3.6 Register description ......................................................................................................42919.3.7 Module Configuration Register (MCR) .......................................................................43119.3.8 Low/Mid address space block Locking register (LML) ...............................................435

19.3.8.1 Non-volatile Low/Mid address space block Locking register (NVLML) .....43619.3.9 High address space Block Locking register (HBL) ......................................................438

19.3.9.1 Non-volatile High address space Block Locking register (NVHBL) ............43819.3.10 Secondary Low/mid address space block Locking register (SLL) ...............................439



19.3.10.1 Non-volatile Secondary Low/mid address space block Locking reg (NVSLL) ..440

19.3.11 Low/Mid address space block Select register (LMS) ...................................................44219.3.12 High address space Block Select register (HBS) .........................................................44319.3.13 Address Register (ADR) ...............................................................................................44419.3.14 User Test 0 register (UT0) ............................................................................................44519.3.15 User Test 1 register (UT1) ............................................................................................44719.3.16 User Test 2 register (UT2) ............................................................................................44819.3.17 User Multiple Input Signature Register 0 (UMISR0) ..................................................44919.3.18 User Multiple Input Signature Register 1 (UMISR1) ..................................................44919.3.19 User Multiple Input Signature Register 2 (UMISR2) ..................................................45019.3.20 User Multiple Input Signature Register 3 (UMISR3) ..................................................45119.3.21 User Multiple Input Signature Register 4 (UMISR4) ..................................................45119.3.22 Register map .................................................................................................................45219.3.23 Programming considerations ........................................................................................453

19.3.23.1 Modify operation ............................................................................................45319.3.23.2 Double word program ....................................................................................45419.3.23.3 Sector erase ....................................................................................................45619.3.23.4 User Test Mode ..............................................................................................458

19.3.24 Error correction code ....................................................................................................46219.3.24.1 ECC algorithms ..............................................................................................46219.3.24.2 EEprom Emulation .........................................................................................462

19.3.25 Protection strategy ........................................................................................................46319.3.25.1 Modify protection ..........................................................................................46319.3.25.2 Censored mode ...............................................................................................464

19.4 Platform Flash controller ...............................................................................................................46419.4.1 Introduction ..................................................................................................................464

19.4.1.1 Overview ........................................................................................................46619.4.1.2 Features ..........................................................................................................466

19.4.2 Modes of operation .......................................................................................................46719.4.3 External signal descriptions ..........................................................................................46719.4.4 Memory map and register description ..........................................................................467

19.4.4.1 Memory map ..................................................................................................46819.4.4.2 Register description ........................................................................................469

19.4.5 Programming model connections .................................................................................47719.5 Functional description ...................................................................................................................479

19.5.1 Basic interface protocol ................................................................................................47919.5.2 Access protections ........................................................................................................48019.5.3 Read cycles Buffer miss ............................................................................................48019.5.4 Read cycles Buffer hit ...............................................................................................48019.5.5 Write cycles ..................................................................................................................48019.5.6 Error termination ..........................................................................................................48119.5.7 Access pipelining ..........................................................................................................48119.5.8 Flash error response operation ......................................................................................48119.5.9 Bank0 page read buffers and prefetch operation ..........................................................482



19.5.9.1 Instruction/Data prefetch triggering ...............................................................48319.5.9.2 Per-master prefetch triggering ........................................................................48319.5.9.3 Buffer allocation .............................................................................................48319.5.9.4 Buffer invalidation .........................................................................................484

19.5.10 Bank1 Temporary Holding Register .............................................................................48419.5.11 Read-while-write functionality .....................................................................................48519.5.12 Wait-state emulation .....................................................................................................48619.5.13 Timing diagrams ...........................................................................................................487

Chapter 20Deserial Serial Peripheral Interface (DSPI)

20.1 Introduction ...................................................................................................................................49520.2 Block diagram ...............................................................................................................................49520.3 Overview .......................................................................................................................................49620.4 Features .........................................................................................................................................49620.5 Modes of operation ........................................................................................................................497

20.5.1 Master mode .................................................................................................................49720.5.2 Slave mode ...................................................................................................................49720.5.3 Module Disable mode ...................................................................................................49820.5.4 Debug mode ..................................................................................................................498

20.6 External signal description ............................................................................................................49820.6.1 Signal overview ............................................................................................................49820.6.2 Signal names and descriptions ......................................................................................498

20.6.2.1 Peripheral Chip Select / Slave Select (CS0_x) ..............................................49820.6.2.2 Peripheral Chip Selects 13 (CS1:3_x) .........................................................49920.6.2.3 Peripheral Chip Select 4 (CS4_x) ..................................................................49920.6.2.4 Peripheral Chip Select 5 / Peripheral Chip Select Strobe(CS5_x) 49920.6.2.5 Serial Input (SIN_x) .......................................................................................49920.6.2.6 Serial Output (SOUT_x) ................................................................................49920.6.2.7 Serial Clock (SCK_x) .....................................................................................499

20.7 Memory map and register description ...........................................................................................50020.7.1 Memory map ................................................................................................................50020.7.2 Register description ......................................................................................................501

20.7.2.1 DSPI Module Configuration Register (DSPIx_MCR) ...................................50120.7.2.2 DSPI Transfer Count Register (DSPIx_TCR) ...............................................50420.7.2.3 DSPI Clock and Transfer Attributes Registers 05 (DSPIx_CTARn) ...........50520.7.2.4 DSPI Status Register (DSPIx_SR) .................................................................51320.7.2.5 DSPI Interrupt Request Enable Register (DSPIx_RSER) .............................51520.7.2.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) ........................................51720.7.2.7 DSPI POP RX FIFO Register (DSPIx_POPR) ..............................................51920.7.2.8 DSPI Transmit FIFO Registers 03 (DSPIx_TXFRn) ...................................52020.7.2.9 DSPI Receive FIFO Registers 03 (DSPIx_RXFRn) ....................................520

20.8 Functional description ...................................................................................................................52120.8.1 Modes of operation .......................................................................................................522



20.8.1.1 Master mode ...................................................................................................52220.8.1.2 Slave mode .....................................................................................................52320.8.1.3 Module Disable mode ....................................................................................52320.8.1.4 Debug mode ...................................................................................................523

20.8.2 Start and stop of DSPI transfers ...................................................................................52320.8.3 Serial peripheral interface (SPI) configuration .............................................................524

20.8.3.1 SPI Master mode ............................................................................................52520.8.3.2 SPI Slave mode ..............................................................................................52520.8.3.3 FIFO disable operation ...................................................................................52520.8.3.4 Transmit First In First Out (TX FIFO) buffering mechanism ........................52620.8.3.5 Receive First In First Out (RX FIFO) buffering mechanism .........................526

20.8.4 DSPI baud rate and clock delay generation ..................................................................52720.8.4.1 Baud rate generator ........................................................................................52820.8.4.2 CS to SCK delay (tCSC) ................................................................................52820.8.4.3 After SCK delay (tASC) ................................................................................52920.8.4.4 Delay after transfer (tDT) ..............................................................................52920.8.4.5 Peripheral chip select strobe enable (CS5_x) ................................................529

20.8.5 Transfer formats ...........................................................................................................53020.8.5.1 Classic SPI transfer format (CPHA = 0) ........................................................53220.8.5.2 Classic SPI transfer format (CPHA = 1) ........................................................53320.8.5.3 Modified SPI transfer format (MTFE = 1, CPHA = 0) ..................................53420.8.5.4 Modified SPI transfer format (MTFE = 1, CPHA = 1) ..................................53520.8.5.5 Continuous selection format ..........................................................................53620.8.5.6 Clock polarity switching between DSPI transfers .........................................538

20.8.6 Continuous serial communications clock .....................................................................53820.8.7 Interrupt requests ..........................................................................................................540

20.8.7.1 End of Queue Interrupt Request (EOQF) ......................................................54020.8.7.2 Transmit FIFO Fill Interrupt Request (TFFF) ...............................................54020.8.7.3 Transfer Complete Interrupt Request (TCF) ..................................................54020.8.7.4 Transmit FIFO Underflow Interrupt Request (TFUF) ...................................54120.8.7.5 Receive FIFO Drain Interrupt Request (RFDF) ............................................54120.8.7.6 Receive FIFO Overflow Interrupt Request (RFOF) ......................................54120.8.7.7 FIFO Overrun Request (TFUF) or (RFOF) ...................................................541

20.8.8 Power saving features ...................................................................................................54120.8.8.1 Module Disable mode ....................................................................................54120.8.8.2 Slave interface signal gating ..........................................................................542

20.9 Initialization and application information .....................................................................................54220.9.1 How to change queues ..................................................................................................54220.9.2 Baud rate settings .........................................................................................................54220.9.3 Delay settings ...............................................................................................................54420.9.4 Calculation of FIFO pointer addresses .........................................................................544

20.9.4.1 Address calculation for the first-in entry and last-in entry in the TX FIFO 54520.9.4.2 Address calculation for the first-in entry and last-in entry in the RX FIFO 545



Chapter 21LIN Controller (LINFlex)

21.1 Introduction ...................................................................................................................................54721.2 Main features .................................................................................................................................547

21.2.1 LIN mode features ........................................................................................................54721.2.2 UART mode features ....................................................................................................54721.2.3 Features common to LIN and UART ...........................................................................547

21.3 General description .......................................................................................................................54821.4 Fractional baud rate generation .....................................................................................................54921.5 Operating modes ...........................................................................................................................551

21.5.1 Initialization mode ........................................................................................................55221.5.2 Normal mode ................................................................................................................55221.5.3 Low power mode (Sleep) .............................................................................................552

21.6 Test modes .....................................................................................................................................55221.6.1 Loop Back mode ...........................................................................................................55221.6.2 Self Test mode ..............................................................................................................553

21.7 Memory map and registers description .........................................................................................55321.7.1 Memory map ................................................................................................................55321.7.2 Register description ......................................................................................................555

21.7.2.1 LIN control register 1 (LINCR1) ...................................................................55521.7.2.2 LIN interrupt enable register (LINIER) .........................................................55821.7.2.3 LIN status register (LINSR) ...........................................................................56021.7.2.4 LIN error status register (LINESR) ...............................................................56321.7.2.5 UART mode control register (UARTCR) ......................................................56421.7.2.6 UART mode status register (UARTSR) .........................................................56621.7.2.7 LIN timeout control status register (LINTCSR) ............................................56821.7.2.8 LIN output compare register (LINOCR) .......................................................56921.7.2.9 LIN timeout control register (LINTOCR) ......................................................56921.7.2.10 LIN fractional baud rate register (LINFBRR) ...............................................57021.7.2.11 LIN integer baud rate register (LINIBRR) ....................................................57121.7.2.12 LIN checksum field register (LINCFR) .........................................................57221.7.2.13 LIN control register 2 (LINCR2) ...................................................................57221.7.2.14 Buffer identifier register (BIDR) ...................................................................57421.7.2.15 Buffer data register LSB (BDRL) ..................................................................57521.7.2.16 Buffer data register MSB (BDRM) ................................................................57521.7.2.17 Identifier filter enable register (IFER) ...........................................................57621.7.2.18 Identifier filter match index (IFMI) ...............................................................57721.7.2.19 Identifier filter mode register (IFMR) ............................................................57821.7.2.20 Identifier filter control register (IFCR2n) ......................................................57921.7.2.21 Identifier filter control register (IFCR2n + 1) ................................................580

21.7.3 Register map and reset values ......................................................................................58221.8 Functional description ...................................................................................................................586

21.8.1 UART mode ..................................................................................................................58621.8.1.1 Buffer in UART mode ....................................................................................58621.8.1.2 UART transmitter ...........................................................................................587



21.8.1.3 UART receiver ...............................................................................................58721.8.1.4 Clock gating ...................................................................................................588

21.8.2 LIN mode ......................................................................................................................58821.8.2.1 Master mode ...................................................................................................58821.8.2.2 Slave mode .....................................................................................................59021.8.2.3 Slave mode with identifier filtering ...............................................................59221.8.2.4 Slave mode with automatic resynchronization ..............................................59421.8.2.5 Clock gating ........

mpc5604b/c microcontroller reference...

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