mpc5746c microcontroller datasheet - farnell element145. see device datasheet and reference manual...
TRANSCRIPT
MPC5746CMPC5746C MicrocontrollerDatasheetFeatures
• 1 x 160 MHz Power Architecture® e200Z4 Dual issue,32-bit CPU– Single precision floating point operations– 8 KB instruction cache and 4 KB data cache– Variable length encoding (VLE) for significant code
density improvements
• 1 x 80 MHz Power Architecture® e200Z2 Single issue,32-bit CPU– Using variable length encoding (VLE) for
significant code size footprint reduction
• End to end ECC– All bus masters, for example, cores generate single
error correction, double error detection (SECDED)code for every bus transaction
– SECDED covers 64-bit data and 29-bit address
• Memory interfaces– 3 MB on-chip flash memory supported with the
flash memory controller– 3 x flash memory page buffers (3 port flash memory
controller)– 384 KB on-chip SRAM across three RAM ports
• Clock interfaces– 8-40 MHz external crystal (FXOSC)– 16 MHz IRC (FIRC)– 128 KHz IRC (SIRC)– 32 KHz external crystal (SXOSC)– Clock Monitor Unit (CMU)– Frequency modulated phase-locked loop (FMPLL)– Real Time Counter (RTC)
• System Memory Protection Unit (SMPU) with up to 32region descriptors and 16-byte region granularity
• 16 Semaphores to manage access to shared resource
• Interrupt controller (INTC) capable of routinginterrupts to any CPU
• Crossbar switch architecture for concurrent access toperipherals, flash memory, and RAM from multiplebus masters
• 32-channels eDMA controller with multiple transferrequest sources using DMAMUX
• Boot Assist Flash (BAF) supports internal flashprogramming via a serial link (SCI)
• Analog– Two analog-to-digital converters (ADC), one 10-bit
and one 12-bit– Three analogue comparators– Cross Trigger Unit to enable synchronization of
ADC conversions with a timer event from theeMIOS or from the PIT
• Communication– Four Deserial Peripheral Interface (DSPI)– Four Serial Peripheral interface (SPI)– 16 serial communication interface (LIN) modules– Eight enhanced FlexCAN3 with FD support– Four inter-IC communication interface (I2C)– ENET complex (10/100 Ethernet) that supports
Multi queue with AVB support, 1588, and MII/RMII
– Dual-channel FlexRay Controller
• Audio– Synchronous Audio Interface (SAI)– Fractional clock dividers (FCD) operating in
conjunction with the SAI
• Configurable I/O domains supporting FlexCAN,LINFlexD, Ethernet, and general I/O
• Supports wake-up from low power modes via theWKPU controller
• On-chip voltage regulator (VREG)
• Debug functionality– e200Z2 core:NDI per IEEE-ISTO 5001-2008
Class3+– e200Z4 core: NDI per IEEE-ISTO 5001-2008 Class
3+
Freescale Semiconductor Document Number MPC5746C
Data Sheet: Technical Data Rev. 4, 3/2016
© 2016 Freescale Semiconductor, Inc.
NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
• Timer– 16 Periodic Interrupt Timers (PITs)– Two System Timer Module (STM)– Three Software Watchdog Timers (SWT)– 64 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels
• Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) and1149.7 (CJTAG)
• Security– Hardware Security Module (HSMv2)– Password and Device Security (PASS) supporting advanced censorship and life-cycle management– One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts
• Functional Safety– ISO26262 ASIL-B compliance
• Multiple operating modes– Includes enhanced low power operation
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
2 Freescale Semiconductor, Inc.
Table of Contents1 Block diagram.................................................................................... 4
2 Family comparison.............................................................................4
3 Ordering parts.....................................................................................7
3.1 Determining valid orderable parts ............................................ 7
3.2 Ordering Information ................................................................7
4 General............................................................................................... 8
4.1 Introduction................................................................................8
4.2 Absolute maximum ratings........................................................8
4.3 Recommended operating conditions..........................................9
4.4 Voltage regulator electrical characteristics................................11
4.5 Voltage monitor electrical characteristics................................. 15
4.6 Supply current characteristics....................................................17
4.7 Electrostatic discharge (ESD) characteristics............................20
4.8 Electromagnetic Compatibility (EMC) specifications...............21
5 I/O parameters....................................................................................21
5.1 AC specifications @ 3.3 V Range............................................. 21
5.2 DC electrical specifications @ 3.3V Range.............................. 22
5.3 AC specifications @ 5 V Range................................................ 23
5.4 DC electrical specifications @ 5 V Range................................ 24
5.5 Reset pad electrical characteristics............................................ 25
5.6 PORST electrical specifications................................................ 26
6 Peripheral operating requirements and behaviours............................ 27
6.1 Analog........................................................................................27
6.1.1 ADC electrical specifications...................................... 27
6.1.2 Analog Comparator (CMP) electrical specifications...30
6.2 Clocks and PLL interfaces modules.......................................... 31
6.2.1 Main oscillator electrical characteristics......................31
6.2.2 32 kHz Oscillator electrical specifications ................. 33
6.2.3 16 MHz RC Oscillator electrical specifications...........34
6.2.4 128 KHz Internal RC oscillator Electrical
specifications ...............................................................34
6.2.5 PLL electrical specifications .......................................34
6.3 Memory interfaces..................................................................... 36
6.3.1 Flash memory program and erase specifications......... 36
6.3.2 Flash memory Array Integrity and Margin Read
specifications................................................................37
6.3.3 Flash memory module life specifications.................... 37
6.3.4 Data retention vs program/erase cycles....................... 38
6.3.5 Flash memory AC timing specifications......................38
6.3.6 Flash read wait state and address pipeline control
settings ........................................................................ 39
6.4 Communication interfaces......................................................... 40
6.4.1 DSPI timing................................................................. 40
6.4.2 FlexRay electrical specifications................................. 46
6.4.2.1 FlexRay timing.........................................46
6.4.2.2 TxEN........................................................ 46
6.4.2.3 TxD.......................................................... 47
6.4.2.4 RxD.......................................................... 48
6.4.3 Ethernet switching specifications................................ 49
6.4.4 SAI electrical specifications ....................................... 50
6.5 Debug specifications..................................................................52
6.5.1 JTAG interface timing ................................................ 52
6.5.2 Nexus timing................................................................55
6.5.3 WKPU/NMI timing..................................................... 57
6.5.4 External interrupt timing (IRQ pin)............................. 58
7 Thermal attributes.............................................................................. 58
7.1 Thermal attributes......................................................................58
8 Dimensions.........................................................................................62
8.1 Obtaining package dimensions ................................................. 62
9 Pinouts................................................................................................63
9.1 Package pinouts and signal descriptions....................................63
10 Revision History.................................................................................63
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 3
1 Block diagram
4 KB d-cache8 KB i-cache
Nexus 3+SPFP-APU
64-bit AHBE2 E-ECC
160 MHz e200z4
Peripheral bridge
E2 E-ECC
Flash Memory Low powerunit interface
(LPU)
E2 E-ECC64-bit data SMPU
64-bit AHB
E2 E-ECC
Nexus 3+
80 MHz e200z2
Flexray
HSMv2Ethernet(ENET)
eDMA
System bus masters
System
128 KHzSIRC
MEMU
WKPU
BAF
FMPLL
RTC/API
2 x SWTs
16 x SEMA42
16 x PIT-RTI
32 KHzSXOSC
8–40 MHzFXOSC
Padkeepersupport
Registerprotection
MC_CGM,MC_PCU,MC_ME,
MC_RGM
STCU(MBIST)
SIUL
2 x STM
PMC
16 MHz FIRC
DEBUG/JTAG
FCCU
PASS
SSCM
CMU
TDMPeripheral clusters
68 ch 10-bit ADC0(mix int and ext)
31 ch 12-bit ADC1 1 x FlexCAN(PN)*7 x FlexCAN*
16 x LINFlexD
4 x I2C 3 x analogcomparator (CMP)
4 x DSPI4 x SPI
3 x SAI3 x FCD
2 x eMIOS + BCTU 2-core INTC DMA and 2 x channel mux
1 x CRC
3 x SA-PF buffers
3 MB array (inc EEE)
E2 E-ECC
Triple ported
64-bit wide RAM
2xRAM
E2 E-ECC
256 KB array
* All FlexCANs optionally support CAN FD
256 KB array
Figure 1. MPC5746C block diagram
2 Family comparisonThe following table provides a summary of the different members of the MPC5746Cfamily and their proposed features. This information is intended to provide anunderstanding of the range of functionality offered by this family. For full details of all ofthe family derivatives please contact your marketing representative.
Block diagram
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
4 Freescale Semiconductor, Inc.
NOTEAll optional features (Flash memory, RAM, Peripherals) startwith lowest number or address (e.g. FlexCAN0) and end athighest available number or address (e.g. MPC574xB/D have 6CAN, ending with FlexCAN5).
Table 1. MPC5746C Family Comparison1
Feature MPC5745B MPC5745D MPC5746B MPC5746D MPC5745C MPC5746C
CPUs e200z4 e200z4 e200z4 e200z4 e200z4
e200z2
e200z4
e200z2
FPU e200z4 e200z4 e200z4 e200z4 e200z4 e200z4
MaximumOperating
Frequency2
160MHz (Z4) 160MHz (Z4) 160MHz (Z4) 160MHz (Z4) 160MHz (Z4)
80MHz (Z2)
160MHz (Z4)
80MHz (Z2)
Flash memory 2 MB 2 MB 3 MB 3 MB 2 MB 3 MB
EEPROMsupport
Emulated up to 64K Emulated up to 128K
RAM 256 KB 256 KB 384 KB(Optional512KB)3
384 KB(Optional512KB)3
256 KB 384 KB(Optional512KB)3
ECC End to End
SMPU 16 entry
DMA 32 channels
10-bit ADC 36 Standard channels
32 External channels
12-bit ADC 15 Precision channels
16 Standard channels
AnalogComparator
3
BCTU 1
SWT 1, SWT[0] 24
STM 1, STM[0] 2
PIT-RTI 16 channels PIT
1 channels RTI
RTC/API 1
Total Timer I/O5 64 channels
16-bits
LINFlexD 1
Master and Slave (LINFlexD[0], 11 Master (LINFlexD[1:11])
1
Master and Slave (LINFlexD[0], 15Master (LINFlexD[1:15])
FlexCAN 6 with optional CAN FD support (FlexCAN[0:5]) 8 with optional CAN FD support(FlexCAN[0:7])
DSPI/SPI 4 x DSPI
4 x SPI
Table continues on the next page...
Family comparison
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 5
Table 1. MPC5746C Family Comparison1 (continued)
Feature MPC5745B MPC5745D MPC5746B MPC5746D MPC5745C MPC5746C
I2C 1, I2C[0] 4 1, I2C[0] 4
SAI/I2S 0 3 0 3
FXOSC 8 - 40 MHz
SXOSC 32 KHz
FIRC 16 MHz
SIRC 128 KHz
FMPLL 1
Low Power Unit(LPU)
Yes
FlexRay 2.1(dual channel)
Yes, 128 MB 0 Yes, 128 MB 0 Yes, 128 MB
Ethernet (RMII,MII + 1588, Muti
queue AVBsupport)
0 1 0 1
CRC 1
MEMU 1
STCU2 1
HSM-v2(security)
Optional
Censorship Yes
FCCU 1
Safety level Specific functions ASIL-B certifiable
User MBIST Yes
I/O Retention inStandby
Yes
GPIO6 Up to 264 GPI and up to 246 GPIO
Debug JTAGC,
CJTAG
Nexus Z4 N3+ (Only available on 324BGA (development only) )
Z2 N3+ (Only available on 324BGA (development only) )
Packages 176 LQFP-EP
256 BGA
100 BGA
176 LQFP-EP
256 BGA
100 BGA
176 LQFP-EP
256 BGA
100 BGA
176 LQFP-EP
256 BGA
100 BGA
176 LQFP-EP
256 BGA
100 BGA
176 LQFP-EP
256 BGA,
324 BGA(development
only)
100 BGA
1. Feature set dependent on selected peripheral multiplexing, table shows example. Peripheral availability is packagedependent.
2. Based on 125°C ambient operating temperature and subject to full device characterization.3. Contact freescale representative for part number4. Additional SWT included when HSM option selected5. See device datasheet and reference manual for information on to timer channel configuration and functions.6. Estimated I/O count for largest proposed packages based on multiplexing with peripherals.
Family comparison
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
6 Freescale Semiconductor, Inc.
Ordering parts
3.1 Determining valid orderable parts
To determine the orderable part numbers for this device, go to www.freescale.com andperform a part number search for the following device number: MPC5746C.
3.2 Ordering Information
Qualification Status
Power Architecture
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
Temperature spec.
Package Code
Qualification StatusP = Engineering samplesS = Automotive qualified
PC = Power Architecture
Automotive Platform57 = Power Architecture in 55nm
Core Version4 = e200z4 Core Version (highest core version in the case of multiple cores)
Flash Memory Size
5 = 2 MB6 = 3 MB
Product Version
Optional fields
Fab and mask version indicatorK = TSMC Fab#(0,1,etc.) = Version of the maskset, like rev. 0=0N65H
Temperature spec.C = -40.C to +85.C TaV = -40.C to +105.C TaM = -40.C to +125.C Ta
R = Tape & Reel (blank if Tray)
Package CodeKU = 176 LQFP EPMJ = 256 MAPBGAMN = 324 MAPBGAM
CPU Frequency
Shipping MethodR = Tape and reelBlank = Tray
CPU Frequency
Fab and mask indicator
Example Code
2 = Z4 operates upto 120 MHz6 = Z4 operates upto 160 MHz
B = Single core FlexRay feature setD = Single core Ethernet feature setC = Dual core (FlexRay + Ethernet) feature set
P PC 57 4 6 C S K0 M MJ 6 R
F = CAN FDB = HSM + CAN FDR = 512K RAMT = HSM + 512K RAMG = CAN FD + 512K RAMH = HSM + CAN FD + 512K RAM
MH = 100MAPBGA
Note: Not all part number combinations are available as production product
Blank = No optional featureS = HSM (Security Module)
3
Ordering parts
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 7
General
4.1 Introduction
The electrical specifications are preliminary and are initial evaluation. Thesespecifications are not fully tested or guaranteed at this early stage of the product lifecycle. Finalized specifications will be published after complete characterization anddevice qualifications have been completed.
4.2 Absolute maximum ratings
NOTEFunctional operating conditions appear in the DC electricalcharacteristics. Absolute maximum ratings are stress ratingsonly, and functional operation at the maximum values is notguaranteed. See footnotes in Table 2 for specific conditions
Stress beyond the listed maximum values may affect devicereliability or cause permanent damage to the device.
Table 2. Absolute maximum ratings
Symbol Parameter Conditions1 Min Max Unit
VDD_HV_A, VDD_HV_B,VDD_HV_C
2, 33.3 V - 5. 5V input/output supply voltage — –0.3 6.0 V
VDD_HV_FLA4, 5 3.3 V flash supply voltage (when supplying
from an external source in bypass mode)— –0.3 3.63 V
VDD_LP_DEC6 Decoupling pin for low power regulators7 — –0.3 1.32 V
VDD_HV_ADC1_REF8 3.3 V / 5.0 V ADC1 high reference voltage — –0.3 6 V
VDD_HV_ADC0
VDD_HV_ADC1
3.3 V to 5.5V ADC supply voltage — –0.3 6.0 V
VSS_HV_ADC0
VSS_HV_ADC1
3.3V to 5.5V ADC supply ground — –0.1 0.1 V
VDD_LV9, 10, 11, 12 Core logic supply voltage — –0.3 1.32 V
VINA Voltage on analog pin with respect toground (VSS_HV)
— –0.3 Min (VDD_HV_x,VDD_HV_ADCx,VDD_ADCx_REF)
+0.3
V
VIN Voltage on any digital pin with respect toground (VSS_HV)
Relative toVDD_HV_A,VDD_HV_B,VDD_HV_C
–0.3 VDD_HV_x + 0.3 V
Table continues on the next page...
4
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
8 Freescale Semiconductor, Inc.
Table 2. Absolute maximum ratings (continued)
Symbol Parameter Conditions1 Min Max Unit
IINJPAD Injected input current on any pin duringoverload condition
Always –5 5 mA
IINJSUM Absolute sum of all injected input currentsduring overload condition
— –50 50 mA
Tramp Supply ramp rate — 0.5 V / min 100V/ms —
TA13 Ambient temperature — -40 125 °C
TSTG Storage temperature — –55 165 °C
1. All voltages are referred to VSS_HV unless otherwise specified2. VDD_HV_B and VDD_HV_C are common together on the 176 LQFP-EP package.3. Allowed VDD_HV_x = 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in
reset, TJ= 150 °C, remaining time at or below 5.5 V.4. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V5. VDD_HV_FLA must be disconnected from ANY power sources when VDD_HV_A = 5V6. This pin should be decoupled with low ESR 1 µF capacitor.7. Not available for input voltage, only for decoupling internal regulators8. 10-bit ADC does not have dedicated reference and its reference is bonded to 10-bit ADC supply(VDD_HV_ADC0) inside
the package.9. Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum TJ = 150 °C, remaining time as defined in footnotes 10
and 11.10. Allowed 1.38 – 1.45 V– for 10 hours cumulative time at maximum TJ = 150 °C, remaining time as defined in footnote 11.11. 1.32 – 1.38 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.326 V at
maximum TJ = 150 °C.12. If HVD on core supply (VHVD_LV_x) is enabled, it will generate a reset when supply goes above threshold.13. TJ=150°C. Assumes TA=125°C
• Assumes maximum θJA for 2s2p board. See Thermal attributes
4.3 Recommended operating conditionsThe following table describes the operating conditions for the device, and for which allspecifications in the data sheet are valid, except where explicitly noted. The deviceoperating conditions must not be exceeded in order to guarantee proper operation andreliability. The ranges in this table are design targets and actual data may vary in thegiven range.
NOTE• For normal device operations, all supplies must be within
operating range corresponding to the range mentioned infollowing tables. This is required even if some of thefeatures are not used.
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 9
• If VDD_HV_A is in 3.3V range, VDD_HV_FLA should beexternally supplied using a 3.3V source. If VDD_HV_A isin 3.3V range, VDD_HV_FLA should be shorted toVDD_HV_A.
• VDD_HV_A, VDD_HV_B and VDD_HV_C are allindependent supplies and can each be set to 3.3V or 5V.The following tables: 'Recommended operating conditions(VDD_HV_x = 3.3 V)' and table 'Recommended operatingconditions (VDD_HV_x = 5 V)' specify their ranges whenconfigured in 3.3V or 5V respectively.
NOTEDesign may experience up to 30mA additional crossovercurrent (on the high voltage flash supply) if the high voltageflash supply is powered before the low voltage core supply.This additional current will be removed once the low voltagecore supply rises to its operating range. There is no reliabilityconcern to the device due to this additional current.
Table 3. Recommended operating conditions (VDD_HV_x = 3.3 V)
Symbol Parameter Conditions1 Min2 Max Unit
VDD_HV_A
VDD_HV_B
VDD_HV_C
HV IO supply voltage — 3.15 3.6 V
VDD_HV_FLA3 HV flash supply voltage — 3.15 3.6 V
VDD_HV_ADC1_REF HV ADC1 high reference voltage — 3.0 5.5 V
VDD_HV_ADC0
VDD_HV_ADC1
HV ADC supply voltage — max(VDD_HV_A,VDD_HV_B,VDD_HV_C) - 0.05
3.6 V
VSS_HV_ADC0
VSS_HV_ADC1
HV ADC supply ground — -0.1 0.1 V
VDD_LV4 Core supply voltage — 1.2 1.32 V
VIN1_CMP_REF5, 6 Analog Comparator DAC reference voltage — 3.15 3.6 V
IINJPAD Injected input current on any pin duringoverload condition
— -3.0 3.0 mA
TA, 7 Ambient temperature under bias fCPU ≤ 160
MHz–40 125 °C
TJ Junction temperature under bias — –40 150 °C
1. All voltages are referred to VSS_HV unless otherwise specified2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the
point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.3. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
10 Freescale Semiconductor, Inc.
4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only beleft floating.
5. VIN1_CMP_REF ≤ VDD_HV_A6. This supply is shorted VDD_HV_A on lower packages.7. TJ=150°C. Assumes TA=125°C
• Assumes maximum θJA of 2s2p board. See Thermal attributes
NOTEIf VDD_HV_A is in 5V range, it is necessary to use internalFlash supply 3.3V regulator. VDD_HV_FLA should not besupplied externally and should only have decoupling capacitor.
Table 4. Recommended operating conditions (VDD_HV_x = 5 V)
Symbol Parameter Conditions 1 Min2 Max Unit
VDD_HV_A
VDD_HV_B
VDD_HV_C
HV IO supply voltage — 4.5 5.5 V
VDD_HV_FLA3 HV flash supply voltage — 3.15 3.6 V
VDD_HV_ADC1_REF HV ADC1 high reference voltage — 3.15 5.5 V
VDD_HV_ADC0
VDD_HV_ADC1
HV ADC supply voltage — max(VDD_HV_A,VDD_HV_B,VDD_HV_C) - 0.05
5.5 V
VSS_HV_ADC0
VSS_HV_ADC1
HV ADC supply ground — -0.1 0.1 V
VDD_LV4 Core supply voltage — 1.2 1.32 V
VIN1_CMP_REF6 Analog Comparator DAC reference voltage — 3.15 5.55 V
IINJPAD Injected input current on any pin duringoverload condition
— -3.0 3.0 mA
TA-1 Ambient temperature under bias fCPU ≤ 160
MHz–40 125 °C
TJ Junction temperature under bias — –40 150 °C
1. All voltages are referred to VSS_HV unless otherwise specified2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the
point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.3. When VDD_HV is in 5 V range, VDD_HV_FLA cannot be supplied externally.This pin is decoupled with Cflash_reg.4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be
left floating5. VIN1_CMP_REF ≤ VDD_HV_A6. This supply is shorted VDD_HV_A on lower packages.
4.4 Voltage regulator electrical characteristicsThe voltage regulator is composed of the following blocks:
• Choice of generating supply voltage for the core area.• Control of external NPN ballast transistor
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 11
• Generating core supply using internal ballast transistor• Connecting an external 1.25V (nominal) directly without the NPN ballast
• Internal generation of the 3.3V flash supply when device connected in 5Vapplications
• External bypass of the 3.3V flash regulator when device connected in 3.3Vapplications
• Low voltage detector - low threshold (LVD_IO_A_LO) for VDD_HV_IO_A supply• Low voltage detector - high threshold (LVD_IO_A_Hi) for VDD_HV_IO_A supply• Low voltage detector (LVD_FLASH) for 3.3 V flash supply (VDD_HV_FLA)• Various low voltage detectors (LVD_LV_x)• High voltage detector (HVD_LV_cold) for 1.2 V digital core supply (VDD_LV)• Power on Reset (POR_LV) for 1.25 V digital core supply (VDD_LV)• Power on Reset (POR_HV) for 3.3V to 5V supply (VDD_HV_A)
The following bipolar transistors1 are supported, depending on the device performancerequirements. As a minimum the following must be considered when determining themost appropriate solution to maintain the device under its maximum power dissipationcapability: current, ambient temperature, mounting pad area, duty cycle and frequency forIdd, collector voltage, etc
1. BCP56, MCP68 and MJD31are guaranteed ballasts.
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
12 Freescale Semiconductor, Inc.
VDD_LP_DEC
CLP/ULPREG
CFLASH_REG
VRC_CTRL
VSS_HV
CFP_REG
VDD_HV_BALLAST
DEVICE
FPREG
VDD_HV_FLA
LPPREG
ULPPREG
Flash voltage regulator
CBE_FPREG
DD_LVV
SS_HVV
VSS_HV
Figure 2. Voltage regulator capacitance connection
NOTEOn BGA, VSS_LV and VSS_HV have been joined on substrateand renamed as VSS.
Table 5. Voltage regulator electrical specifications
Symbol Parameter Conditions Min Typ Max Unit
Cfp_reg1 External decoupling / stability
capacitorMin, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.
1.32 2.22 3 µF
Combined ESR of externalcapacitor
— 0.001 — 0.03 Ohm
Clp/ulp_reg External decoupling / stabilitycapacitor for internal low powerregulators
Min, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.
0.8 1 1.4 µF
Combined ESR of externalcapacitor
— 0.001 — 0.1 Ohm
Cbe_fpreg3 Capacitor in parallel to base-
emitterBCP68 and BCP56 3.3 nF
MJD31 4.7
Table continues on the next page...
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 13
Table 5. Voltage regulator electrical specifications (continued)
Symbol Parameter Conditions Min Typ Max Unit
Cflash_reg4 External decoupling / stability
capacitor for internal Flashregulators
Min, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.
1.32 2.2 3 µF
Combined ESR of externalcapacitor
— 0.001 — 0.03 Ohm
CHV_VDD_A
VDD_HV_A supply capacitor 5 Min, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.
1 — — µF
CHV_VDD_B
VDD_HV_B supply capacitor5 Min, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.
1 — — µF
CHV_ADC0
CHV_ADC1
HV ADC supply decouplingcapacitances
Min, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.
1 — — µF
CHV_ADR6 HV ADC SAR reference supply
decoupling capacitancesMin, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.
0.47 — — µF
VDD_HV_BALL
AST7
FPREG Ballast collector supplyvoltage
When collector of NPN ballast isdirectly supplied by an on boardsupply source (not shared withVDD_HV_A supply pin) withoutany series resistance, that is,RC_BALLAST less than 0.01 Ohm.
2.25 — 5.5 V
RC_BALLAST Series resistor on collector ofFPREG ballast
When VDD_HV_BALLAST isshorted to VDD_HV_A on theboard
— — 0.1 Ohm
tSU Start-up time with externalballastafter main supply(VDD_HV_A) stabilization
Cfp_reg = 3 μF — 74 — μs
tSU_int Start-up time with internal ballastafter main supply (VDD_HV_A)stabilization
Cfp_reg = 3 μF — 103 — μs
tramp Load current transient Iload from 15% to 55%
Cfp_reg
= 3 µF
1.0 µs
1. Split capacitance on each pair VDD_LV pin should sum up to a total value of Cfp_reg2. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum and
maximum values.3. Ceramic X7R or X5R type with capacitance-temperature characteristics +/-15% of -55 degC to +125degC is
recommended. The tolerance +/-20% is acceptable.4. It is required to minimize the board parasitic inductance from decoupling capacitor to VDD_HV_FLA pin and the routing
inductance should be less than 1nH.5. 1. For VDD_HV_x, 1µf on each side of the chip
a. 0.1 µf close to each VDD/VSS pin pair.b. 10 µf near for each power supply source
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
14 Freescale Semiconductor, Inc.
c. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulationmode, this amount of capacitance will need to be subtracted from the total capacitance required by theregulator for e.g., as specified by CFP_REG parameter.
2. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation mode, thisamount of capacitance will need to be subtracted from the total capacitance required by the regulator for e.g., asspecified by CFP_REG parameter
6. Only applicable to ADC17. In external ballast configuration the following must be ensured during power-up and power-down (Note: If VDD_HV_BALLAST
is supplied from the same source as VDD_HV_A this condition is implicitly met):• During power-up, VDD_HV_BALLAST must have met the min spec of 2.25V before VDD_HV_A reaches the
POR_HV_RISE min of 2.75V.• During power-down, VDD_HV_BALLAST must not drop below the min spec of 2.25V until VDD_HV_A is below
POR_HV_FALL min of 2.7V.
NOTE
For a typical configuration using an external ballast transistorwith separate supply for VDD_HV_A and the ballast collector,a bulk storage capacitor (as defined in Table 5) is required onVDD_HV_A close to the device pins to ensure a stable supplyvoltage.
Extra care must be taken if the VDD_HV_A supply is alsobeing used to power the external ballast transistor or the deviceis running in internal regulation mode. In these modes, theinrush current on device Power Up or on exit from Low PowerModes is significant and may case the VDD_HV_A voltage todrop resulting in an LVD reset event. To avoid this, the boardlayout should be optimized to reduce common trace resistanceor additional capacitance at the ballast transistor collector (orVDD_HV_A pins in the case of internal regulation mode) isrequired. NXP recommends that customers simulate theexternal voltage supply circuitry.
In all circumstances, the voltage on VDD_HV_A must bemaintained within the specified operating range (seeRecommended operating conditions) to prevent LVD events.
4.5 Voltage monitor electrical characteristicsTable 6. Voltage monitor electrical characteristics
Symbol Parameter State Conditions Configuration Threshold Unit
Power Up1
MaskOpt2
ResetType
Min Typ Max V
VPOR_LV LV supply poweron reset detector
Fall Untrimmed Yes No Destructive
0.930 0.979 1.028 V
Trimmed - - - V
Table continues on the next page...
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 15
Table 6. Voltage monitor electrical characteristics (continued)
Symbol Parameter State Conditions Configuration Threshold Unit
Power Up1
MaskOpt2
ResetType
Min Typ Max V
Rise Untrimmed 0.980 1.029 1.078 V
Trimmed - - - V
VHVD_LV_col
d
LV supply highvoltagemonitoring,detecting atdevice pin
Fall Untrimmed No Yes Functional
Disabled at Start
Trimmed 1.3200 1.3475 1.3750 V
Rise Untrimmed Disabled at Start
Trimmed 1.3400 1.3650 1.3950 V
VLVD_LV_PD
2_hot
LV supply lowvoltagemonitoring,detecting on thePD2 core (hot)area
Fall Untrimmed Yes No Destructive
1.0800 1.1200 1.1600 V
Trimmed 1.1250 1.1425 1.1600 V
Rise Untrimmed 1.1000 1.1400 1.1800 V
Trimmed 1.1450 1.1625 1.1800 V
VLVD_LV_PD
1_hot (BGFP)
LV supply lowvoltagemonitoring,detecting on thePD1 core (hot)area
Fall Untrimmed Yes No Destructive
1.0800 1.1200 1.1600 V
Trimmed 1.1140 1.1370 1.1600 V
Rise Untrimmed 1.1000 1.140 1.1800 V
Trimmed 1.1340 1.1570 1.1800 V
VLVD_LV_PD
0_hot (BGFP)
LV supply lowvoltagemonitoring,detecting on thePD0 core (hot)area
Fall Untrimmed Yes No Destructive
1.0800 1.1200 1.1600 V
Trimmed 1.1140 1.1370 1.1600 V
Rise Untrimmed 1.1000 1.1400 1.1800 V
Trimmed 1.1340 1.1570 1.1800 V
VPOR_HV HV supply poweron reset detector
Fall Untrimmed Yes No Destructive
2.7000 2.8500 3.0000 V
Trimmed - - - V
Rise Untrimmed 2.7500 2.9000 3.0500 V
Trimmed - - - V
VLVD_IO_A_L
O, 3
HV IO_A supplylow voltagemonitoring - lowrange
Fall Untrimmed Yes No Destructive
2.7500 2.9230 3.0950 V
Trimmed 2.9780 3.0390 3.1000 V
Rise Untrimmed 2.7800 2.9530 3.1250 V
Trimmed 3.0080 3.0690 3.1300 V
VLVD_IO_A_H
I3
HV IO_A supplylow voltagemonitoring - highrange
Fall Trimmed No Yes Destructive
Disabled at Start
4.0600 4.151 4.2400 V
Rise Trimmed Disabled at Start
4.1150 4.2010 4.3000 V
VLVD_LV_PD
2_cold
LV supply lowvoltagemonitoring,detecting at thedevice pin
Fall Untrimmed No Yes Functional
Disabled at Start
Trimmed 1.1400 1.1550 1.1750 V
Rise Untrimmed Disabled at Start
Trimmed 1.1600 1.1750 1.1950 V
1. All monitors that are active at power-up will gate the power up recovery and prevent exit from POWERUP phase until theminimum level is crossed. These monitors can in some cases be masked during normal device operation, but when activewill always generate a destructive reset.
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
16 Freescale Semiconductor, Inc.
2. Voltage monitors marked as non maskable are essential for device operation and hence cannot be masked.3. There is no voltage monitoring on the VDD_HV_ADC0, VDD_HV_ADC1, VDD_HV_B and VDD_HV_C I/O segments. For applications
requiring monitoring of these segments, either connect these to VDD_HV_A at the PCB level or monitor externally.
4.6 Supply current characteristics
Current consumption data is given in the following table. These specifications are designtargets and are subject to change per device characterization.
NOTEThe ballast must be chosen in accordance with the ballasttransistor supplier operating conditions and recommendations.
Table 7. Current consumption characteristics
Symbol Parameter Conditions1 Min Typ Max Unit
IDD_BODY_1
2, 3
RUN Body Mode Profile Operatingcurrent
LV supply + HV supply + HVFlash supply +
2 x HV ADC supplies4
Ta = 125°C , 5
VDD_LV = 1.25 V
VDD_HV_A = 5.5V
SYS_CLK = 80MHz
— — 147 mA
Ta = 105°C — — 142 mA
Ta = 85 °C — — 137 mA
IDD_BODY_2
6
RUN Body Mode Profile Operatingcurrent
LV supply + HV supply + HVFlash supply + 2 x HV ADCsupplies4
Ta = 125°C5
VDD_LV = 1.25 V
VDD_HV_A = 5.5V
SYS_CLK = 160MHz
— — 246 mA
Ta = 105°C — — 235 mA
Ta = 85°C — — 210 mA
IDD_BODY_3
7
RUN Body Mode Profile Operatingcurrent
LV supply + HV supply + HVFlash supply + 2 x HV ADCsupplies4
Ta = 125 °C 5
VDD_LV = 1.25 V
VDD_HV_A = 5.5V
SYS_CLK = 120MHz
— — 181 mA
Ta = 105 °C — — 176 mA
Ta = 85°C — — 171 mA
Table continues on the next page...
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 17
Table 7. Current consumption characteristics (continued)
Symbol Parameter Conditions1 Min Typ Max Unit
IDD_BODY_48 RUN Body Mode Profile Operating
currentLV supply + HV supply + HVFlash supply + 2 x HV ADCsupplies4
Ta = 125 °C 5
VDD_LV = 1.25 V
VDD_HV_A = 5.5V
SYS_CLK = 120MHz
— — 264 mA
Ta = 105 °C — — 176 mA
Ta = 85 °C — — 171 mA
IDD_STOP STOP mode Operating current Ta = 125 °C9
VDD_LV = 1.25 V
— — 49 mA
Ta = 105 °C
VDD_LV = 1.25 V
— 10.6 —
Ta = 85 °C
VDD_LV = 1.25 V
— 8.1 —
Ta = 25 °C
VDD_LV = 1.25 V
— 4.6 —
IDD_HV_ADC_REF10, 11 ADC REF Operating current Ta = 125 °C5
2 ADCs operating at 80 MHz
VDD_HV_ADC_REF = 5.5 V
— 200 400 µA
Ta = 105 °C
2 ADCs operating at 80 MHz
VDD_HV_ADC_REF = 5.5 V
— 200 —
Ta = 85 °C
2 ADCs operating at 80 MHz
VDD_HV_ADC_REF = 5.5 V
— 200 —
Ta = 25 °C
2 ADCs operating at 80 MHz
VDD_HV_ADC_REF = 3.6 V
— 200 —
IDD_HV_ADCx11 ADC HV Operating current Ta = 125 °C5
ADC operating at 80 MHz
VDD_HV_ADC = 5.5 V
— 1.2 2 mA
Ta = 25 °C
ADC operating at 80 MHz
VDD_HV_ADC = 3.6 V
— 1 2
IDD_HV_FLASH12 Flash Operating current during read
accessTa = 125 °C5
3.3 V supplies
160 MHz frequency
— 40 45 mA
Ta = 105 °C — 40 45
Table continues on the next page...
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
18 Freescale Semiconductor, Inc.
Table 7. Current consumption characteristics (continued)
Symbol Parameter Conditions1 Min Typ Max Unit
3.3 V supplies
160 MHz frequency
Ta = 85 °C
3.3 V supplies
160 MHz frequency
— 40 45
1. The content of the Conditions column identifies the components that draw the specific current.2. Single e200Z4 core cache disabled @80 MHz, no FlexRay, no ENET, 2 x CAN, 8 LINFlexD, 2 SPI, ADC0 and 1 used
constantly, no HSM, Memory: 2M flash, 128K RAM RUN mode, Clocks: FIRC on, XOSC, PLL on, SIRC on for TOD, no32KHz crystal (TOD runs off SIRC).
3. Recommended Transistors:MJD31 @ 85°C, 105°C and 125°C. In case of internal ballast mode, it is expected that theexternal ballast is not mounted and BAL_SELECT_INT pin is tied to VDD_HV_A supply on board. Internal ballast can beused for all use cases with current consumption upto 150mA
4. The power consumption does not consider the dynamic current of I/Os5. Tj=150°C. Assumes Ta=125°C
• Assumes maximum θJA of 2s2p board. SeeThermal attributes6. e200Z4 core, 160MHz, cache enabled; e200Z2 core , 80MHz, no FlexRay, no ENET, 7 CAN, 16 LINFlexD, 4 SPI, 1x ADC
used constantly, includes HSM at start-up / periodic use, Memory: 3M flash, 256K RAM, Clocks: FIRC on, XOSC on, PLLon, SIRC on, no 32KHz crystal
7. e200Z4 core, 120MHz, cache enabled; e200Z2 core, 60MHz; no FlexRay, no ENET, 7 CAN, 16 LINFlexD, 4 SPI, 1x ADCused constantly, includes HSM at start-up / periodic use, Memory: 3M flash, 128K RAM, Clocks: FIRC on, XOSC on, PLLon, SIRC on, no 32KHz crystal
8. e200Z4 core, 160MHz, cache enabled; e200Z4 core, 80MHz; HSM fully operational (Z0 core @80MHz) FlexRay, 5x CAN,5x LINFlexD, 2x SPI, 1x ADC used constantly, 1xeMIOS (5 ch), Memory: 3M flash, 384K RAM, Clocks: FIRC on, XOSCon, PLL on, SIRC on, no 32KHz crystal
9. Assuming Ta=Tj, as the device is in Stop mode. Assumes maximum θJA of 2s2p board. SeeThermal attributes.10. Internal structures hold the input voltage less than VDD_HV_ADC_REF + 1.0 V on all pads powered by VDDA supplies, if the
maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications.11. This value is the total current for two ADCs.Each ADC might consume upto 2mA at max.12. This assumes the default configuration of flash controller register. For more details, refer to Flash memory program and
erase specifications
Table 8. Low Power Unit (LPU) Current consumption characteristics
Symbol Parameter Conditions1 Min Typ Max Unit
LPU_RUN with 256K RAM Ta = 25 °C
SYS_CLK = 16MHz
ADC0 = OFF, SPI0 = OFF, LIN0 = OFF, CAN0 = OFF
— 10 — mA
Ta = 85 °C
SYS_CLK = 16MHz
ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON
— 10.5 —
Ta = 105 °C
SYS_CLK = 16MHz
ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON
— 11 —
Ta = 125 °C, 2
SYS_CLK = 16MHz
ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON
— — 26
Table continues on the next page...
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 19
Table 8. Low Power Unit (LPU) Current consumption characteristics(continued)
Symbol Parameter Conditions1 Min Typ Max Unit
LPU_STOP with 256K RAM Ta = 25 °C — 0.18 — mA
Ta = 85 °C — 0.60 —
Ta = 105 °C — 1.00 —
Ta = 125 °C 2 — — 10.6
1. The content of the Conditions column identifies the components that draw the specific current.2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum θJA of 2s2p board. SeeThermal
attributes
Table 9. STANDBY Current consumption characteristics
Symbol Parameter Conditions1 Min Typ Max Unit
STANDBY0 STANDBY with8K RAM
Ta = 25 °C — 43 — µA
Ta = 85 °C — 125 —
Ta = 105 °C — 195 —
Ta = 125 °C , 2 — 2100
STANDBY1 STANDBY with64K RAM
Ta = 25 °C — 44.4 — µA
Ta = 85 °C — 140 —
Ta = 105 °C — 225 —
Ta = 125 °C 2 — 2700
STANDBY2 STANDBY with128K RAM
Ta = 25 °C — 46.1 — µA
Ta = 85 °C — 155 —
Ta = 105 °C — 255 —
Ta = 125 °C 2 — 3400
STANDBY3 STANDBY with256K RAM
Ta = 25 °C — 49.5 — µA
Ta = 85 °C — 180 —
Ta = 105 °C — 290 —
Ta = 125 °C 2 — 4800
1. The content of the Conditions column identifies the components that draw the specific current.2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum θJA of 2s2p board. SeeThermal
attributes
4.7 Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) areapplied to the pins of each sample according to each pin combination. The sample sizedepends on the number of supply pins in the device (3 parts × (n + 1) supply pin). Thistest conforms to the AEC-Q100-002/-003/-011 standard.
General
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
20 Freescale Semiconductor, Inc.
NOTEA device will be defined as a failure if after exposure to ESDpulses the device no longer meets the device specificationrequirements. Complete DC parametric and functional testingshall be performed per applicable device specification at roomtemperature followed by hot temperature, unless specifiedotherwise in the device specification.
Table 10. ESD ratings
Symbol Parameter Conditions1 Class Max value2 Unit
VESD(HBM) Electrostatic discharge
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C 2000 V
VESD(CDM) Electrostatic discharge
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A 500
750 (corners)
V
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.2. Data based on characterization results, not tested in production.
4.8 Electromagnetic Compatibility (EMC) specifications
EMC measurements to IC-level IEC standards are available from Freescale on request.
I/O parameters
5.1 AC specifications @ 3.3 V RangeTable 11. Functional Pad AC Specifications @ 3.3 V Range
Symbol Prop. Delay (ns)1
L>H/H>L
Rise/Fall Edge (ns) Drive Load (pF) ipp_sre[1:0]
Min Max Min Max MSB,LSB
pad_sr_hv
(output)
6/6 1.9/1.5 25 11
2.5/2.5 8.25/7.5 0.8/0.6 3.25/3 50
6.4/5 19.5/19.5 3.5/2.5 12/12 200
2.2/2.5 8/8 0.55/0.5 3.9/3.5 25 10
0.090 1.1 0.035 1.1 asymmetry2
2.9/3.5 12.5/11 1/1 7/6 50
11/8 35/31 7.7/5 25/21 200
Table continues on the next page...
5
I/O parameters
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 21
Table 11. Functional Pad AC Specifications @ 3.3 V Range (continued)
Symbol Prop. Delay (ns)1
L>H/H>L
Rise/Fall Edge (ns) Drive Load (pF) ipp_sre[1:0]
Min Max Min Max MSB,LSB
8.3/9.6 45/45 4/3.5 25/25 50 01
13.5/15 65/65 6.3/6.2 30/30 200
13/13 75/75 6.8/6 40/40 50 003
21/22 100/100 11/11 51/51 200
pad_i_hv/pad_sr_hv
(input)4
2/2 0.5/0.5 0.5 NA
1. As measured from 50% of core side input to Voh/Vol of the output2. This row specifies the min and max asymmetry between both the prop delay and the edge rates for a given PVT and 25pF
load. Required for the Flexray spec.3. Slew rate control modes4. Input slope = 2ns
NOTEData based on characterization results, not tested in production.
5.2 DC electrical specifications @ 3.3V RangeTable 12. DC electrical specifications @ 3.3V Range
Symbol Parameter Value Unit
Min Max
Vih (pad_i_hv) Pad_I_HV Input Buffer High Voltage 0.72*VDD_HV_x
VDD_HV_x +0.3
V
Vil (pad_i_hv) Pad_I_HV Input Buffer Low Voltage VDD_HV_x -0.3
0.45*VDD_HV_x
V
Vhys (pad_i_hv) Pad_I_HV Input Buffer Hysteresis 0.11*VDD_HV_x
V
Vih_hys CMOS Input Buffer High Voltage (with hysteresisenabled)
0.67*VDD_HV_x
VDD_HV_x +0.3
V
Vil_hys CMOS Input Buffer Low Voltage (with hysteresisenabled)
VDD_HV_x -0.3
0.35*VDD_HV_x
V
Vih CMOS Input Buffer High Voltage (with hysteresisdisabled)
0.57 *VDD_HV_x1
VDD_HV_x1 +0.3
V
Vil CMOS Input Buffer Low Voltage (with hysteresisdisabled)
VDD_HV_x -0.3
0.4 *VDD_HV_x1
V
Vhys CMOS Input Buffer Hysteresis 0.09 *VDD_HV_x1
V
Pull_IIH (pad_i_hv) Weak Pullup Current2 Low 15 µA
Pull_IIH (pad_i_hv) Weak Pullup Current3 High 55 µA
Pull_IIL (pad_i_hv) Weak Pulldown Current3 Low 28 µA
Table continues on the next page...
I/O parameters
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
22 Freescale Semiconductor, Inc.
Table 12. DC electrical specifications @ 3.3V Range (continued)
Symbol Parameter Value Unit
Min Max
Pull_IIL (pad_i_hv) Weak Pulldown Current2 High 85 µA
Pull_Ioh Weak Pullup Current4 15 50 µA
Pull_Iol Weak Pulldown Current5 15 50 µA
Iinact_d Digital Pad Input Leakage Current (weak pull inactive) -2.5 2.5 µA
Voh Output High Voltage6 0.8*VDD_HV_x1
— V
Vol Output Low Voltage7 — 0.1*VDD_HV_x1
V
Ioh_f Full drive Ioh8 (ipp_sre[1:0] = 11) 18 70 mA
Iol_f Full drive Iol8 (ipp_sre[1:0] = 11) 21 120 mA
Ioh_h Half drive Ioh8 (ipp_sre[1:0] = 10) 9 35 mA
Iol_h Half drive Iol8 (ipp_sre[1:0] = 10) 10.5 60 mA
1. VDD_HV_x = VDD_HV_A, VDD_HV_B, VDD_HV_C2. Measured when pad=0.69*VDD_HV_x3. Measured when pad=0.49*VDD_HV_x4. Measured when pad = 0 V5. Measured when pad = VDD_HV_x6. Measured when pad is sourcing 2 mA7. Measured when pad is sinking 2 mA8. Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.
5.3 AC specifications @ 5 V RangeTable 13. Functional Pad AC Specifications @ 5 V Range
Symbol Prop. Delay (ns)1
L>H/H>L
Rise/Fall Edge (ns) Drive Load (pF) ipp_sre[1:0]
Min Max Min Max MSB,LSB
pad_sr_hv
(output)
4.5/4.5 1.3/1.2 25 11
6/6 2.5/2 50
13/13 9/9 200
5.25/5.25 3/2 25 10
9/8 5/4 50
22/22 18/16 200
27/27 13/13 50 012
40/40 24/24 200
40/40 24/24 50 002
65/65 40/40 200
pad_i_hv/pad_sr_hv
(input)
1.5/1.5 0.5/0.5 0.5 NA
I/O parameters
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 23
1. As measured from 50% of core side input to Voh/Vol of the output2. Slew rate control modes
5.4 DC electrical specifications @ 5 V RangeTable 14. DC electrical specifications @ 5 V Range
Symbol Parameter Value Unit
Min Max
Vih (pad_i_hv) pad_i_hv Input Buffer High Voltage 0.7*VDD_HV_x VDD_HV_x +0.3
V
Vil (pad_i_hv) pad_i_hv Input Buffer Low Voltage VDD_HV_x -0.3
0.45*VDD_HV_x
V
Vhys (pad_i_hv) pad_i_hv Input Buffer Hysteresis 0.09*VDD_HV_x
V
Vih_hys CMOS Input Buffer High Voltage (with hysteresisenabled)
0.65*VDD_HV_x
VDD_HV_x +0.3
V
Vil_hys CMOS Input Buffer Low Voltage (with hysteresisenabled)
VDD_HV_x -0.3
0.35*VDD_HV_x
V
Vih CMOS Input Buffer High Voltage (with hysteresisdisabled)
0.55 *VDD_HV_x1
VDD_HV_x1 +0.3
V
Vil CMOS Input Buffer Low Voltage (with hysteresisdisabled)
VDD_HV_x -0.3
0.40 *VDD_HV_x1
V
Vhys CMOS Input Buffer Hysteresis 0.09 *VDD_HV_x1
V
Pull_IIH (pad_i_hv) Weak Pullup Current2 Low 23 µA
Pull_IIH (pad_i_hv) Weak Pullup Current3 High 82 µA
Pull_IIL (pad_i_hv) Weak Pulldown Current3 Low 40 µA
Pull_IIL (pad_i_hv) Weak Pulldown Current2 High 130 µA
Pull_Ioh Weak Pullup Current4 30 80 µA
Pull_Iol Weak Pulldown Current5 30 80 µA
Iinact_d Digital Pad Input Leakage Current (weak pull inactive) -2.5 2.5 µA
Voh Output High Voltage6 0.8 *VDD_HV_x1
— V
Vol Output Low Voltage7 — 0.1 *VDD_HV_x1
V
Ioh_f Full drive Ioh8 (ipp_sre[1:0] = 11) 18 70 mA
Iol_f Full drive Iol8 (ipp_sre[1:0] = 11) 21 120 mA
Ioh_h Half drive Ioh8 (ipp_sre[1:0] = 10) 9 35 mA
Iol_h Half drive Iol8 (ipp_sre[1:0] = 10) 10.5 60 mA
1. VDD_HV_x = VDD_HV_A, VDD_HV_B, VDD_HV_C2. Measured when pad=0.69*VDD_HV_x3. Measured when pad=0.49*VDD_HV_x4. Measured when pad = 0 V5. Measured when pad = VDD_HV_x6. Measured when pad is sourcing 2 mA7. Measured when pad is sinking 2 mA
I/O parameters
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
24 Freescale Semiconductor, Inc.
8. Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.
5.5 Reset pad electrical characteristics
The device implements a dedicated bidirectional RESET pin.
VIL
VDD_HV_IOx
device reset forced by PORST
VDDMIN
PORST
VIH
device start-up phase
AAA
A
Figure 3. Start-up reset requirements
VPORST
VIL
VIH
VDD_HV_IO
filtered by hysteresis
filtered by lowpass filter
WFRST
WNFRST
hw_rst
‘1’
‘0’filtered by lowpass filter
WFRST
unknown resetstate device under hardware reset
A
Figure 4. Noise filtering on reset signal
I/O parameters
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 25
Table 15. Functional reset pad electrical specifications
Symbol Parameter Conditions Value Unit
Min Typ Max
VIH CMOS Input Buffer High Voltage — 0.65*VD
D_HV_x
— VDD_HV_x+0.3
V
VIL CMOS Input Buffer Low Voltage — VDD_HV_
x-0.3— 0.35*VDD_HV
_x
V
VHYS CMOS Input Buffer hysterisis — 300 — — mV
VDD_POR Minimum supply for strong pull-downactivation
— — — 1.2 V
IOL_R Strong pull-down current 1 Device under power-on reset
VDD_HV_A= V DD_POR
VOL = 0.35*VDD_HV_A
0.2 — — mA
Device under power-on reset
VDD_HV_A= V DD_POR
VOL = 0.35*VDD_HV_IO
11 — — mA
WFRST RESET input filtered pulse — — — 500 ns
WNFRST RESET input not filtered pulse — 2000 — — ns
|IWPU| Weak pull-up current absolute value RESET pin VIN = VDD 23 — 82 µA
1. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for RESET.
5.6 PORST electrical specificationsTable 16. PORST electrical specifications
Symbol Parameter Value Unit
Min Typ Max
WFPORST PORST input filtered pulse — — 200 ns
WNFPORST PORST input not filtered pulse 1000 — — ns
VIH Input high level 0.65 xVDD_HV_A
— — V
VIL Input low level — — 0.35 xVDD_HV_A
V
I/O parameters
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
26 Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviours
Analog
6.1.1 ADC electrical specifications
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
(2 )
(1)
(3 ) (4)
(5)
Offset Error OSE
Offset Error OSE
Gain Error GE
1 LSB (ideal)
Vin(A) (LSBideal)
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve
code out
4095 4094 4093 4092 4091 4090
5 4 3 2 1
0
7 6
1 2 3 4 5 6 7 4089 4090 4091 4092 4093 4094 4095
1 LSB ideal =(VrefH-VrefL)/ 4096 = 3.3V/ 4096 = 0.806 mV Total Unadjusted Error TUE = +/- 6 LSB = +/- 4.84mV
Figure 5. ADC characteristics and error definitions
6
6.1
Peripheral operating requirements and behaviours
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 27
6.1.1.1 Input equivalent circuit and ADC conversion characteristics
RF
CF
RS RL RSW1
CP2
VDD_IO
Sampling Source Filter Current Limiter
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME
RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance
CP1
RAD
Channel Selection
VA CS
Figure 6. Input equivalent circuit
NOTEThe ADC performance specifications are not guaranteed if twoADCs simultaneously sample the same shared channel.
Table 17. ADC conversion characteristics (for 12-bit)
Symbol Parameter Conditions Min Typ1 Max Unit
fCK ADC Clock frequency (depends onADC configuration) (The duty cycledepends on AD_CK2 frequency)
— 15.2 80 80 MHz
fs Sampling frequency 80 MHz — — 1.00 MHz
tsample Sample time3 80 MHz@ 100 ohm sourceimpedance
250 — — ns
tconv Conversion time4 80 MHz 700 — — ns
ttotal_conv Total Conversion time tsample +tconv (for standard and extendedchannels)
80 MHz 1.55 — — µs
Total Conversion time tsample +tconv (for precision channels)
1 — —
CS, 6 ADC input sampling capacitance — — 3 5 pF
CP16 ADC input pin capacitance 1 — — — 5 pF
CP26 ADC input pin capacitance 2 — — — 0.8 pF
RSW16 Internal resistance of analog
sourceVREF range = 4.5 to 5.5 V — — 0.3 kΩ
VREF range = 3.15 to 3.6 V — — 875 Ω
Table continues on the next page...
Analog
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
28 Freescale Semiconductor, Inc.
Table 17. ADC conversion characteristics (for 12-bit) (continued)
Symbol Parameter Conditions Min Typ1 Max Unit
RAD6 Internal resistance of analog
source— — — 825 Ω
INL Integral non-linearity (precisechannel)
— –2 — 2 LSB
INL Integral non-linearity (standardchannel)
— –3 — 3 LSB
DNL Differential non-linearity — –1 — 1 LSB
OFS Offset error — –6 — 6 LSB
GNE Gain error — –4 — 4 LSB
ADC Analog Pad(pad going to one
ADC)
Max leakage (precision channel) 150 °C — — 250 nA
Max leakage (standard channel) 150 °C — — 2500 nA
Max positive/negative injection –5 — 5 mA
TUEprecision channels Total unadjusted error for precisionchannels
Without current injection –6 +/-4 6 LSB
With current injection7 +/-5 LSB
TUEstandard/extended
channels
Total unadjusted error for standard/extended channels
Without current injection –8 +/-6 8 LSB
With current injection7 +/-8 LSB
trecovery STOP mode to Run mode recoverytime
< 1 µs
1. Active ADC input, VinA < [min(ADC_VrefH, ADC_ADV, VDD_HV_IOx)]. VDD_HV_IOx refers to I/O segment supplyvoltage. Violation of this condition would lead to degradation of ADC performance. Please refer to Table: 'Absolutemaximum ratings' to avoid damage. Refer to Table: 'Recommended operating conditions (VDD_HV_x = 3.3 V)' for requiredrelation between IO_supply_A,B,C and ADC_Supply.
2. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheralclock based on register configuration in the ADC.
3. During the sample time the input capacitance CS can be charged/discharged by the external source. The internalresistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of thesample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sampleclock tsample depend on programming.
4. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time toload the result register with the conversion result.
5. Apart from tsample and tconv, few cycles are used up in ADC digital interface and hence the overall throughput from theADC is lower.
6. See Figure 2.7. Current injection condition for ADC channels is defined for an inactive ADC channel (on which conversion is NOT being
performed), and this occurs when voltage on the ADC pin exceeds the I/O supply or ground. However, absolute maximumvoltage spec on pad input (VINA, see Table: Absolute maximum ratings) must be honored to meet TUE spec quoted here
Table 18. ADC conversion characteristics (for 10-bit)
Symbol Parameter Conditions Min Typ1 Max Unit
fCK ADC Clock frequency (depends onADC configuration) (The duty cycledepends on AD_CK2 frequency.)
— 15.2 80 80 MHz
fs Sampling frequency — — — 1.00 MHz
tsample Sample time3 80 MHz@ 100 ohm sourceimpedance
275 — — ns
tconv Conversion time4 80 MHz 550 — — ns
Table continues on the next page...
Analog
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 29
Table 18. ADC conversion characteristics (for 10-bit) (continued)
Symbol Parameter Conditions Min Typ1 Max Unit
ttotal_conv Total Conversion time tsample +tconv (for standard channels)
80 MHz 1 — — µs
Total Conversion time tsample +tconv (for extended channels)
1.5 — —
CS ADC input sampling capacitance — — 3 5 pF
CP15 ADC input pin capacitance 1 — — — 5 pF
CP25 ADC input pin capacitance 2 — — — 0.8 pF
RSW15 Internal resistance of analog
sourceVREF range = 4.5 to 5.5 V — — 0.3 kΩ
VREF range = 3.15 to 3.6 V — — 875 Ω
RAD5 Internal resistance of analog
source— — — 825 Ω
INL Integral non-linearity — –2 — 2 LSB
DNL Differential non-linearity — –1 — 1 LSB
OFS Offset error — –4 — 4 LSB
GNE Gain error — –4 — 4 LSB
ADC Analog Pad(pad going to one
ADC)
Max leakage (standard channel) 150 °C — — 2500 nA
Max positive/negative injection –5 — 5 mA
TUEstandard/extended
channels
Total unadjusted error for standardchannels
Without current injection –4 +/-3 4 LSB
With current injection6 +/-4 LSB
trecovery STOP mode to Run mode recoverytime
< 1 µs
1. Active ADC Input, VinA < [min(ADC_ADV, IO_Supply_A,B,C)]. Violation of this condition would lead to degradation of ADCperformance. Please refer to Table: 'Absolute maximum ratings' to avoid damage. Refer to Table: 'Recommendedoperating conditions' for required relation between IO_supply_A, B, C and ADC_Supply.
2. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheralclock based on register configuration in the ADC.
3. During the sample time the input capacitance CS can be charged/discharged by the external source. The internalresistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of thesample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sampleclock tsample depend on programming.
4. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time toload the result register with the conversion result.
5. See Figure 2-16. Current injection condition for ADC channels is defined for an inactive ADC channel (on which conversion is NOT being
performed), and this occurs when voltage on the ADC pin exceeds the I/O supply or ground. However, absolute maximumvoltage spec on pad input (VINA, see Table: Absolute maximum ratings) must be honored to meet TUE spec quoted here
6.1.2 Analog Comparator (CMP) electrical specificationsTable 19. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 250 μA
Table continues on the next page...
Analog
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
30 Freescale Semiconductor, Inc.
Table 19. Comparator and 6-bit DAC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — 5 11 μA
VAIN Analog input voltage VSS — VIN1_CMP_RE
F
V
VAIO Analog input offset voltage 1 -47 — 47 mV
VH Analog comparator hysteresis 2
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
1
20
40
60
25
50
70
105
mV
mV
mV
mV
tDHS Propagation Delay, High Speed Mode (Full Swing) 1, 3 — — 250 ns
tDLS Propagation Delay, Low power Mode (Full Swing) 1, 3 — 5 21 μs
Analog comparator initialization delay, High speedmode4
— 4 μs
Analog comparator initialization delay, Low speedmode 4
— 100 μs
IDAC6b 6-bit DAC current adder (when enabled)
3.3V Reference Voltage — 6 9 μA
5V Reference Voltage — 10 16 μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB5
DNL 6-bit DAC differential non-linearity –0.8 — 0.8 LSB
1. Measured with hysteresis mode of 002. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_HV_A-0.6V3. Full swing = VIH, VIL4. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.5. 1 LSB = Vreference/64
Clocks and PLL interfaces modules
6.2.1 Main oscillator electrical characteristics
This device provides a driver for oscillator in pierce configuration with amplitudecontrol. Controlling the amplitude allows a more sinusoidal oscillation, reducing in thisway the EMI. Other benefits arises by reducing the power consumption. This LoopControlled Pierce (LCP mode) requires good practices to reduce the stray capacitance oftraces between crystal and MCU.
6.2
Clocks and PLL interfaces modules
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 31
An operation in Full Swing Pierce (FSP mode), implemented by an inverter is alsoavailable in case of parasitic capacitances and cannot be reduced by using crystal withhigh equivalent series resistance. For this mode, a special care needs to be takenregarding the serial resistance used to avoid the crystal overdrive.
Other two modes called External (EXT Wave) and disable (OFF mode) are provided. ForEXT Wave, the drive is disabled and an external source of clock within CMOS levelbased in analog oscillator supply can be used. When OFF, EXTAL is pulled down by 240Kohms resistor and the feedback resistor remains active connecting XTAL throughEXTAL by 1M resistor.
Figure 7. Oscillator connections scheme
Table 20. Main oscillator electrical characteristics
Symbol Parameter Mode Conditions Min Typ Max Unit
fXOSCHS Oscillatorfrequency
FSP/LCP 8 40 MHz
Table continues on the next page...
Clocks and PLL interfaces modules
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
32 Freescale Semiconductor, Inc.
Table 20. Main oscillator electrical characteristics (continued)
Symbol Parameter Mode Conditions Min Typ Max Unit
gmXOSCHS DriverTransconductance
LCP 23 mA/V
FSP 33
VXOSCHS OscillationAmplitude
LCP1, 2 8 MHz 1.0 VPP
16 MHz 1.0
40 MHz 0.8
TXOSCHSSU Startup time FSP/LCP1 8 MHz 2 ms
16 MHz 1
40 MHz 0.5
OscillatorAnalog Circuitsupply current
FSP 8 MHz 2.2 mA
16 MHz 2.2
40 MHz 3.2
LCP 8 MHz 141 uA
16 MHz 252
40 MHz 518
VIH Input Highlevel CMOSSchmitt trigger
EXT Wave Oscillatorsupply=3.3
1.95 V
VIL Input low levelCMOSSchmitt trigger
EXT Wave Oscillatorsupply=3.3
1.25 V
1. Values are very dependent on crystal or resonator used and parasitic capacitance observed in the board.2. Typ value for oscillator supply 3.3 V@27 °C
6.2.2 32 kHz Oscillator electrical specificationsTable 21. 32 kHz oscillator electrical specifications
Symbol Parameter Condition Min Typ Max Unit
fosc_lo Oscillator crystalor resonatorfrequency
32 40 KHz
tcst Crystal Start-upTime1, 2
2 s
1. This parameter is characterized before qualification rather than 100% tested.2. Proper PC board layout procedures must be followed to achieve specifications.
Clocks and PLL interfaces modules
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 33
6.2.3 16 MHz RC Oscillator electrical specificationsTable 22. 16 MHz RC Oscillator electrical specifications
Symbol Parameter Conditions Value Unit
Min Typ Max
FTarget IRC target frequency — — 16 — MHz
PTA IRC frequency variation after trimming — -5 — 5 %
Tstartup Startup time — — 1.5 us
TSTJIT Cycle to cycle jitter — — 1.5 %
TLTJIT Long term jitter — — 0.2 %
IVDDHV Current consumption on 3.3 V powersupply
After Tstartup — — 75 µA
IVDDLV Current consumption on 1.2 V powersupply
After Tstartup — — 25 µA
NOTEThe above start up time of 1 us is equivalent to 16 cycles of 16MHz.
6.2.4 128 KHz Internal RC oscillator Electrical specificationsTable 23. 128 KHz Internal RC oscillator electrical specifications
Symbol Parameter Condition Min Typ Max Unit
Foscu1 Oscillator
frequencyCalibrated 119 128 136.5 KHz
Temperaturedependence
600 ppm/C
Supplydependence
18 %/V
Supply current Clock running 2.75 µA
Clock stopped 200 nA
1. Vdd=1.2 V, 1.32V, Ta=-40 C, 125 C
6.2.5 PLL electrical specificationsTable 24. PLL electrical specifications
Parameter Min Typ Max Unit Comments
Input Frequency 8 40 MHz
VCO Frequency Range 600 1280 MHz
Table continues on the next page...
Clocks and PLL interfaces modules
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
34 Freescale Semiconductor, Inc.
Table 24. PLL electrical specifications(continued)
Parameter Min Typ Max Unit Comments
Duty Cycle at pllclkout 48% 52% This specification is guaranteedat PLL IP boundary
Period Jitter See Table 25 ps NON SSCG mode
TIE See Table 25 at 960 M Integrated over 1MHzoffset not valid in SSCG mode
Modulation Depth (Center Spread) +/- 0.25% +/- 3.0%
Modulation Frequency 32 KHz
Lock Time 60 µs Calibration mode
Table 25. Jitter calculation
Type of jitter Jitter due toSupply
Noise (ps)JSN
1
Jitter due toFractional Mode
(ps) JSDM2
Jitter due toFractional Mode
JSSCG (ps) 3
1 SigmaRandomJitter JRJ
(ps) 4
Total Period Jitter (ps)
Period Jitter 60 ps 3% of pllclkout1,2 Modulation depth 0.1% ofpllclkout1,2
+/-(JSN+JSDM+JSSCG+N[4]
×JRJ)
Long Term Jitter(Integer Mode)
40 +/-(N x JRJ)
Long Term jitter(Fractional Mode)
100 +/-(N x JRJ)
1. This jitter component is due to self noise generated due to bond wire inductances on different PLL supplies. The jitter valueis valid for inductor value of 5nH or less each on avdd, avss, dvdd, dvss.
2. This jitter component is added when the PLL is working in the fractional mode.3. This jitter component is added when the PLL is working in the Spread Spectrum Mode. Else it is 0.4. The value of N is dependent on the accuracy requirement of the application. See Percentage of sample exceeding
specified value of jitter table
Table 26. Percentage of sample exceeding specified value of jitter
N Percentage of samples exceeding specified value of jitter(%)
1 31.73
2 4.55
3 0.27
4 6.30 × 1e-03
5 5.63 × 1e-05
6 2.00 × 1e-07
7 2.82 × 1e-10
Clocks and PLL interfaces modules
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 35
Memory interfaces
6.3.1 Flash memory program and erase specifications
NOTEAll timing, voltage, and current numbers specified in thissection are defined for a single embedded flash memory withinan SoC, and represent average currents for given supplies andoperations.
Table 27 shows the estimated Program/Erase times.
Table 27. Flash memory program and erase specifications
Symbol Characteristic1 Typ2 FactoryProgramming3, 4
Field Update Unit
InitialMax
InitialMax, Full
Temp
TypicalEnd ofLife5
Lifetime Max6
20°C ≤TA≤30°C
-40°C ≤TJ≤150°C
-40°C ≤TJ≤150°C
≤ 1,000cycles
≤ 250,000cycles
tdwpgm Doubleword (64 bits) program time 43 100 150 55 500 μs
tppgm Page (256 bits) program time 73 200 300 108 500 μs
tqppgn Quad-page (1024 bits) programtime
268 800 1,200 396 2,000 μs
t16kers 16 KB Block erase time 168 290 320 250 1,000 ms
t16kpgn 16 KB Block program time 34 45 50 40 1,000 ms
t32kers 32 KB Block erase time 217 360 390 310 1,200 ms
t32kpgm 32 KB Block program time 69 100 110 90 1,200 ms
t64kers 64 KB Block erase time 315 490 590 420 1,600 ms
t64kpgm 64 KB Block program time 138 180 210 170 1,600 ms
t256kers 256 KB Block erase time 884 1,520 2,030 1,080 4,000 — ms
t256kpgm 256 KB Block program time 552 720 880 650 4,000 — ms
1. Program times are actual hardware programming times and do not include software overhead. Block program timesassume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 150 cycles, nominal voltage.4. Plant Programing times provide guidance for timeout limits used in the factory.5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.6. Conditions: -40°C ≤ TJ ≤ 150°C, full spec voltage.
6.3
Memory interfaces
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
36 Freescale Semiconductor, Inc.
6.3.2 Flash memory Array Integrity and Margin Read specificationsTable 28. Flash memory Array Integrity and Margin Read specifications
Symbol Characteristic Min Typical Max1 Units2
tai16kseq Array Integrity time for sequential sequence on 16KB block. — — 512 xTperiod x
Nread
—
tai32kseq Array Integrity time for sequential sequence on 32KB block. — — 1024 xTperiod x
Nread
—
tai64kseq Array Integrity time for sequential sequence on 64KB block. — — 2048 xTperiod x
Nread
—
tai256kseq Array Integrity time for sequential sequence on 256KB block. — — 8192 xTperiod x
Nread
—
tmr16kseq Margin Read time for sequential sequence on 16KB block. 73.81 — 110.7 μs
tmr32kseq Margin Read time for sequential sequence on 32KB block. 128.43 — 192.6 μs
tmr64kseq Margin Read time for sequential sequence on 64KB block. 237.65 — 356.5 μs
tmr256kseq Margin Read time for sequential sequence on 256KB block. 893.01 — 1,339.5 μs
1. Array Integrity times need to be calculated and is dependant on system frequency and number of clocks per read. Theequation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) andNread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has theaddress pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in theequation, the results of the equation are also unit accurate.
6.3.3 Flash memory module life specificationsTable 29. Flash memory module life specifications
Symbol Characteristic Conditions Min Typical Units
Array P/Ecycles
Number of program/erase cycles per blockfor 16 KB, 32 KB and 64 KB blocks.1
— 250,000 — P/Ecycles
Number of program/erase cycles per blockfor 256 KB blocks.2
— 1,000 250,000 P/Ecycles
Dataretention
Minimum data retention. Blocks with 0 - 1,000 P/Ecycles.
50 — Years
Blocks with 100,000 P/Ecycles.
20 — Years
Blocks with 250,000 P/Ecycles.
10 — Years
1. Program and erase supported across standard temperature specs.2. Program and erase supported across standard temperature specs.
Memory interfaces
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 37
6.3.4 Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by thefollowing figure. The spec window represents qualified limits. The extrapolated dottedline demonstrates technology capability, however is beyond the qualification limits.
6.3.5 Flash memory AC timing specificationsTable 30. Flash memory AC timing specifications
Symbol Characteristic Min Typical Max Units
tpsus Time from setting the MCR-PSUS bit until MCR-DONE bit is setto a 1.
— 7
plus foursystemclock
periods
9.1
plus foursystemclock
periods
μs
tesus Time from setting the MCR-ESUS bit until MCR-DONE bit is setto a 1.
— 16
plus foursystemclock
periods
20.8
plus foursystemclock
periods
μs
tres Time from clearing the MCR-ESUS or PSUS bit with EHV = 1until DONE goes low.
— — 100 ns
Table continues on the next page...
Memory interfaces
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
38 Freescale Semiconductor, Inc.
Table 30. Flash memory AC timing specifications (continued)
Symbol Characteristic Min Typical Max Units
tdone Time from 0 to 1 transition on the MCR-EHV bit initiating aprogram/erase until the MCR-DONE bit is cleared.
— — 5 ns
tdones Time from 1 to 0 transition on the MCR-EHV bit aborting aprogram/erase until the MCR-DONE bit is set to a 1.
— 16
plus foursystemclock
periods
20.8
plus foursystemclock
periods
μs
tdrcv Time to recover once exiting low power mode. 16
plus sevensystemclock
periods.
— 45
plus sevensystemclock
periods
μs
taistart Time from 0 to 1 transition of UT0-AIE initiating a Margin Reador Array Integrity until the UT0-AID bit is cleared. This time alsoapplies to the resuming from a suspend or breakpoint byclearing AISUS or clearing NAIBP
— — 5 ns
taistop Time from 1 to 0 transition of UT0-AIE initiating an ArrayIntegrity abort until the UT0-AID bit is set. This time also appliesto the UT0-AISUS to UT0-AID setting in the event of a ArrayIntegrity suspend request.
— — 80
plus fifteensystemclock
periods
ns
tmrstop Time from 1 to 0 transition of UT0-AIE initiating a Margin Readabort until the UT0-AID bit is set. This time also applies to theUT0-AISUS to UT0-AID setting in the event of a Margin Readsuspend request.
10.36
plus foursystemclock
periods
— 20.42
plus foursystemclock
periods
μs
6.3.6 Flash read wait state and address pipeline control settings
The following table describes the recommended RWSC and APC settings at variousoperating frequencies based on specified intrinsic flash access times of the flash modulecontroller array at 125 °C.
Table 31. Flash Read Wait State and Address Pipeline ControlCombinations
Flash frequency RWSC setting APC setting
0 MHz < fFlash <= 33 MHz 0 0
33 MHz < fFlash <= 100 MHz 2 1
100 MHz < fFlash <= 133 MHz 3 1
133 MHz < fFlash <= 160 MHz 4 1
Memory interfaces
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 39
Communication interfaces
6.4.1 DSPI timingTable 32. DSPI electrical specifications
No Symbol Parameter Conditions High Speed Mode low Speed mode Unit
Min Max Min Max
1 tSCK DSPI cycletime
Master (MTFE = 0) 25 — 50 — ns
Slave (MTFE = 0) 40 — 60 —
2 tCSC PCS to SCKdelay
— 16 — — — ns
3 tASC After SCKdelay
— 16 — — — ns
4 tSDC SCK dutycycle
— tSCK/2 - 10 tSCK/2 + 10 — — ns
5 tA Slave accesstime
SS active to SOUTvalid
— 40 — — ns
6 tDIS Slave SOUTdisable time
SS inactive to SOUTHigh-Z or invalid
— 10 — — ns
7 tPCSC PCSx toPCSS time
— 13 — — — ns
8 tPASC PCSS toPCSx time
— 13 — — — ns
9 tSUI Data setuptime forinputs
Master (MTFE = 0) NA — 20 — ns
Slave 2 — 2 —
Master (MTFE = 1,CPHA = 0)
15 — 81 —
Master (MTFE = 1,CPHA = 1)
15 — 20 —
10 tHI Data holdtime forinputs
Master (MTFE = 0) NA — –5 — ns
Slave 4 — 4 —
Master (MTFE = 1,CPHA = 0)
0 — 111 —
Master (MTFE = 1,CPHA = 1)
0 — -5 —
11 tSUO Data valid(after SCK
edge)
Master (MTFE = 0) — NA — 4 ns
Slave — 15 — 23
Master (MTFE = 1,CPHA = 0)
— 4 — 161
Master (MTFE = 1,CPHA = 1)
— 4 — 4
12 tHO Data holdtime foroutputs
Master (MTFE = 0) NA — –2 — ns
Table continues on the next page...
6.4
Communication interfaces
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
40 Freescale Semiconductor, Inc.
Table 32. DSPI electrical specifications (continued)
No Symbol Parameter Conditions High Speed Mode low Speed mode Unit
Min Max Min Max
Slave 4 — 6 —
Master (MTFE = 1,CPHA = 0)
-2 — 101 —
Master (MTFE = 1,CPHA = 1)
–2 — –2 —
1. SMPL_PTR should be set to 1
NOTE
Restriction For High Speed modes
• DSPI2, DSPI3, SPI1 and SPI2 will support 40MHz Mastermode SCK
• DSPI2, DSPI3, SPI1 and SPI2 will support 25MHz SlaveSCK frequency
• Only one {SIN,SOUT and SCK} group per DSPI/SPI willsupport high frequency mode
• For Master mode MTFE will be 1 for high speed mode• For high speed slaves, their master have to be in MTFE=1
mode or should be able to support 15ns tSUO delay
NOTEFor numbers shown in the following figures, see Table 32
Table 33. DSPI high speed mode I/Os
DSPI High speed SCK High speed SIN High speed SOUT
DSPI2 GPIO[78] GPIO[76] GPIO[77]
DSPI3 GPIO[100] GPIO[101] GPIO[98]
SPI1 GPIO[173] GPIO[175] GPIO[176]
SPI2 GPIO[79] GPIO[110] GPIO[111]
Communication interfaces
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 41
Data Last DataFirst Data
First Data Data Last Data
SIN
SOUT
PCSx
SCK Output
4
9
12
1
11
10
4
SCK Output
(CPOL=0)
(CPOL=1)
32
Figure 8. DSPI classic SPI timing — master, CPHA = 0
Data Last DataFirst DataSIN
SOUT
12 11
10
Last DataDataFirst Data
SCK Output
SCK Output
PCSx
9
(CPOL=0)
(CPOL=1)
Figure 9. DSPI classic SPI timing — master, CPHA = 1
Communication interfaces
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
42 Freescale Semiconductor, Inc.
Last DataFirst Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
12
SCK Input
First Data Last Data
SCK Input
2
(CPOL=0)
(CPOL=1)
Figure 10. DSPI classic SPI timing — slave, CPHA = 0
5 6
9
12
11
10
Last Data
Last DataSIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL=0)
(CPOL=1)
Figure 11. DSPI classic SPI timing — slave, CPHA = 1
Communication interfaces
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 43
PCSx
3
14
10
4
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
2
(CPOL=0)
(CPOL=1)
Figure 12. DSPI modified transfer format timing — master, CPHA = 0
PCSx
109
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
(CPOL=0)
(CPOL=1)
Figure 13. DSPI modified transfer format timing — master, CPHA = 1
Communication interfaces
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
44 Freescale Semiconductor, Inc.
Last DataFirst Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
SCK Input
First Data Last Data
SCK Input
2
(CPOL=0)
(CPOL=1)
12
Figure 14. DSPI modified transfer format timing – slave, CPHA = 0
5 6
9
12
11
10
Last Data
Last DataSIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL=0)
(CPOL=1)
Figure 15. DSPI modified transfer format timing — slave, CPHA = 1
PCSx
7 8
PCSS
Figure 16. DSPI PCS strobe (PCSS) timing
Communication interfaces
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 45
FlexRay electrical specifications
6.4.2.1 FlexRay timing
This section provides the FlexRay Interface timing characteristics for the input and outputsignals. It should be noted that these are recommended numbers as per the FlexRay EPLv3.0 specification, and subject to change per the final timing analysis of the device.
6.4.2.2 TxEN
dCCTxENRISEdCCTxENFALL
20 %
80 %
TxEN
Figure 17. TxEN signal
Table 34. TxEN output characteristics1
Name Description Min Max Unit
dCCTxENRISE25 Rise time of TxEN signal at CC 9 ns
dCCTxENFALL25 Fall time of TxEN signal at CC 9 ns
dCCTxEN01 Sum of delay between Clk to Q of the last FF and the finaloutput buffer, rising edge
25 ns
dCCTxEN10 Sum of delay between Clk to Q of the last FF and the finaloutput buffer, falling edge
25 ns
1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +±10%, TJ = –40 °C / 150 °C, TxEN pin load maximum 25 pF
6.4.2
FlexRay electrical specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
46 Freescale Semiconductor, Inc.
dCCTxEN10 dCCTxEN01
TxEN
PE_Clk
Figure 18. TxEN signal propagation delays
6.4.2.3 TxD
dCCTxD50%
TxD
dCCTxDFALL dCCTxDRISE
20 %
50 %
80 %
Figure 19. TxD Signal
Table 35. TxD output characteristics
Name Description1 Min Max Unit
dCCTxAsym Asymmetry of sending CC @ 25 pF load (=dCCTxD50% - 100ns)
–2.45 2.45 ns
dCCTxDRISE25+dCCTxDFALL25
Sum of Rise and Fall time of TxD signal at the output 92 ns
Table continues on the next page...
FlexRay electrical specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 47
Table 35. TxD output characteristics (continued)
Name Description1 Min Max Unit
dCCTxD01 Sum of delay between Clk to Q of the last FF and the finaloutput buffer, rising edge
25 ns
dCCTxD10 Sum of delay between Clk to Q of the last FF and the finaloutput buffer, falling edge
25 ns
1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +±10%, TJ = –40 °C / 150 °C, TxD pin load maximum 25 pF.2. For 3.3 V ± 10% operation, this specification is 10 ns.
dCCTxD10 dCCTxD01
TxD
PE_Clk*
*FlexRay Protocol Engine Clock
Figure 20. TxD Signal propagation delays
6.4.2.4 RxDTable 36. RxD input characteristic
Name Description1 Min Max Unit
C_CCRxD Input capacitance onRxD pin
7 pF
uCCLogic_1 Threshold for detectinglogic high
35 70 %
uCCLogic_0 Threshold for detectinglogic low
30 65 %
dCCRxD01 Sum of delay fromactual input to the Dinput of the first FF,
rising edge
10 ns
dCCRxD10 Sum of delay fromactual input to the Dinput of the first FF,
falling edge
10 ns
FlexRay electrical specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
48 Freescale Semiconductor, Inc.
1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +±10%, TJ = –40 oC / 150 oC.
6.4.3 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translatedappropriately to arrive at timing specs/constraints for the physical interface.
6.4.3.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range oftransceiver devices.
Table 37. MII signal switching specifications
Symbol Description Min. Max. Unit
— RXCLK frequency — 25 MHz
MII1 RXCLK pulse width high 35% 65% RXCLK
period
MII2 RXCLK pulse width low 35% 65% RXCLK
period
MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 — ns
MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 — ns
— TXCLK frequency — 25 MHz
MII5 TXCLK pulse width high 35% 65% TXCLK
period
MII6 TXCLK pulse width low 35% 65% TXCLK
period
MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 — ns
MII8 TXCLK to TXD[3:0], TXEN, TXER valid — 25 ns
MII7MII8
Valid data
Valid data
Valid data
MII6 MII5
TXCLK (input)
TXD[n:0]
TXEN
TXER
Figure 21. RMII/MII transmit signal timing diagram
FlexRay electrical specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 49
MII2 MII1
MII4MII3
Valid data
Valid data
Valid data
RXCLK (input)
RXD[n:0]
RXDV
RXER
Figure 22. RMII/MII receive signal timing diagram
6.4.3.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range oftransceiver devices.
Table 38. RMII signal switching specifications
Num Description Min. Max. Unit
— EXTAL frequency (RMII input clock RMII_CLK) — 50 MHz
RMII1 RMII_CLK pulse width high 35% 65% RMII_CLKperiod
RMII2 RMII_CLK pulse width low 35% 65% RMII_CLKperiod
RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 — ns
RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 — ns
RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 — ns
RMII8 RMII_CLK to TXD[1:0], TXEN valid — 15 ns
6.4.4 SAI electrical specifications
All timing requirements are specified relative to the clock period or to the minimumallowed clock period of a device
Table 39. Master mode SAI Timing
no Parameter Value Unit
Min Max
Operating Voltage 2.7 3.6 V
S1 SAI_MCLK cycle time 40 - ns
Table continues on the next page...
FlexRay electrical specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
50 Freescale Semiconductor, Inc.
Table 39. Master mode SAI Timing (continued)
no Parameter Value Unit
Min Max
S2 SAI_MCLK pulse width high/low 45% 55% MCLKperiod
S3 SAI_BCLK cycle time 80 - BCLKperiod
S4 SAI_BCLK pulse width high/low 45% 55% ns
S5 SAI_BCLK to SAI_FS output valid - 15 ns
S6 SAI_BCLK to SAI_FS output invalid 0 - ns
S7 SAI_BCLK to SAI_TXD valid - 15 ns
S8 SAI_BCLK to SAI_TXD invalid 0 - ns
S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 28 - ns
S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 - ns
Figure 23. Master mode SAI Timing
Table 40. Slave mode SAI Timing
No Parameter Value Unit
Min Max
Operating Voltage 2.7 3.6 V
S11 SAI_BCLK cycle time (input) 80 - ns
S12 SAI_BCLK pulse width high/low (input) 45% 55% BCLK period
S13 SAI_FS input setup before SAI_BCLK 10 - ns
S14 SAI_FS input hold after SAI_BCLK 2 - ns
Table continues on the next page...
FlexRay electrical specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 51
Table 40. Slave mode SAI Timing (continued)
No Parameter Value Unit
Min Max
S15 SAI_BCLK to SAI_TXD/SAI_FS output valid - 28 ns
S16 SAI_BCLK to SAI_TXD/SAI_FS output invalid 0 - ns
S17 SAI_RXD setup before SAI_BCLK 10 - ns
S18 SAI_RXD hold after SAI_BCLK 2 - ns
Figure 24. Slave mode SAI Timing
Debug specifications
6.5.1 JTAG interface timingTable 41. JTAG pin AC electrical characteristics 1
# Symbol Characteristic Min Max Unit
1 tJCYC TCK Cycle Time 2 62.5 — ns
2 tJDC TCK Clock Pulse Width 40 60 %
3 tTCKRISE TCK Rise and Fall Times (40% - 70%) — 3 ns
4 tTMSS, tTDIS TMS, TDI Data Setup Time 5 — ns
5 tTMSH, tTDIH TMS, TDI Data Hold Time 5 — ns
6 tTDOV TCK Low to TDO Data Valid — 203 ns
7 tTDOI TCK Low to TDO Data Invalid 0 — ns
8 tTDOHZ TCK Low to TDO High Impedance — 15 ns
11 tBSDV TCK Falling Edge to Output Valid — 6004 ns
Table continues on the next page...
6.5
Debug specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
52 Freescale Semiconductor, Inc.
Table 41. JTAG pin AC electrical characteristics 1 (continued)
# Symbol Characteristic Min Max Unit
12 tBSDVZ TCK Falling Edge to Output Valid out of HighImpedance
— 600 ns
13 tBSDHZ TCK Falling Edge to Output High Impedance — 600 ns
14 tBSDST Boundary Scan Input Valid to TCK Rising Edge 15 — ns
15 tBSDHT TCK Rising Edge to Boundary Scan Input Invalid 15 — ns
1. These specifications apply to JTAG boundary scan only.2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
Refer to pad specification for allowed transition frequency3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.
TCK
1
2
2
3
3
Figure 25. JTAG test clock input timing
Debug specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 53
TCK
4
5
6
7 8
TMS, TDI
TDO
Figure 26. JTAG test access port timing
Debug specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
54 Freescale Semiconductor, Inc.
TCK
OutputSignals
InputSignals
OutputSignals
11
12
13
14
15
Figure 27. JTAG boundary scan timing
6.5.2 Nexus timingTable 42. Nexus debug port timing 1
No. Symbol Parameter Conditions
Min Max Unit
1 tMCYC MCKO Cycle Time — 15.6 — ns
2 tMDC MCKO Duty Cycle — 40 60 %
3 tMDOV MCKO Low to MDO, MSEO, EVTO Data Valid2 — –0.1 0.25 tMCYC
4 tEVTIPW EVTI Pulse Width — 4 — tTCYC
5 tEVTOPW EVTO Pulse Width — 1 — tMCYC
6 tTCYC TCK Cycle Time3 — 62.5 — ns
7 tTDC TCK Duty Cycle — 40 60 %
8 tNTDIS,tNTMSS
TDI, TMS Data Setup Time — 8 — ns
Table continues on the next page...
Debug specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 55
Table 42. Nexus debug port timing 1 (continued)
No. Symbol Parameter Conditions
Min Max Unit
9 tNTDIH,tNTMSH
TDI, TMS Data Hold Time — 5 — ns
10 tJOV TCK Low to TDO/RDY Data Valid — 0 25 ns
1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measuredfrom 50% of MCKO and 50% of the respective signal.
2. For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.3. The system clock frequency needs to be four times faster than the TCK frequency.
1
2
MCKO
MDOMSEOEVTO
Output Data Valid
3
5
Figure 28. Nexus output timing
EVTI4
Figure 29. Nexus EVTI Input Pulse Width
Debug specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
56 Freescale Semiconductor, Inc.
TDO/RDY
8
9
TMS, TDI
10
TCK
6
7
Figure 30. Nexus TDI, TMS, TDO timing
6.5.3 WKPU/NMI timingTable 43. WKPU/NMI glitch filter
No. Symbol Parameter Min Typ Max Unit
1 WFNMI NMI pulse width that is rejected — — 20 ns
2 WNFNMID NMI pulse width that is passed 400 — — ns
Debug specifications
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 57
6.5.4 External interrupt timing (IRQ pin)Table 44. External interrupt timing specifications
No. Symbol Parameter Conditions Min Max Unit
1 tIPWL IRQ pulse width low — 3 — tCYC
2 tIPWH IRQ pulse width high — 3 — tCYC
3 tICYC IRQ edge to edge time — 6 — tCYC
These values applies when IRQ pins are configured for rising edge or falling edge events,but not both.
IRQ
1
2
3
Figure 31. External interrupt timing
Thermal attributes
7.1 Thermal attributes
Board type Symbol Description 176LQFP Unit Notes
Single-layer (1s) RθJA Thermalresistance, junctionto ambient (naturalconvection)
50.7 °C/W 1, 2
Four-layer (2s2p) RθJA Thermalresistance, junctionto ambient (naturalconvection)
24.2 °C/W 1, 2, 3
Single-layer (1s) RθJMA Thermalresistance, junctionto ambient (200 ft./min. air speed)
38.1 °C/W 1, 3
Four-layer (2s2p) RθJMA Thermalresistance, junction
17.8 °C/W 1, 3
Table continues on the next page...
7
Thermal attributes
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
58 Freescale Semiconductor, Inc.
Board type Symbol Description 176LQFP Unit Notesto ambient (200 ft./min. air speed)
— RθJB Thermalresistance, junctionto board
10.9 °C/W 4
— RθJC Thermalresistance, junctionto case
8.4 °C/W 5
— ΨJT Thermalresistance, junctionto package top
0.5 °C/W 6
— ΨJB Thermalcharacterizationparameter, junctionto package bottom
0.3 °C/W 7
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and boardthermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.3. Per JEDEC JESD51-6 with the board horizontal.4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).6. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any
interface resistance. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.7. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is writtenas Psi-JB.
Board type Symbol Description 324 MAPBGA Unit Notes
Single-layer (1s) RθJA Thermalresistance, junctionto ambient (naturalconvection)
31.0 °C/W 1, 2
Four-layer (2s2p) RθJA Thermalresistance, junctionto ambient (naturalconvection)
24.3 °C/W 1,2,3
Single-layer (1s) RθJMA Thermalresistance, junctionto ambient (200 ft./min. air speed)
23.5 °C/W 1, 3
Four-layer (2s2p) RθJMA Thermalresistance, junctionto ambient (200 ft./min. air speed)
20.1 °C/W 1,3
— RθJB Thermalresistance, junctionto board
16.8 °C/W 4
Table continues on the next page...
Thermal attributes
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 59
Board type Symbol Description 324 MAPBGA Unit Notes
— RθJC Thermalresistance, junctionto case
7.4 °C/W 5
— ΨJT Thermalcharacterizationparameter, junctionto package topnatural convection
0.2 °C/W 6
— ΨJB Thermalcharacterizationparameter, junctionto package bottomnatural convection
7.3 °C/W 7
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and boardthermal resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.3. Per JEDEC JESD51-6 with the board horizontal4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter iswritten as Psi-JB.
Board type Symbol Description 256 MAPBGA Unit Notes
Single-layer (1s) RθJA Thermalresistance, junctionto ambient (naturalconvection)
42.6 °C/W 1, 2
Four-layer (2s2p) RθJA Thermalresistance, junctionto ambient (naturalconvection)
26.0 °C/W 1,2,3
Single-layer (1s) RθJMA Thermalresistance, junctionto ambient (200 ft./min. air speed)
31.0 °C/W 1,3
Four-layer (2s2p) RθJMA Thermalresistance, junctionto ambient (200 ft./min. air speed)
21.3 °C/W 1,3
— RθJB Thermalresistance, junctionto board
12.8 °C/W 4
— RθJC Thermalresistance, junctionto case
7.9 °C/W 5
Table continues on the next page...
Thermal attributes
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
60 Freescale Semiconductor, Inc.
Board type Symbol Description 256 MAPBGA Unit Notes
— ΨJT Thermalcharacterizationparameter, junctionto package topoutside center(naturalconvection)
0.2 °C/W 6
— RθJB_CSB Thermalcharacterizationparameter, junctionto package bottomoutside center(naturalconvection)
9.0 °C/W 7
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and boardthermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.3. Per JEDEC JESD51-6 with the board horizontal4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is writtenas Psi-JT.
7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junctiontemperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter iswritten as Psi-JB.
Board type Symbol Description 100 MAPBGA Unit Notes
Single-layer (1s) RθJA Thermalresistance, junctionto ambient (naturalconvection)
50.9 °C/W 1,2
Four-layer (2s2p) RθJA Thermalresistance, junctionto ambient (naturalconvection)
27.0 °C/W 1,2,3
Single-layer (1s) RθJMA Thermalresistance, junctionto ambient (200 ft./min. air speed)
38.0 °C/W 1,3
Four-layer (2s2p) RθJMA Thermalresistance, junctionto ambient (200 ft./min. air speed)
22.2 °C/W 1,3
— RθJB Thermalresistance, junctionto board
10.8 °C/W 4
Table continues on the next page...
Thermal attributes
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 61
Board type Symbol Description 100 MAPBGA Unit Notes
— RθJC Thermalresistance, junctionto case
8.2 °C/W 5
— ΨJT Thermalcharacterizationparameter, junctionto package topoutside center(naturalconvection)
0.2 °C/W 6
— ΨJB Thermalcharacterizationparameter, junctionto package bottomoutside center(naturalconvection)
7.8 °C/W 7
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and boardthermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.3. Per JEDEC JESD51-6 with the board horizontal4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is writtenas Psi-JT.
7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junctiontemperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter iswritten as Psi-JB.
Dimensions
8.1 Obtaining package dimensions
Package dimensions are provided in package drawing.
To find a package drawing, go to www.freescale.com and perform a keyword search forthe drawing’s document number:
Package Freescale Document Number
100 MAPBGA 98ASA00802D
176-pin LQFP-EP 98ASA00698D
256 MAPBGA 98ASA00346D
324 MAPBGA 98ASA10582D
8
Dimensions
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
62 Freescale Semiconductor, Inc.
Pinouts
9.1 Package pinouts and signal descriptions
For package pinouts and signal descriptions, refer to the Reference Manual.
10 Revision HistoryThe following table provides a revision history for this document.
Table 45. Revision History
Rev. No. Date Substantial Changes
Rev 1 14 March 2013 Initial Release
Rev 2 7 August 2015 • In features:• Updated BAF feature with sentence, Boot Assist Flash (BAF) supports internal
flash programming via a serial link (SCI)• Updated FlexCAN3 with FD support• Updated number of STMs to two.
• In Block diagram:• Updated SRAM size from 128 KB to 256 KB.
• In Family Comparison:• Added note: All optional features (Flash memory, RAM, Peripherals) start with
lowest number or address (e.g. FlexCAN0) and end at highest available numberor address (e.g. MPC574xB/D have 6 CAN, ending with FlexCAN5).
• Revised MPC5746C Family Comparison table.• In Ordering parts:
• Updated ordering parts diagram to include 100 MAPBGA information and optionalfields.
• In table: Absolute maximum ratings• Removed entry: 'VSS_HV'• Added spec for 'VDD12'• Updated 'Max' column for 'VINA'• Updated footnote for VDD_HV_ADC1_REF.• Added footnote to 'Conditions', All voltages are referred to VSS_HV unless
otherwise specified• Removed footnote from 'Max', Absolute maximum voltages are currently
maximum burn-in voltages. Absolute maximum specifications for device stresshave not yet been determined.
• In section: Recommended operating conditions• Added opening text: ''The following table describes the operating conditions ... "• Added note: "VDD_HV_A, VDD_HV_B and VDD_HV_C are all ... "• In table: Recommended operating conditions (VDD_HV_x = 3.3 V) and
(VDD_HV_x = 5 V)• Added footnote to 'Conditions' cloumn, (All voltages are referred to VSS_HV
unless otherwise specified).• Updated footnote for 'Min' column to Device will be functional down (and
electrical specifications as per various datasheet parameters will be
Table continues on the next page...
9
Pinouts
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 63
Table 45. Revision History (continued)
Rev. No. Date Substantial Changes
guaranteed) to the point where one of the LVD/HVD resets the device.When voltage drops outside range for an LVD/HVD, device is reset.
• Removed footnote for 'VDD_HV_A', 'VDD_HV_B', and 'VDD_HV_C' entry andupdated the parameter column.
• Removed entry : 'VSS_HV'• Updated 'Parameter' column for 'VDD_HV_FLA', 'VDD_HV_ADC1_REF', 'VDD_LV'• Updated 'Min' column for 'VDD_HV_ADC0' 'VDD_HV_ADC1'• Updated 'Parameter' 'Min' 'Max' columns for 'VSS_HV_ADC0' and 'VSS_HV_ADC1'• Updated footnote for 'VDD_LV ' to VDD_LV supply pins should never be
grounded (through a small impedance). If these are not driven, they shouldonly be left floating.
• Removed row for symbol 'VSS_LV'• Removed footnote from 'Max' column of 'VDD_HV_ADC0' and 'VDD_HV_ADC1',
(PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming fromVDD_HV_B domain hence VDD_HV_ADC1 should be within ±100 mV ofVDD_HV_B when these channels are used for ADC_1).
• In table: Recommended operating conditions (VDD_HV_x = 3.3 V)• Removed footnote from 'VIN1_CMP_REF', (Only applicable when supplying
from external source).• In table: Recommended operating conditions (VDD_HV_x = 5 V)
• Added spec for 'VIN1_CMP_REF' and corresponding footnotes.
• In section: Voltage monitor electrical characteristics• Updated description for Low Voltage detector block.• Added note, BCP56, MCP68 and MJD31 are guaranteed ballasts.• In table: Voltage regulator electrical specifications
• Added footnote, Ceramic X7R or X5R type with capacitance-temperaturecharacteristics +/-15% of -55 degC to +125degC is recommended. Thetolerance +/-20% is acceptable.
• Revised table, Voltage monitor electrical characteristics
• In section: Supply current characteristics• In table: Current consumption characteristics
• IDD_BODY_4: Updated SYS_CLK to 120 MHz.• IDD_BODY_4: Updated Max for Ta= 105 °C fand 85 °C )• Idd_STOP: Added condition for Ta= 105 °C and removed Max value for Ta= 85
°C.• IDD_HV_ADC_REF: Added condition for Ta= 105 °C and 85 °C and removed
Max value for Ta= 25 °C.• IDD_HV_FLASH: Added condition for Ta= 105 °C and 85 °C
• In table: Low Power Unit (LPU) Current consumption characteristics• LPU_RUN and LPU_STOP: Added condition for Ta= 105 °C and 85 °C
• In table: STANDBY Current consumption characteristics• Added condition for Ta= 105 °C and 85 °C for all entries.
• In section: I/O parameters• In table: Functional Pad AC Specifications @ 3.3 V Range
• Updated values for 'pad_sr_hv (output)'• In table: DC electrical specifications @ 3.3V Range
• Updateded Min and Max values for Vih and Vil respectively.• In table: Functional Pad AC Specifications @ 5 V Range
• Updated values for 'pad_sr_hv (output)'• In table DC electrical specifications @ 5 V Range
• Updated Min value for Vhys
• In section: Reset pad electrical characteristics
Table continues on the next page...
Revision History
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
64 Freescale Semiconductor, Inc.
Table 45. Revision History (continued)
Rev. No. Date Substantial Changes
• Revised table, Reset electrical characteristics• Deleted note, There are some specific ports that supports TTL functionality. These
ports are, PB[4], PB[5], PB[6], PB[7], PB[8], PB[9], PD[0], PD[1], PD[2], PD[3],PD[4], PD[5], PD[6], PD[7], PD[8], PD[9], PD[10], and PD[11].
• In section: PORST electrical specifications• In table: PORST electrical specifications
• Updated 'Min' value for WNFPORST
• In section: Peripheral operating requirements and behaviours• Changed section title from Input impedance and ADC accuracy to Input equivalent
circuit and ADC conversion characteristics.• Revised table: ADC conversion characteristics (for 12-bit) and ADC conversion
characteristics (for 10-bit)• Removed table, ADC supply configurations.
• In section: Analogue Comparator (CMP) electrical specifications• In table: Comparator and 6-bit DAC electrical specifications
• Updated 'Max' value of IDDLS• Updated 'Min' and 'Max' for VAIO and DNL• Updated 'Descripton' 'Min' 'Max' od VH• Updated row for tDHS• Added row for tDLS• Removed row for VCMPOh and VCMPOl
• In section: Clocks and PLL interfaces modules• In table: Main oscillator electrical characteristics
• VXOSCHS: Removed values for 4 MHz.• TXOSCHSSU: Updated range to 8-40 MHz.
• In table: 16 MHz RC Oscillator electrical specifications• Updated 'Max' for Tstartup and TLTJIT• Removed FUntrimmed row
• In table: 128 KHz Internal RC oscillator electrical specifications• Fosc: Removed Uncaliberated 'Condition' and updated 'Min', 'Typ', and
'Max' for Caliberated condition• Fosc: Updated 'Temperature dependence' and 'Supply dependence' Max
values• In table: PLL electrical specifications
• Removed entries for Input Clock Low Level, Input Clock High Level, Powerconsumption, Regulator Maximum Output Current, Analog Supply, DigitalSupply (VDD_LV), Modulation Depth (Down Spread), PLL reset assertiontime, and Power Consumption
• Removed 'Typ' value for Duty Cycle at pllclkout• Removed 'Min' value for Lock Time in calibration mode.
• In table: Jitter calculation• Added 1 Sigma Random Jitter and Total Period Jitter values for Long Term
Jitter (Interger and Fractional Mode) rows.
• In section Flash read wait state and address pipeline control settings• In Flash Read Wait State and Address Pipeline Control: Updated APC for 40 MHz.
• Removed section: On-chip peripherals
• In section, Thermal attributes• Added table for 100 MAPBGA
• In section Obtaining package dimensions• Updated package details for 100 MAPBGA
Table continues on the next page...
Revision History
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 65
Table 45. Revision History (continued)
Rev. No. Date Substantial Changes
• Editoral updates throughtout including correction of various module names.
Rev 3 2 March 2016 • In section, Recommended operating conditions• Added a new Note
• In section, Voltage regulator electrical characteristics• In table, Voltage regulator electrical specifications:
• Added a new row for CHV_VDD_B• Added a footnote on VDD_HV_BALLAST
• Added a new Note at the end of this section
• In section, Voltage monitor electrical characteristics• In table, Voltage monitor electrical characteristics:
• Removed "VLVD_FLASH" and "VLVD_FLASH during low power mode usingLPBG as reference" rows
• Updated Fall and Rise trimmed Minimum values for VHVD_LV_cold
• In section, Supply current characteristics• In table, Current consumption characteristics:
• Updated the footnote mentioned in the Condition column of IDD_STOP row• Updated all TBD values
• In table, Low Power Unit (LPU) Current consumption characteristics:• Updated the typical value of LPU_STOP to 0.18 mA• Updated all TBD values
• In table, STANDBY Current consumption characteristics:• Updated all TBD values
• In section, AC specifications @ 3.3 V Range• In table, Functional Pad AC Specifications @ 3.3 V Range:
• Updated Rise/Fall Edge values
• In section, DC electrical specifications @ 3.3V Range• In table, DC electrical specifications @ 3.3V Range:
• Updated Max value for Vol to 0.1 * VDD_HV_x
• In section, AC specifications @ 5 V Range• In table, Functional Pad AC Specifications @ 5 V Range:
• Updated Rise/Fall Edge values
• In section, DC electrical specifications @ 5 V Range• In table, DC electrical specifications @ 5 V Range:
• Updated Min and Max values for Pull_Ioh and Pull_Iol rows• Updated Max value for Vol to 0.1 * VDD_HV_x
• In section, Reset pad electrical characteristics• In table, Functional reset pad electrical specifications:
• Updated parameter column for VIH, VIL and VHYS rows• Updated Min and Max values for VIH and VIL rows
• In section, PORST electrical specifications• In table, PORST electrical specifications:
• Updated Unit and Min/Max values for VIH and VIL rows
• In section, Input equivalent circuit and ADC conversion characteristics• In table, ADC conversion characteristics (for 12-bit):
• Updated "ADC Analog Pad (pad going to one ADC)" row• In table, ADC conversion characteristics (for 10-bit):
Table continues on the next page...
Revision History
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
66 Freescale Semiconductor, Inc.
Table 45. Revision History (continued)
Rev. No. Date Substantial Changes
• Updated "ADC Analog Pad (pad going to one ADC)" row
• In section, Analog Comparator (CMP) electrical specifications• In table, Comparator and 6-bit DAC electrical specifications:
• Updated Min and Max values for VAIO to ±47 mV• Updated Max value for tDLS to 21 μs
• In section, Main oscillator electrical characteristics• In table, Main oscillator electrical characteristics:
• Updated VIH Min value to 1.95V• Updated VIL Max value to 1.25V• Removed VIH Typ value
• In section, PLL electrical specifications• In table, PLL electrical specifications:
• Updated Max value for Modulation Depth (Center Spread) to +/- 3.0%
Rev 4 9 March 2016 • In section, Voltage regulator electrical characteristics• In table, Voltage regulator electrical specifications:
• Updated the footnote on VDD_HV_BALLAST
Revision History
MPC5746C Microcontroller Datasheet, Rev. 4, 3/2016
Freescale Semiconductor, Inc. 67
How to Reach Us:
Home Page:freescale.com
Web Support:freescale.com/support
Information in this document is provided solely to enable system andsoftware implementers to use Freescale products. There are no expressor implied copyright licenses granted hereunder to design or fabricateany integrated circuits based on the information in this document.Freescale reserves the right to make changes without further notice toany products herein.
Freescale makes no warranty, representation, or guarantee regardingthe suitability of its products for any particular purpose, nor doesFreescale assume any liability arising out of the application or use ofany product or circuit, and specifically disclaims any and all liability,including without limitation consequential or incidental damages.“Typical” parameters that may be provided in Freescale data sheetsand/or specifications can and do vary in different applications, andactual performance may vary over time. All operating parameters,including “typicals,” must be validated for each customer application bycustomer's technical experts. Freescale does not convey any licenseunder its patent rights nor the rights of others. Freescale sells productspursuant to standard terms and conditions of sale, which can be foundat the following address: www.freescale.com/salestermsandconditions.
Freescale and the Freescale logo are trademarks of FreescaleSemiconductor, Inc., Reg. U.S. Pat. & Tm. Off. The Power Architectureand Power.org word marks and the Power and Power.org logos andrelated marks are trademarks and service marks licensed by Power.org.All other product or service names are the property of their respectiveowners.
© 2016 Freescale Semiconductor, Inc.
Document Number MPC5746CRevision 4, 3/2016