mproz – a 16 bit minimal processor · [email protected] 9.3.99 mproz – a 16 bit...
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[email protected] 9.3.99
MPROZ – A 16 bit minimal processor
MPROZ is a simplified version of the 16 bit processor XPROZ.
The schematics (WORKVIEW format) and the assembler (QBasic) can be found inmproz.zip
1. Processor architectur
1.1 InterfaceADR[14:0] : 15 bit address busDAT[15:0] : 16 bit data busRAMSEL~ : RAM accessROMSEL~ : ROM accessIOSEL~ : I/O accessR/W~ : read / writeOE~ : output enableCLK : clockIRQ~ : interrupt request
1.2 RegisterTo minimize the hardware, there is only a 15 bit program counter (PC) and a 1 bit flag (F). Noother user accessible registers exist. After a reset PC and F are initialized to 0.
dout[15:0]
adr[14:0]
din[15:0]
memsel~r/w~
clkirq~
MPROZ Interface
DAT[15:0]
ADR[14:0]
RAMSEL~ROMSEL~IOSEL~R/W~OE~
CLKIRQ~
RAMROMI/O
1.3 InstructionsMPROZ supports three instructions:
br adrLoad adr into PC if F=0Clear F
add adr1,adr2Add the contents of memory location adr1 and the contents ofmemory location adr2 and store the result in memory location adr2.Store the carry of the addition in F.
nor adr1,adr2Calculate the NOR function of the contents of memory location adr1and the contents of memory location adr2 and store the result inmemory location adr2. F=1 if result =0 , else F=0.
1.4 InterruptBecause there is no instruction to set or reset the interrupt enable flag (ie), this is done by accessingmemory location $4000. A read from $4000 enables interrupts (ie=1) and a write to $4000 disablesinterrupts (ie=0). An external interrupt request (IRQ~) must be asserted until the interrupt isserviced by MPROZ. The interrupt is serviced by MPROZ, when the interrupt enable flag is set anda branch instruction with F=0 is executed. Thereby it is not necessary to save the program counter(PC) and the flag (F), but it is sufficient to save the interrupted branch instruction. This instructionis saved at the memory location which address is stored in memory location 1 (this normally shouldbe address $4000, because then the ie flag is automatically cleared, when the instruction is saved).The execution of the interrupt program starts at address 2. The return from interrupt is done by abranch to $4000, which also automatically sets the ie flag.
1 adr
0 adr 10 adr 2
0 adr 11 adr 2
2. Implementation
2.1 MPROZ
OP: 1 bit registerF: 1 bit registerPC: 15 bit registerXREG: 16 bit registerYREG: 16 bit registerAMUX: IF (s4=0) THEN out=in1 ELSE out=in2XGATE: IF (s5=0) THEN out=$0000 ELSE out=inYGATE: IF (s6=0) THEN out=$0001 ELSE out=inALU: IF (s7=0) THEN out=in1 ADD in2 , F=carry
ELSE out=in1 NOR in2 , F=zeroSTEU: generates control signals s0-s8, memsel~ und r/w~
state action
q0 PC→adr, PC+1→PC, din→XREG,YREG
q1 YREG→adr, din→XREG
q2 PC→adr, din→ YREG, din15→OP
q3 YREG→adr, din→YREG
q4 XREG [ADD|NOR] YREG → DOUT, [Carry|Zero] → F, DIN→XREG
q5 PC→adr, PC+1→PC, din→ YREG
q6 YREG→adr, XREG+0→dout
q7 [XREG | 1]+0→PC falls F=0, 0→F
XREG EOP Eclks0
clks1 YREG E
clks2 PC E
clks3
XGATE E s5 YGATE E s6
ALU
AMUX
S7
S4
s0s1s2s3s4s5s6s7s8
memsel~r/w~clkirq~
F Eclks8
din[15:0]
dout[15:0]
adr[14:0]
din15
STEU
int = irq~ + ie + F
Zustand s8 s7 s6 s5 s4 s3 s2 s1 s0 memsel r/w~q0 0 0 1 0 1 1 1 1 - 0 1q1 - - - - 0 0 - 1 - 0 1q2 - - - - 1 0 1 0 1 0 1q2* - 0 1 0 1 1 1 0 1 0 1q3 - - - - 0 0 1 0 0 0 1q4 1 OP 1 1 0 0 - 1 - 1 0q5 0 0 1 0 1 1 1 0 - 0 1q6 0 0 0 1 0 0 - - - 0 0q7 1 0 0 int - F - 0 - 1 1
q2*: for 3 address instructions instead of 2 address instructions
s0 = q2
s1 = q0 + q1 + q4
s2 = 1
s3 = q0 + q5 +q7 ⋅ F
s4 = q0 + q2 + q5
s5 = q4 + q6 + q7 ⋅ int
s6 = q6 + q7
s7 = q4 ⋅ OP
s8 = q4 + q7
memsel~ = q4 + q7
r/w~ = q4 + q6
d0 = q6 + q7 ⋅ int
d1 = q0 ⋅ D15
d2 = q1
d3 = q2
d4 = q3
d5 = q4 + q7 ⋅ int
d6 = q5
d7 = q0 ⋅ D15
0 4321
7
5 6D15
D15 int
int
2.2 Interface
The interface generates the output signals (RAMSEL~, ROMSEL~, IOSEL~, R/W~and OE~).
address$0000 - $3fff ROMSEL~ 64 kByte$4000 - $7dff RAMSEL~ 63 kByte$7e00 - $7fff IOSEL~ 1 kByte
For exact timing, the external clock signal is divided by 8.
CLK
t0=clk
t1
t2
reset
2.3 Schematics
2.3.1 MPROZ
STEU
ADR[14:0]
STEU
S8S7S6S5S4S3S2S1S0
RW
OP MEM
IRQ
F
D15
CLK
ADR[14:0]
ADR[15:0]
FIN
FOUT
FLAG
CLK
E
IRQ
ALU
Y[15:0]
S
1:norALU
X[15:0]
Z[15:0]F
0:add
E
D
Q
CLK
OPS3
CLK
B2[15:0] B3[15:0]
B5[14:0]
YREG
CLK
Q[15:0]
D[15:0]
YREG
E
B4[15:0]
A[15:0] B[14:0]
C[15:0]
SAMUX
S8
S1XREG
Q[15:0]
D[15:0]
XREG
E
CLK
A[15:0]
C[15:0]
GXGATE
B1[15:0]
CLK
CLK
S2
S5
S7
S4
CLK
S0
YGATEYGATE
A[15:0]
C[15:0]
G S6
CLK
S0S1S2S3S4S5S6S7S8
RW
MEM
DIN15
DIN[15:0]
DOUT[15:0]
DOUT[14:0]
PC
Q[14:0]
D[14:0]CLK
E
CLK
DI[15:0]
ADR[14:0]
DO[15:0]
MPROZ
CLK
MPROZ
DOUT[15:0]
DIN[15:0]
ADR[14:0]
IRQ
RW
MEM
INTER
MEM
RW
IRQ
CLK
ADR[14:0]
DOUT[15:0]
IRQ-
DIN[15:0]
INTER
TAKT
ROMSEL-RAMSEL-
IOSEL-
D9D8D7D6D5D4D3D2
D15D14D13D12D11D10
D1D0
A9A8A7A6A5A4A3A2
A14A13A12A11A10
A1A0
OE-RW-
PART=3195PC84-5
IRQ-RW-OE-
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0
ROMSEL-IOSEL-
TAKT
RAMSEL-
2.3.1.1 XREG
2.3.1.2 XGATE
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D[15:0]
E
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q[15:0]
OR2B1
A0
A1
A2
A3
A5
A6
A7
A8
A9
A10
A11
A12
A13
A15
A14
A4
A[15:0]
C0
C1
C2
C3
C5
C6
C7
C8
C9
C10
C11
C12
C13
C15
C14
C4
C[15:0]
G
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
2.3.1.3 YREG
2.3.1.4 YGATE
Q[15:0]
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CLK
E
D[15:0]
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
A0
A1
A2
A3
A5
A6
A7
A8
A9
A10
A11
A12
A13
A15
A14
A4
A[15:0]
C0
C1
C2
C3
C5
C6
C7
C8
C9
C10
C11
C12
C13
C15
C14
C4
C[15:0]
G
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
AND2
2.3.1.5 PC
2.3.1.6 AMUX
CLK
E
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q[14:0]
D[14:0]
D0
D1
D2
D3
D4
D5
D6
D7
D9
D10
D11
D12
D13
D14
D8
C15
C[15:0]
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
A15
A[15:0]
A0
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
B
B0
B[14:0]
B14
B13
B12
B11
B10
B9
B8
B6
B5
B3
B2
B1
B7
B4
S
S SB
2.3.1.7 STEU
OR3
AND2
INT
FIRQ
ADR1
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
ADR[14:0]
ADR14
ADR13
ADR12
ADR11
ADR10
ADR0
MEM
CLK
RW
CCE
DQ
RD
DFF
AND3B1
OR4
NOR3
OR5
OR5
INT
Q7
CCE
DQ
RD
DFF
Q4
Q6
CCE
DQ
RD
DFF
CCE
DQ
RD
DFF
CCE
DQ
RD
DFF
Q7
OR3
S5Q4
Q6
AND2
Q6
Q4
OP
Q4
Q6
AND2B1
OR2
OR3
S0
S1
S2
S3
S4
S6
S7
S8
MEM
RW
Q7
Q4
Q7
NOR2
Q5
Q2
Q0
Q7
Q5
Q0
AND2B1
OR3
B
Q4
Q1
Q0
Q2
Q3
Q2
Q1
CCE
DQ
RD
DFF
C
CE
DQ
RD
DFF
CCE
DQ
RD
DFF
CCE
DQ
RD
DFF
B
B
VDD
NOR2
F
NOR2
AND2
Q6
Q7
INT
Q5
Q7
INT
INV
Q0
D15
Q0
AND2
D15
AND2B1
OR2
CLK
IE
OR3B1
2.3.1.8 ALU
D0
D1
OSE
GMUX
F
OR5
OR5
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
Z
S
CI
XY
AddNor
CO
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
X[15:0]
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y[15:0]
GND
OR5
NOR4
Z[15:0]
Z15
Z14
Z13
Z12
Z10
Z9
Z8
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
Z15
Z14
Z13
Z12
Z11
Z10
Z9
Z8
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
Z11
B BBS S S
S
S
2.3.1.9 ADDNOR
2.3.1.10 OP
2.3.1.11 FLAG
CI
OR3
AND2
AND2
AND2
OR5
AND4B1
AND4B3
AND4B3
AND3B2
AND3B2
S
X
Y
X
Y
Y
X
CI
S
X
Y
CI
S
CI
X
Y
CI
S
Z
X
Y
X
Y
CI
CO
C
CE
D Q
RD
DFF
D
E
CLK
Q
FOUT
CLK
E
FIN
C
CE
D Q
RD
DFF
2.3.2 Interface
2.3.2.1 TAKT
LOC=P66
BPAD
GND
OBUFZ
OBUFZ
OBUFZ
OBUFZ
OBUFZ
OBUFZ
OBUFZ
OBUFZ
OBUFZ
OBUFZ
OBUFZ
OBUFZ
DOUT[15:0]
DOUT10
DOUT9
DOUT1
DOUT13
DOUT3
DOUT2
DOUT0
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT11
DOUT12
DOUT15
DOUT14
DIN1
DIN9
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
DIN2
DIN0
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN[15:0]
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
OBUF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
LOC=P79
BPAD
LOC=P17
BPAD
LOC=P8
BPAD
LOC=P68
BPAD
LOC=P67
BPAD
LOC=P58
BPAD
LOC=P59
BPAD
LOC=P40
BPAD
LOC=P39
BPAD
LOC=P37
BPAD
LOC=P36
BPAD
LOC=P20
BPAD
LOC=P23
BPAD
LOC=P24
BPAD
LOC=P25
BPAD
MEM
LOC=P81
OPADRAMSEL-
OR3
ROMSEL-
OR2B1
IOSEL-
OR4B2
OR2
LOC=P4
OPAD
LOC=P6
OPADOE-
RW-
LOC=P83
OPAD
LOC=P84
OPAD
IRQ
CLK
IBUF
LOC=P3
OPAD
LOC=P82
OPAD
LOC=P77
OPAD
LOC=P80
OPAD
LOC=P69
OPAD
LOC=P60
OPAD
LOC=P61
OPAD
LOC=P44
OPAD
LOC=P45
OPAD
LOC=P38
OPAD
LOC=P35
OPAD
LOC=P34
OPAD
LOC=P5
OPAD
LOC=P27
OPAD
LOC=P26
OPAD
TAKTE
LOC=P57
IPADTAKT
LOC=P41
IPAD
ACLK
PULLUP
IRQ-
C
CE
DQ
RD
DFF
C
CE
DQ
RD
DFF
AND5
OR4B1
OR2
RW
OBUF
IBUF
IBUF
IBUF
IBUF
OBUFZ
OBUFZ
OBUFZ
OBUFZ
ADR[14:0]ADR0
ADR1
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
ADR10
ADR11
ADR12
ADR13
ADR10
ADR11
ADR12
ADR13
ADR14
ADR14
ADR14
ADR9
CLK
T2T1T0
TAKT
CLK
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
T0
GCLK
VDD
INV C
CE
D Q
RD
DFF
INV
INV
AND2
T2 T1
AND2
C
CE
D Q
RD
DFF
3. Assembler
The assembler supports beyond the three MPROZ instructions (add, nor, br) also the macroinstructions move and bsr (branch subroutine) and indirect addressing. For better readability thesynonyms bcc and bne can be used instead of br :
add r0,r1add #20,r0add (r0),r1add r0,(r1)add (r0),(r1)bcc lab1 ; branch to lab1 if F=carry=0br lab1 ; branch to lab1 (now F is always zero)
lab2: nor r0,r1nor #20,r0nor (r0),r1nor r0,(r1)nor (r0),(r1)bne lab1 ; branch to lab1 if F=zero=0br lab1 ; branch to lab1 (now F is always zero)
lab3: move r0,r1move #20,r0move (r0),r1move r0,(r1)move (r0),(r1)br lab1 ; branch to lab1 (F =0 after a move).
lab1: bsr sub..
sub: dcw 0 ; memory location to save a jump to the return address...br sub ; return from subroutine
r0: dc.w 0r1: dc.w 0#20: dc.w 20#$ffff: dc.w #$ffff#$7fff: dc.w #$7fff
Because this macros are realized with selfmodifying Code, they can be used only in programsstored in RAM but not in ROM. If these macros are used, the following to lines must be insertedinto the program:
#$ffff: dc.w #$ffff#$7fff: dc.w #$7fff
4. Extentions
4.1 In- / Output
In order to do simple IO without external hardware, an 8 bit input and an 8 bit output port wasincluded in MPROZ. This port is addressed by $7fff . Bit 7-0 belongs to the output and bit 15-8 tothe input lines.
dout[15:0]
adr[14:0]
din[15:0]
memsel~r/w~
clkirq~
MPROZ Interface
DAT[15:0]
ADR[14:0]
RAMSEL~ROMSEL~IOSEL~R/W~OE~
CLKIRQ~
RAMROMI/O
I/O-Port
8 x in
8 x out
4.1.1 Schematics
4.1.1 IO
DIN[15:0]
ADR[14:0]
IO
IOCLK
MEM
RW
ADR[14:0]
DINB[15:0]
DINA[15:0]
DOUT[15:0]
MPROZ
CLK
MPROZ
DOUT[15:0]
DIN[15:0]
ADR[14:0]
IRQ
RW
MEM
INTER
MEM
RW
IRQ
CLK
ADR[14:0]
DOUT[15:0]
IRQ-
DIN[15:0]
INTER
TAKT
ROMSEL-RAMSEL-
IOSEL-
D9D8D7D6D5D4D3D2
D15D14D13D12D11D10
D1D0
A9A8A7A6A5A4A3A2
A14A13A12A11A10
A1A0
OE-RW-
DI[15:0]
DO[15:0]
PART=3195PC84-5
IRQ-RW-OE-
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0
ROMSEL-IOSEL-
TAKT
RAMSEL-
SS B
OBUF
OBUF
OBUF
DINA7
DINA15
DINA[15:0]
DINA6
DINA5
DINA4
DINA3
DINA2
DINA1
DINA0
DINA8
DINA9
DINA10
DINA11
DINA12
DINA13
DINA14
DINB15
DINB7
DINB2
DINB14
DINB13
DINB12
DINB11
DINB10
DINB9
DINB8
DINB[15:0]
DINB0
DINB1
DINB3
DINB4
DINB5
DINB6
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
DOUT[15:0]
AND2B1
OUT1
OUT0
IN7
AND4B1
AND5
AND5
AND5
IN0
IN1
IN2
IN3
IN4
IN5
IN6
PULLUP
LOC=P49
IPAD
IBUF
IBUFLOC=P48
IPAD
PULLUP
IBUFLOC=P47
IPAD
PULLUP
IBUFLOC=P46
IPAD
PULLUP
PULLUP
LOC=P50
IPAD
IBUF
PULLUP
LOC=P51
IPAD
IBUF
PULLUP
LOC=P52
IPAD
IBUF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
C
CE
D Q
RD
DFF
LOC=P53
IPAD
IBUF
CLK
ADR0
ADR1
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
ADR10
ADR11
ADR12
ADR13
ADR14
ADR[14:0]
PULLUP
RW
OUT7LOC=P78
OPAD
OUT6LOC=P75
OPAD
OUT5LOC=P76
OPAD
OUT4LOC=P71
OPAD
OUT3LOC=P70
OPAD
OUT2LOC=P63
OPAD
LOC=P62
OPAD
LOC=P56
OPAD
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
D0
D1
OSE
GMUX
MEM
OBUF
OBUF
OBUF
OBUF
OBUF
4.2 Microprogramming
4.2.1 Hardware
To show the principles of microprogramming, the control unit of MPROZ is also design in amicroprogrammed version :
The three bits x,y,z determine, whether microword A or B is stored into the micro instructionregister:
x y z0 – 0 A0 – 1 B1 0 0 A if F=0 B if F=11 0 1 A if OP=0 B if OP=11 1 0 A if D15=0 B if D15=11 1 1 A if INT=0 B if INT=1
s8 s7 s6 s5 s4 s3 s2 s1 s0 me
mse
l~r/
w~
x y z a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
FOPdin15int
µRAM A(1k x 24)
µRAM B(1k x 24)
MUX
µ-Befehlsregister
4.2.1 Software
The microprogram for control unit of MPROZ:
microword A microword B
Adresse
s8
s7
s6
s5
s4
s3
s2
s1
s0
memsel~
r/w~xyz
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
s8
s7
s6
s5
s4
s3
s2
s1
s0
memsel~
r/w~xyz
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A B0 0010 1111 0011 1000 0000 0001 0010 1111 0011 1000 0000 0010 2f3801 2f38021 0000 0001 0010 0000 0000 0011 1001 0100 0111 1100 0000 0110 012003 947c062 0000 0001 0010 0000 0000 0011 1001 0000 0110 0000 0000 0000 012003 9060003 0000 1010 1010 0100 0000 0011 0000 0010 0011 0100 0000 0100 0aa403 0234044 1011 0001 0100 0000 0000 0101 1111 0001 0100 0000 0000 0101 b14005 f140055 0010 1110 0010 0100 0000 0101 0001 0000 0001 0000 0000 0000 2e2405 1010006 1000 0100 0110 0000 0000 0101 0010 1111 0011 1000 0000 0001 846005 2f3801
4.2.3 Schematics
4.2.3.1 UFF
AD4
AD5
AD6
AD9
AD8
AD2
AD1
AD0
AD3
AD[9:0]
AD7
URAM_A
uRAM (1k X 24)
D[23:0]
A[9:0]
URAM_B
uRAM (1k X 24)
D[23:0]
A[9:0]
AND2B1
AND4B2
AND4B1
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S
Q
BA
CUFF
S7
S6
S5
S4
S3
S2
S1
S0
MEM
RW
AND4
OR5
INT
D15
OP
F
AND4B1
S
Q
BA
CUFF
A[23:0]
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
B[23:0]
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
S8
CLK
OR3B1
OR5
OR5
NOR3
OR4
AND3B1
CCE
DQ
RD
DFF
IE
RW
CLK
MEM
ADR1
ADR0
ADR10
ADR11
ADR12
ADR13
ADR14
ADR[14:0]
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
IRQ
F
INT
S
Q
BA
CUFF
C
D0
D1
OSE
GMUX
C
CE
D Q
RD
DFFB
S
A
Q
5. Test hardware
To demonstrate that MPROZ works properly, a simple traffic-light was realized.
Program for the traffic-light:
;******;****** ampel_5.ass vom 10.März 1999 ******;****** mit Fußgängerampel (Interrupt) ******; pc=$0 br auto_amp dcw $4000 ; Adresse zum retten des PC bei einem Interrupt;;****** Interruptroutine ab Adresse 0002 !!! ******;; br irq ; Adresse der Interruptroutineirq: move io,r0 ; nor #ff3f,r0 ; Abfrage, ob FUSS AUS bne set_fuss ; FUSS AUS ---> FUSS auf rot move io,r0 add #00c0,r0 ; FUSS auf ROT move r0,ioset_fuss: br $4000 ; Rücksprung aus Interrupt br $4000 ; Rücksprung aus Interrupt;;********** Variablen **********;#$7fff: dcw $7fff#$ffff: dcw $ffff#$0001: dcw $0001#0000 : dcw $0000#0001 : dcw $0001;;********** Die Zeitschleife "zeit" für 22 Sekunden hat im äußeren;********** Schleifenregister den Wert $96 und im inneren den Wert;********** $ffff bei einem 32MHz-Quarz (Teiler 8=250µsec);#02s : dcw $0001 ; Zeitwert für 0,2 Sekunden#05s : dcw $0003 ; Zeitwert für 0,5 Sekunden#1s : dcw $0007 ; Zeitwert für 1 Sekunden#2s : dcw $000d ; Zeitwert für 2 Sekunden#4s : dcw $001b ; Zeitwert für 4 Sekunden#6s : dcw $0029 ; Zeitwert für 6 Sekunden#8s : dcw $0036 ; Zeitwert für 8 Sekunden#22s : dcw $0096 ; Zeitwert für 22 Sekunden;#0076: dcw $0076#00c0: dcw $00c0#00db: dcw $00db#00eb: dcw $00eb#00f1: dcw $00f1#00f5: dcw $00f5#00f6: dcw $00f6#00e3: dcw $00e3#005b :dcw $005b#ff00 :dcw $ff00#ff3f :dcw $ff3f#ffbf: dcw $ffbf#feff: dcw $feff#ff7f: dcw $ff7f#ffff: dcw $ffff;;;********** Programmstart und Initialisierung **********;auto_amp: move #ff00,io ; Alle LEDs AN move #1s,r3 move auto_ini1,zeit_ret
br zeitauto_ini1: dcw $8000+auto_ini2auto_ini2: move #ffff,io ; Alle LEDs AUS move #1s,r3 move auto_ini3,zeit_ret br zeitauto_ini3: dcw $8000+auto_ini3a
auto_ini3a: move #1s,r6 nor #0000,r6auto_ini4: move #0001,r2 ; LED's nacheinander ANauto_ini5: move r2,r4 nor #0000,r4 move r4,io ; Ausgabe move #02s,r3 move auto_ini6,zeit_ret br zeitauto_ini6: dcw $8000+auto_ini7auto_ini7: move r2,r5 add r5,r2 move r2,r5 nor #feff,r5 bne auto_ini5 add #0001,r6 bcc auto_ini4auto_ini8: move #ffff,io ; Alle LEDs AUS move #2s,r3 move auto_ini9,zeit_ret br zeitauto_ini9: dcw $8000+auto_ini10
auto_ini10: add $4000,tmp ; Lesezugriff: Interrupt enable;;********** Ampelsteuerung **********;auto_1: ;aampel_1: rt - 6 sec / aampel_2: gn - 6 sec; Wert:$xxdb
move io,r4 ; nor #ff3f,r4 ; FUSS maskieren move #00db,r5 nor #0000,r5 nor r5,r4 move r4,io
move #6s,r3 move a1_s,zeit_ret br zeita1_s: dcw $8000+auto_2
auto_2: ;aampel_1: rt - 2 sec / aampel_2: ge - 2 sec; Wert:$xxeb
move io,r4 ; nor #ff3f,r4 ; FUSS maskieren move #00eb,r5 nor #0000,r5 nor r5,r4 move r4,io
move #2s,r3 move a2_s,zeit_ret br zeita2_s: dcw $8000+auto_3
auto_3: ;aampel_1: rt/ge - 2 sec / aampel_2: rt - 2 sec; Wert:$xxf1
move io,r4 ;
nor #ff3f,r4 ; FUSS maskieren move #00f1,r5 nor #0000,r5 nor r5,r4 move r4,io move #2s,r3 move a3_s,zeit_ret br zeita3_s: dcw $8000+auto_4
auto_4: ;aampel_1: gn - 6 sec / aampel_2: rt - 6 sec; Wert:$xxf6
move io,r4 ; nor #ffbf,r4 ; Abfrage, ob FUSS rot bne a4_1 ; FUSS ROT? move #00f6,io ; Normalbetrieb br a4_2a4_1: move #0076,io ; FUSS auf grün setzen!a4_2: move #6s,r3 move a4_s,zeit_ret br zeita4_s: dcw $8000+auto_5
move #6s,r3 move a4_s,zeit_ret br zeita4_s: dcw $8000+auto_5
auto_5: ;aampel_1: ge - 2 sec / aampel_2: rt - 2 sec; Wert:$xxf5
move io,r4 nor #ff7f,r4 ; FUSS grün? bne a5_1 move io,r4 ; FUSS nicht grün nor #ff3f,r4 move #00f5,r5 nor #0000,r5 nor r5,r4 move r4,io br a5_2a5_1: move #00f5,io ; FUSS AUSa5_2: move #2s,r3 move a5_s,zeit_ret br zeita5_s: dcw $8000+auto_6
auto_6: ;aampel_1: rt - 2 sec / aampel_2: rt/ge - 2 sec; Wert:$xxe3
move io,r4 ; nor #ff3f,r4 ; FUSS maskieren move #00e3,r5 nor #0000,r5 nor r5,r4 move r4,io move #2s,r3 move a6_s,zeit_ret br zeita6_s: dcw $8000+auto_1
;************ Zeitschleife *************;************ Zählerwert in r3 ************
zeit: nor #$ffff,r1 nor #0000,r3 add #$0001,r3w1i: add #$0001,r1 bcc w1i
add #$0001,r3 bcc w1i br zeit_ret
;************ Umschalten auf RAM ************; pc=$4000 dcw 0 ; Speicherzelle zum retten des PC bei einem Interrupt
r0: dcw 0r1: dcw 0r2: dcw 0r3: dcw 0r4: dcw 0r5: dcw 0r6: dcw 0doio_ret:dcw 0zeit_ret:dcw 0tmp: dcw 0io=$7fff
;****** Die Fußgängerampel schaltet mit aampel_2 (Querrichtung);;auto_1=01xx: ;aampel_1: rt - 6 sec / aampel_2: gn - 6 sec; Wert:$xxdb;auto_2=02xx: ;aampel_1: rt - 2 sec / aampel_2: ge - 2 sec; Wert:$xxeb;auto_3=03xx: ;aampel_1: rt/ge - 2 sec / aampel_2: rt - 2 sec; Wert:$xxf1;auto_4=04xx: ;aampel_1: gn - 6 sec / aampel_2: rt - 6 sec; Wert:$xxf6;auto_5=05xx: ;aampel_1: ge - 2 sec / aampel_2: rt - 2 sec; Wert:$xxf5;auto_6=06xx: ;aampel_1: rt - 2 sec / aampel_2: rt/ge - 2 sec; Wert:$xxe3;fuss_1=07xx: ;fussampel: rot - Beginn in auto_3 bis auto_6;fuss_2=08xx: ;fussampel: grün - 8 sec in Phase auto_1 und auto_2
end:_