mr-mod · mr-mod ethernet media renderer module 8/38 engineered sa - switzerland doc. v.117e/rev....

MR-MODETHERNETMEDIARENDERERMODULE

DATASHEET

Allrightsreserved.NopartofthisworkcoveredbytheengineeredSAcopyrightmaybereproducedorcopiedinanyform or by anymeans (graphic, electronic ormechanical, including photocopying, recording, taping or informationretrievalsystems)withoutthewrittenpermissionofengineeredSA.Copyright©engineeredSAAvenuedesSports28,1400Yverdon-les-BainsSwitzerland+41215433966 [email protected]/www.engineered.ch doc.v.117e/rev.Nov-16

MR-MODETHERNETMEDIARENDERERMODULE 2/38

engineeredSA-Switzerland doc.v.117e/rev.Nov-16

TableofcontentsTableofcontents...........................................................................................................................................................................................3Preface...............................................................................................................................................................................................................6I. AboutThisDatasheet.................................................................................................................................................................6II. CompanyInformation................................................................................................................................................................6III. Notice................................................................................................................................................................................................6IV. ProductWarningsandRestrictions.....................................................................................................................................6V. RepairandMaintenance...........................................................................................................................................................7VI. DocumentationReleaseNotice..............................................................................................................................................7

1 Introduction............................................................................................................................................................................................81.1 Highlights........................................................................................................................................................................................81.2 FirmwareVersion........................................................................................................................................................................81.3 FunctionalBlockDiagram........................................................................................................................................................9

2 CharacteristicsandSpecifications..............................................................................................................................................102.1 ElectrostaticDischargeWarning.......................................................................................................................................102.2 RecommendedOperatingConditions..............................................................................................................................102.3 AbsoluteMaximumRatings.................................................................................................................................................102.4 ElectricalSpecifications.........................................................................................................................................................102.5 DigitalAudioSpecifications.................................................................................................................................................112.6 AudioFormats............................................................................................................................................................................112.7 PinConfiguration......................................................................................................................................................................122.8 PinDescriptions........................................................................................................................................................................13

3 ApplicationInformation.................................................................................................................................................................143.1 HomeNetworkDevices..........................................................................................................................................................143.1.1 DigitalMediaServer(DMS).........................................................................................................................................143.1.2 DigitalMediaRenderer(DMR)..................................................................................................................................143.1.3 DigitalControlPoint(DCP).........................................................................................................................................14

3.2 TypicalSetup..............................................................................................................................................................................143.3 TypicalApplication..................................................................................................................................................................153.4 PowerSupply..............................................................................................................................................................................163.5 ClockManagement...................................................................................................................................................................163.6 I2SDigitalAudioBus...............................................................................................................................................................163.7 DSDMode.....................................................................................................................................................................................173.8 EthernetInterfacing................................................................................................................................................................183.9 NetworkSetup...........................................................................................................................................................................193.10 DigitalVolumeControl...........................................................................................................................................................20

4 SerialPeripheralInterface(SPI).................................................................................................................................................214.1 Registerinterface......................................................................................................................................................................214.2 Interrupts.....................................................................................................................................................................................244.3 TimingRequirements.............................................................................................................................................................244.4 RegisterTypes............................................................................................................................................................................25



4.5 RegisterMap...............................................................................................................................................................................264.6 RegistersDefinition.................................................................................................................................................................274.6.1 Register0x40:VOL.........................................................................................................................................................274.6.2 Register0x41:DVC.........................................................................................................................................................274.6.3 Register0x42:ETL..........................................................................................................................................................274.6.4 Register0x43:ETH.........................................................................................................................................................274.6.5 Register0x44:TDL.........................................................................................................................................................274.6.6 Register0x45:TDH.........................................................................................................................................................274.6.7 Register0x46:PS.............................................................................................................................................................284.6.8 Register0x47:ARN.........................................................................................................................................................284.6.9 Register0x48:ALN.........................................................................................................................................................284.6.10 Register0x49:TRN......................................................................................................................................................284.6.11 Register0x4A:COV......................................................................................................................................................284.6.12 Register0x4B:TRF.......................................................................................................................................................284.6.13 Register0x4C:IP0........................................................................................................................................................284.6.14 Register0x4D:IP1........................................................................................................................................................294.6.15 Register0x4E:IP2........................................................................................................................................................294.6.16 Register0x4F:IP3.........................................................................................................................................................294.6.17 Register0x50:IF0.........................................................................................................................................................294.6.18 Register0x51:IF1.........................................................................................................................................................304.6.19 Register0x52:IF2.........................................................................................................................................................304.6.20 Register0x59:OFMT...................................................................................................................................................304.6.21 Register0x60:ELS........................................................................................................................................................314.6.22 Register0x61:SR..........................................................................................................................................................314.6.23 Register0x62:BPS.......................................................................................................................................................314.6.24 Register0x65:MAG......................................................................................................................................................314.6.25 Register0x66:SCR.......................................................................................................................................................324.6.26 Register0x68:MAC0...................................................................................................................................................324.6.27 Register0x69:MAC1...................................................................................................................................................324.6.28 Register0x6A:MAC2...................................................................................................................................................324.6.29 Register0x6B:MAC3...................................................................................................................................................324.6.30 Register0x6C:MAC4...................................................................................................................................................324.6.31 Register0x6D:MAC5...................................................................................................................................................324.6.32 Register0x6F:FIRM....................................................................................................................................................33

5 FirmwareUpdate...............................................................................................................................................................................346 MechanicalData.................................................................................................................................................................................356.1 BoardDimensions....................................................................................................................................................................356.2 ModuleBottomView...............................................................................................................................................................356.3 ModuleSideView.....................................................................................................................................................................366.4 BackplaneFootprintTopView...........................................................................................................................................36

7 RelatedProducts................................................................................................................................................................................377.1 Kitsandevaluationplatforms.............................................................................................................................................377.2 CustomApplications...............................................................................................................................................................37



7.3 S8andQ8Upsamplers...........................................................................................................................................................377.4 DMCKDualMasterClockModule......................................................................................................................................37

8 OrderingInformation......................................................................................................................................................................388.1 PartNumber...............................................................................................................................................................................388.2 ContactInformation................................................................................................................................................................38



Preface

I. AboutThisDatasheet

This document provides the information needed to design and integrate the MR-MOD Ethernet MediaRendererModuleintoyourproduct.Formoreinformation,pleaserefertotheproductdescriptionavailablefromtheengineeredWebsiteat:www.engineered.ch

II. CompanyInformation

engineeredSAAvenuedesSports281400Yverdon-les-BainsSwitzerland+41215343966info@engineered.ch/www.engineered.ch

III. Notice

engineeredSAprovidestheenclosedproduct(s)underthefollowingconditions:Theuserassumesallresponsibilityandliabilityforproperandsafehandlingofthegoods.Further,theuserindemnifies engineered SA from all claims arising from the handling or use of the goods. InformationprovidedbyengineeredSAisbelievedtobeaccurateandreliable.However,noresponsibilityisassumedbyengineeredSA for itsuse.Pleasebeaware that theproductsreceivedmaynotberegulatorycompliantoragency certified. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BELIABLETOTHEOTHERFORANYINDIRECT,SPECIAL,INCIDENTAL,ORCONSEQUENTIALDAMAGES. engineered SAcurrentlydealswithavarietyofcustomersforproducts,andthereforeourarrangementwiththeuserisNOTEXCLUSIVE.engineeredSAassumesNOLIABILITYFORAPPLICATIONSASSISTANCE,CUSTOMERPRODUCTDESIGN,SOFTWAREPERFORMANCE,ORINFRINGEMENTOFPATENTSORSERVICESDESCRIBEDHEREIN.Pleasereadthedatasheetand,specifically,the“ProductWarningsandRestrictions”noticeinthedatasheetprior to handling the product. This notice contains important safety information. Persons handling theproduct must have electronics training and observe good laboratory practice standards. No license isgrantedunderanypatentrightorotherintellectualpropertyrightofengineeredSAcoveringorrelatingtoanymachine, process, or combination inwhich such engineered SA products or servicesmight be or areused.

IV. ProductWarningsandRestrictions

It is important to operate this product within the specified input and output range described in thisdocument.Exceedingthespecifiedinputrangemaycauseunexpectedoperationand/orirreversibledamagetotheproduct.If youhavequestions regarding the input range, please contact engineered SA customer support prior toconnectingthepowersupply.Applyingloadsoutsideofthespecifiedoutputrangemayresultinunintendedoperation and/or possible permanent damage to the product. Please consult the datasheet prior toconnecting any load. If you have doubts concerning the load specification, please contact engineered SAcustomersupport.



V. RepairandMaintenance

Routinemaintenance is not required. This product is warranted to be free of any defect with respect toperformance,quality,reliabilityandworkmanshipforaperiodofSIX(6)monthsfromthedateofshipmentfromengineered.Intheeventthatyourproductprovestobedefectiveinanywayduringthiswarrantyperiod,wewillgladlyrepairorreplacethispieceofequipmentwithaunitofequalorsuperiorperformancecharacteristics.Shouldyoufindthisproducthasfailedafteryourwarrantyperiodhasexpired,wewillrepairyourdefectivepieceofequipmentforaslongassuitablereplacementcomponentsareavailable.You,theowner,willbearanylabourand/orcomponentcostsincurredintherepairorrefurbishmentofsaidequipment,beyondtheSIX(6)monthswarrantyperiod.Anyattempttorepairthisproductbyanyoneduringthisperiodotherthanbyengineeredoranyauthorized3rdpartywillvoidyourwarranty.engineered reserves the right to assess anymodifications or repairsmade by you and decide if they fallwithin warranty limitations, should you decide to return your product for repair. In no event shallengineered be liable for direct, indirect, special, incidental, or consequential damages (including loss andprofits)incurredbytheuseofthisproduct.Impliedwarrantiesareexpresslylimitedtothedurationofthiswarranty.

VI. DocumentationReleaseNotice

Thisdocumentisunderrevisioncontrolandupdateswillonlybeissuedasareplacementdocumentwithanewversionnumber.Productspecificationsaresubjecttochangewithoutnotice.



1 Introduction

1.1 Highlights

TheEthernetMediaRendererModule(MR-MOD)isacompact,easy-to-integrateOEMsolutionfornetworkaudioplaybacksystems.KeyfeaturesfortheMR-MODinclude:

• DigitalMediaRenderer.• UPnPAV2.0/DLNA.• Playinganddecodingcommonaudioformats*fromHTTPstreams.• PCMresolutionupto32-bit,samplingrateupto384kHz.• SupportfornativeDSD64,DSD128andDSD256.• Bit-perfectdatatransmission.• 2-channelasynchronousendpointforjitter-freestereoplayback.• Supportforgaplessplayback.• Embedded32-bitdigitalvolumeattenuator.• I2Sserialaudiooutputinslavemode.• EthernetRJ45interface.• Hardwaremodeforeasyintegration.• SPIinterface.• BasedonAnalogDeviceBlackfinBF537DSP.

(*)Subjecttolicensingbythefinalproductmanufacturerforthevariousaudiodecoders.

TheMR-MODplaysmusicfromstreams,fromafileserveroranInternetradio,actingasaUPnPAV/DLNAMedia Renderer device. Common PCM (Pulse Code Modulation) audio formats are supported, includinglosslessFLACat192kHz24-bit.One-bitDSD(DirectStreamDigital)isalsosupportedviauncompressedDSFandDFFfiles.TheEthernetstreamisasynchronousandtheaudiodataareextractedattherateofthelocalclocks.Thus,foroptimalperformances,thedigitalaudiooutputportoftheMR-MODworksinslavemodeandassuresbit-perfectdatatransferandjitter-freeclocking.

1.2 FirmwareVersion

Thisdatasheetisbasedonthecurrentfirmwareversionv1.50.



1.3 FunctionalBlockDiagram

Figure1-1–functionalblockdiagram

Refertochapter3“ApplicationInformation”formoredetailsaboutthetypicalsetupformusicplaybackoverahomenetworkandtheMR-MODintegration.

BlackfinBF537 DSP

256MbRAM

64MbFlash

ethernetPHY

25MHz

Voltage regulators

Voltage supervisor

Digital Audio Clocks

Digital Audio Data

Control Flags

Serial Peripheral Interface

ethernet

Power Supply



2 CharacteristicsandSpecifications

2.1 ElectrostaticDischargeWarning

Many of the components in this product are subject to be damaged by electrostatic discharge (ESD).Customers are advised to observe proper ESD precautions when unpacking and handling the board,includingtheuseofagroundedwriststrapatanapprovedESDworkstation.Caution:FailuretoobserveESDhandlingproceduresmayresultindamagetotheproduct.

2.2 RecommendedOperatingConditions

Table2-1indicatestherecommendedconditionsunderwhichtheproductshouldrunproperly.

Parameter RecommendConditionPowersupplyvoltage 3.30VDC

Inputsignalvoltage VIL(min/max):0.0V/0.4V VIH(min/max):2.4V/3.3V

Operatingfree-airtemperature TA(min/max):0°C/60°C

Table2-1–recommendedoperatingconditions

2.3 AbsoluteMaximumRatings

Theuser shouldbeawareof theabsolutemaximumoperatingconditions for theMR-MOD.Stressbeyondmaximumratingsmaycausepermanentdamagetothedevice.Table2-2summarizesthecriticaldatapoints.

Parameter Min. Max.Powersupplyvoltage -0.30V 3.60V

Inputsignalvoltage -0.30V 3.60V

Table2-2–absolutemaximumratings

2.4 ElectricalSpecifications

Parameter Min. Typ. Max.ExternalDCsupplyvoltage 3.15V 3.30V 3.45V

ExternalDCsupplycurrent 450mA 750mA

LVTTLoutputhighlevelVIH VDD-0.4V 3.10V VDD

LVTTLoutputlowlevelVIL 0 0.2V 0.4V

Table2-3–electricalspecifications



2.5 DigitalAudioSpecifications

Parameter Min. Typ. Max.PCMinputresolution 16-bit 32-bit

PCMinputsamplingfrequency 44.1kHz 384kHz

PCMdynamicrange 32-bit

DSDinputsamplingfrequency 2.8224MHz 11.2896MHz

Table2-4–digitalaudiospecifications

2.6 AudioFormats

ThefollowingaudioformatsaresupportedbytheMR-MOD:

• FLAC(FreeLosslessAudioCodec)• WAV(WaveformAudioFileFormat)• MP3(MpegAudioLayer3)• ALAC(AppleLosslessAudioCodec)• AAC(AdvancedAudioCoding)• AIFF(AudioInterchangeFileFormat)• DSFandDFF(DSDstreamfile)

Theaudiodata inWAVandstandardAIFFfilesareuncompressedpulse-codemodulation(PCM).Likeanynon-compressed, lossless format, it uses much more disk space than compressed formats. SuchuncompressedPCMstreamsaresupportedupto384kHz/32-bit.FLAC isanopen formatwithroyalty-free licensing. Itsupports formetadata tagging,albumcoverart,andfast seeking. The technical strengths of FLAC compared to other lossless formats lie in its ability to bestreamedanddecodedquickly,whichisindependentofcompressionlevel.SinceFLACisalosslessscheme,it is suitable as an archive format for owners of CDs and othermediawhowish to preserve their audiocollections.TheMR-MODdecodesFLACfilesupto192kHz.MP3 andAAC are lossy compressions and encoding schemes for digital audio. These are non-free codecscovered by patents and subject to licensing by the final product manufacturer. The MR-MOD offers thetechnical ability to decode such formats, but engineered is not responsible for non-free audio codecslicensing.DSF andDFF filesmay containmulti-channel audio data and various resolutions. TheMR-MOD supportsuncompressedone-bitstereoaudioat2.8224MHz,5.6448MHzand11.2896MHz.Note: It is the responsibility of the manufacturer of the final product (the brand) to take care of the licensingandfeesforthenon-freeaudiocodecs.



2.7 PinConfiguration

TheMR-MODusesHiroseFX8-60P-SVconnectorsbelowtheboard.Forphysicallocationofthepins,refertochapter“MechanicalData”.

!

BITCLK

LRCLK

SDATA0

SDATA1

3

58

4

57

11

13

12

14

47

48

39

24

37

25

99

44K1_EN

RATE0

RATE1

DSD/PCM

MUTE

INT

SS

MOSI

MISO

SCK

RESET

LED_SPEED

LED_ACT

TX+

RX+

TX-

RX-

VA

110

72

108

74

107

75

106

+3.3V

9 10 103

27 51 52 73 79

GND

LED_S0

LED_S1

46

44

Dig

ital A

udio

Clo

cks

and

Dat

aD

igita

l Aud

ioC

ontro

lS

eria

l Per

iphe

ral

Inte

rface

Eth

erne

tS

tatu

s

Figure2-1–pinconfiguration



2.8 PinDescriptions

Table2-5describessignalsandpinassignments.Pinsnotlistedherearereservedforfutureuseandmustbeleftunconnected.Pin# Name Type Description

3 I2S_BITCLK Input SerialAudioBitClockInput–Serialbitclockforaudiodata.

58 I2S_LRCLK Input SerialAudioLeft/RightClockInput–FramesyncclockforPCMaudiodata.

4 I2S_SDATA0 Output SerialAudioDataOutput–StereoPCMaudiodataorDSDaudioleft-channeldata.

57 I2S_SDATA1 Output SerialAudioDataOutput–DSDaudioright-channeldata.

11 CC_44K1_EN OutputSamplingFrequencyLow:thesamplingfrequencyisamultipleof44.1kHz.High:thesamplingfrequencyisamultipleof48kHz.RefertoTable3-1.

12 CC_RATE1 Output SamplingRateFlag–Samplingrateinformation.RefertoTable3-1.13 CC_RATE0 Output SamplingRateFlag–Samplingrateinformation.RefertoTable3-1.

47 CC_MUTE OutputMuteLow:theaudiodatastreamisnotvalidandtheDACmustbemuted.High:theaudiodatastreamisvalid.

14 CC_DSD/PCM OutputDSDFormatLow:theoutputsignalisPCMHigh:theoutputsignalisDSD

48 SPI_INT Output SPIInterrupt–Activelow.

39 SPI_SS Input SPISlaveSelect–Activelow.

24 SPI_MOSI Input SPIDataInput

37 SPI_MISO Output SPIDataOutput

25 SPI_SCK Input SPIClock

46 LED_S0 Output StatusLED0–Activehigh.

44 LED_S1 Output StatusLED1–Activehigh.

72 ETH_LED_ACT Output EthernetActivityLED–Activelow,blinkonactivity.

74 ETH_RX+ Output Ethernet

75 ETH_RX- Output Ethernet

106 ETH_VA Power Ethernet–Power.

108 ETH_TX+ Output Ethernet

107 ETH_TX- Output Ethernet

110 ETH_LED_SPEED Output EthernetSpeedLED–Indicatesselectedspeed10/100.0:100Mb/1:10Mb.

99 RESET# Input Reset–Activelow.Thissignalmaybeusedtoforceareset.Ifnotused,donotconnect.

9 VDD Power PowerSupplyInput:+3.30V



27 GND Ground Ground





Table2-5–pindescriptions



3 ApplicationInformation

3.1 HomeNetworkDevices

3.1.1 DigitalMediaServer(DMS)MultimediafilesarestoredonthisdeviceandaremadeavailabletothenetworkDigitalMediaRenderers.Ex.:computer,network-attachedstorage(NAS)devices.

3.1.2 DigitalMediaRenderer(DMR)ThisdeviceiscontrolledbyaDigitalControlPointandcanplaythecontentofaDigitalMediaServer.Ex.:networkaudioplayerbasedontheMR-MOD,audio/videoreceiver,TV,remotespeakers.

3.1.3 DigitalControlPoint(DCP)ThisdevicecanbrowsethecontentonaDigitalMediaServerandcontrolaDigitalMediaRenderertoplaythesefiles.Ex.:smartphone,tablet,computer.

3.2 TypicalSetup

TheMR-MOD provides a very high quality solution to play audio files on a home network. Thanks to itscompatibilitywiththeUPnPAV2.0standard,itsintegrationintoahomenetworkisveryeasy.Developedforhigh-endHi-Fisystems,itachievesbit-perfectplaybackwithnocompromiseonsoundquality.

Figure3-1–typicalsetupofanetworkaudiosystem

Howitworks:

1. MusicfilesarestoredontheMediaServer.2. Theusercanbrowsethefilesandsend/receivecommands(play,volume,displaytime,cover...)via

theControlPoint.3. The network audio Media Renderer Module (MR-MOD) fetches a stream to play from the Media

Server,thenconvertsitintoaudiodata.4. TheaudiodataaresenttotheDACwhichconvertsthemintoananalogsignal.Thissignalcanthenbe

amplifiedandplayedonspeakers.

MR-MOD DACDHCPRouter

ethernetMedia Server

ethernet

UPnP AV Control Point

WiFi

audio OUT

Media Renderer



3.3 TypicalApplication

ThedesignerhasseveraloptionstointegratetheMR-MODOEMmoduleintoasystem.Forinstance,theI2Sserialaudiodataoutputbuscanbeconnectedto:

• aD/AConverter(DAC)inordertooutputanalogaudiosignal• aDigitalaudioTransmitter(DIT)inordertooutputS/PDIFsignal• aDSPtoapplydigitalprocessing(e.g.oversampling)• anFPGAforclockandsignalrouting

TheI2Soutputportof themodule isconfiguredasaslavedevice.Bitclockandleft/rightclockhavetobeprovidedbyanexternaldevice,beingaD/Aconverter,anFPGAoranyothercircuitabletobeclockmasteronthedigitalaudiobus.However,bitclockandleft/rightclockfrequencyhavetomatchthesamplingrateofthefileplayedoverthenetwork,whichinvolvesthefollowingconcept:

• generatingtwomasterclocks:22.5792MHzand24.5760MHz• selectingtheappropriatemasterclockbyreadingthehardwareflag44K1_EN#• dividingthemasterclockbytheappropriateratiotoproducebitclockandleft/rightclock,according

tothehardwareflagsRATE0andRATE1The behaviour of the hardware flags in explained further in Table 3-1. Clock frequencies and ratios aredetailedinTable3-2.The following drawing illustrates an applicationwhere the clock selection, DAC and DIT configuration isperformedbyamicro-controller(MCU).

MR-MOD

MCUClock

Management

DAC

DITControl

I2S DataLEFT

RIGHT

S/PDIF

ethernet

FlagsGPIO

I2S Clocks

Figure3-2–exampleofanetworkaudioplayerbasedontheMR-MOD



3.4 PowerSupply

TheMR-MODmodule integrates a voltage supervisor that resets the DSP when the power supply dropsbelow a defined threshold. Power supply regulation, voltage precision, current capability and connexionimpedanceareimportantfactorstoensurecleanoperationofthemodule.Caution:Failuretorespectthepowersupplypolarityandvoltagelevelmayresultindamagetotheproduct.

3.5 ClockManagement

TheMR-MOD I2S port is clock-slave.Master clock, bit clock and left/right clock (MCLK, BITCLK, LRCLK)mustbesuppliedexternally,asshowninFigure3-3.Anexternallogichastomonitorthehardwareflags(RATE0,RATE1and44K1_EN#)andselectthecorrectclockstodrivertheMR-MODI2Sport.SeeTable3-1andTable3-2formoreinformation.

Figure3-3–clockmanagement

3.6 I2SDigitalAudioBus

ThedigitalaudioportisconfiguredinI2S,slavemode.Bitandleft/rightclocksaregeneratedexternally.TheMR-MODsuppliesthedatasignalsandtheclockmanagementinformation.Thedatasignalsaremadeoftwolines:SDATA0andSDATA1.Bydefault,onlySDATA0isusedinPCMaudio.Theclockmanagementinformationismadeofthreesignals:RATE0,RATE1and44K1_EN(Table3-1).

Figure3-4–I2Sdataformat

MR-MOD

BITCLK and LRCLK

Generator

DAC

SDATA

BITCLK

LRCLK

MCLK

24.5760MHz

22.5792MHz0

1RATE0, RATE1

44K1_EN#

LRCLK

BITCLK

SDATA

left channel right channel

MSB LSB MSB LSB



TheMUTEsignalindicateswhenevertheserialdataarenolongervalidandthereforeshouldbediscarded.Table3-1showshowtheclockmodesignalsmustbedecoded.Left/RightClockFrequency(Fs) RATE0 RATE1 44K1_EN

44.1kHz High High Low

48kHz High High High

88.2kHz Low High Low

96kHz Low High High

176.4kHz High Low Low

192kHz High Low High

352.8kHz Low Low Low

384kHz Low Low High

Table3-1–relationbetweensamplingfrequencyandhardwareflags

Table 3-2 shows how the audio sampling frequency (Fs), the bit clock frequency and the master clockfrequencyarerelated.Left/RightClockFrequency(Fs) BitClockRatio MasterClockRatio MasterClockFrequency

44.1kHz 64*Fs 512*Fs 22.5792MHz

48kHz 64*Fs 512*Fs 24.5760MHz

88.2kHz 64*Fs 256*Fs 22.5792MHz

96kHz 64*Fs 256*Fs 24.5760MHz

176.4kHz 64*Fs 128*Fs 22.5792MHz

192kHz 64*Fs 128*Fs 24.5760MHz

352.8kHz 64*Fs 64*Fs 22.5792MHz

384kHz 64*Fs 64*Fs 24.5760MHz

Table3-2–relationbetweenleft/rightclock,masterclockandbitclock

3.7 DSDMode

WhenplayingDSD, the I2Sdigitalaudiobus isre-configured inorder tooutputDSDdata.Left/rightclock(LRCLK)isdiscarded.Pin# Name PCMSignal DSDSignal

3 I2S_BITCLK BITCLK BITCLK

58 I2S_LRCLK LRCLK n/a

4 I2S_SDATA0 PCMdataL/R DSDdataleft

57 I2S_SDATA1 n/a DSDdataright

14 CC_DSD/PCM Low High

Table3-3–pinmappinginPCMandDSDmode



SupportfornativeDSD64,DSD128aswellasDSD256isprovidedbytheMR-MODmodule.DSDdataformatisindicatedbytheflagCC_DSD/PCMonpin14.

CC_DSD/PCM DataStreamType

Low PCM

High DSD

Table3-4–Datastreamtype

Table3-5 showshow theDSD frequency is indicatedby thehardware flags, andTable3-6 illustrates therelationbetweenDSDrate,BitClockandMasterClockfrequencies.

DSDType RATE0 RATE1 44K1_EN#DSD64 High High Low

DSD128 Low High Low

DSD256 High Low Low

Table3-5–RelationbetweenDSDrateandhardwareflags

DSDType BitClockFrequency MasterClockFrequency

DSD64 2.8224MHz 22.5792MHz

DSD128 5.6448MHz 22.5792MHz

DSD256 11.2896MHz 22.5792MHz

Table3-6–RelationbetweenDSDrate,bitclockandmasterclock

3.8 EthernetInterfacing

TheMR-MOD integrates an on-boardEthernet interface.Only theRJ45 connector andESDprotection areneededonthebackplaneboard,asshownonFigure3-5.Note: RJ45connectorisshownhereforreferenceonly,andbasedonpartnumberJ0011D01NLfromPulse ElectronicsCorporation.Pinnumberingvariesfromonemanufacturer/modeltotheother.



Figure3-5–Ethernetinterfacing

3.9 NetworkSetup

The MR-MOD is compatible with the UPnP AV/DLNA specification and no specific user configuration isneeded to integrate it intoanEthernetnetwork.TheremustbeaDHCPserveron thenetworkwhere theMR-MODoperates.TheMR-MODwillfetchitsconfigurationinformationdirectlyfromtheDHCPserver.Twostatussignalsgive informationabout theboot statusof themodule.Theycanbeconnected tostatusLEDsfordiagnostic.

LED_S1 LED_S0 Description1 1 Powerup.Booting.

1 0 Systembooted

0 1 Systembooted.Networkconfigured.

0 0 Anerroroccurred

Table3-7–statusLEDdescription

!

LED_SPEED

LED_ACT

TX+

RX+

TX-

RX-

VA

110

72

108

74

107

75

106

470R

470R

+3.3V

LED_Y+

LED_Y-

LED_G+

LED_G-

TD+

RD+

TD-

RD-

CTT

CTR

GND

RJ45MR-MOD12

11

9

10

1

3

2

6

4

5

8

10R

CHS13

CHS14GND

CHASSIS

10nF

10pF 10pF 10pF 10pF



3.10 DigitalVolumeControl

ThevolumeinformationistransmittedfromtheControlPointtotheMR-MODviatheEthernetconnection.Bydefault, thecorrespondingattenuation is thencomputed insidetheDSPandappliedtotheserialaudiodataoutput.Mostofbasicdigitalvolumecontrollersdeteriorate theaudiosignaldue to truncationorroundingerrors,butthankstoa32-bitcalculationthesignalintegrityispreservedhere.Pleasenotethatthereisalatencyonvolumechangesduetotherenderer'sbufferingsystem.

Figure3-6–volumecontroldescription

TheMR-MODembeddedvolumecontrolcanbedisabledviatheSPIinterface.Inthiscase,theattenuationisnotappliedonthedataandthevolumecontrolinformationisavailableforreadingviaSPI.Refertochapter4“SerialPeripheralInterface(SPI)”formoreinformation.

MR-MOD

DAC

DHCPRouter

Media Server

UPnP AV ControlPoint

Media Data(tags, covers, …)

Controls(volume, play, …)

SerialAudio Data(I2S, S/PDIF)

Audio Stream Audio Stream

Media Renderer

32-bit digitalvolume control



4 SerialPeripheralInterface(SPI)TheMR-MODfeaturesafull-duplexserialportbasedontheSerialPeripheralInterfacestandard.The SPI port communicates in slavemode. It is used to access registers allowing theMR-MODmodule totransmitinformationtothehostdevice,referredasmaster,andtobeconfiguredforthedesiredoperationalmode.AninterruptlineisprovidedtoindicateadatachangeandavoidtheneedforthehosttopolltheMR-MODcontinuously.TheoperationoftheSPIportmaybecompletelyasynchronouswithrespecttotheaudiostreamrates.

4.1 Registerinterface

The SPI port is a five-wires serial interface where SPI_SS (active low) is the module chip select signal,SPI_SCK is thecontrolportbit clock(input into theMR-MODfromthehostdevice),SPI_MOSI is the inputdatalinefrommaster,SPI_MISOistheoutputdatalinetothemasterandSPI_INTistheinterruptline.Datawordsare16-bitlongandtransmittedinMSBFformat.DataisclockedinontherisingedgeofSPI_SCKandclockedoutonthefallingedge.Figure4-1andFigure4-2illustratetheoperationoftheSPIportaswellastheprotocolforregisterreadandwriteoperations.

Figure4-1–SPIprotocolforregisterwriteoperation

The register WRITE operation requires two 16-bit words to be sent by the host device. A handshakingmechanism ensures that the transfer is valid. Refer to the register description hereafter for detailedinformation.

Figure4-2–SPIprotocolforregisterreadoperation

TheregisterREADoperationrequirestwo16-bitwordstobesentbythehostdevice,thesecondonebeingadummyword.Ahandshakingmechanismensuresthatthetransferisvalid.Refertotheregisterdescriptionhereafterfordetailedinformation.

!

SPI_SS

SPI_SCK

SPI_MOSIMSB LSB MSB LSB

Header Word Data Word

SPI_MISOMSB LSB MSB LSB

Status Word Status WordHi-Z Hi-Z

!

SPI_SS

SPI_SCK

SPI_MOSIMSB LSB MSB LSB

Header Word Dummy Word

SPI_MISOMSB LSB MSB LSB

Status Word Status + Data WordHi-Z Hi-Z



Figure4-3–SPIprotocolforregisterburstreadoperation.

Some registers allow readingmore than oneword and therefore a longer data transfer is required. Thishappenswithstringandbufferdatatypes.Whenaccessingtheseregisters,aburstreadtransferisused.Thelengthofthetransferdependsonthedatatype.AregisteraccessismadeofoneHeaderWordfollowedbyoneormoreData/DummyWord.Delaybetweeneach Word transferred is critical, please refer to the timing specification. If the maximum delay is notrespected,atimeoutoccur,thecommunicationisresetandthenextexpectedWordisaHeader.Alltransfersrelyuponahandshakingmechanism.ThishandshakingmechanismusesfourbitsofthewordtransmittedbytheMR-MODtothehost.TheVALIDbit indicateswhenevertheSPItransferisvalidornot,meanwhilethePARITYbitallowsforparitycheck.TheREADYbitindicatesifthedeviceisreadytoprocessthetransferorifthismustberepeated.TheSTATEbitindicatesifthecurrenttransferisrelatedtoaHeaderoraDataWord.READYbitclearedmeansthattheDSPisnotreadytoprocessthecommunication.ThelastWordsentbythehostislost,andthereplyisnotvalid.ThelastWordmustbesentagainbythehostuntilREADYisset.AwrongVALIDorPARITYbitmeansa transmissionerroroccurred.Theusemustabort the transferandwaitatleastthecommunicationtimeoutbeforerestartinganewtransfer.TheSTATEbitisheretohelptheusertodetectamisalignmentintheHeader/Datasequencing.Handlingofthisbitisnotmandatory.TheHeaderWordsentbythehostisdefinedasfollows:WordName MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSBHeader 0 0 0 0 0 0 0 0 R/W A6 A5 A4 A3 A2 A1 A0

Table4-1–headerworddefinition

Bit15-8: Setto0Bit7 : R/W:definesaReadorWriteoperation 0=Writeoperation 1=ReadoperationBit6-0 : A6-A0:registeraddressTheDummyWordsentbythehostforaregisterreadoperationisnotused.Allbitsmustbesettozero.

!

SPI_SS

SPI_MOSI Header

SPI_MISO

Dummy Dummy Dummy

Status Status + Data Status + Data Status + Data

SPI_SCK



TheDataWordsentbythehostforaregisterwriteoperationisdefinedasfollows:WordName MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSBData 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0

Table4-2–dataworddefinition

Bit15-8: Setto0Bit7-0 : DataTheStatusWordsentbytheMR-MODisdefinedasfollows:WordName MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSBStatus READY STATE PARITY VALID 0 0 0 0 0 0 0 0 0 0 0 0

Table4-3–statusworddefinition

MSB : READY:readybit 0=deviceisnotreadyandtransferfailed 1=deviceisreadyandtransfersucceededBit14 : STATE:indicateswhenevertheWordreceivedbytheMR-MODisaHeaderorData 0=DATAstate 1=CMDstateBit13 : PARITY:evenparityinbits15to0 Thenumberof'1'inbits15to0(includingtheparitybit)isevenBit12 : VALID:validbit 0=transfersucceeded 1=transferfailedBit11-0: Setto0TheStatus+DataWordsentbytheMR-MODisdefinedasfollows:WordName MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSBStatus+Data READY STATE PARITY VALID 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0

Table4-4–status+dataworddefinition

MSB : READY:readybit 0=deviceisnotreadyandtransferfailed 1=deviceisreadyandtransfersucceededBit14 : STATE:interfacecurrentstatus 0=currenttransferfromthehostisaData/DummyWord 1=currenttransferfromthehostisaHeaderWordBit13 : PARITY:evenparityinbits15to0 Thenumberof'1'inbits15to0(includingtheparitybit)isevenBit12 : VALID:validbit 0=transfersucceeded 1=transferfailedBit11-8: Setto0Bit7-0 : Data



4.2 Interrupts

AninterruptlineisprovidedtoindicateadatachangeandavoidtheneedforthehosttopolltheMR-MODcontinuously.Theinterruptlineisanactivelowsignal,assertedwhenoneormoreinterruptflagsareset.Thereare15activehighinterruptflagbitsdispatchedinthethreeregisters.Refertoregistersdefinitionfordetailedinformation.Interruptflagbitsaresetwhenachangeoccursintherelateddata.Interrupt flags must be cleared by the user software once the interrupt has been handled by the host.Writinga'0'clearsthecorrespondinginterruptflag.Theinterruptlineisdeassertedwhenallinterruptflagsarecleared.

4.3 TimingRequirements

SPItimingrequirementsarespecifiedaccordingtothefollowingchartanddiagram.

Figure4-4–SPIprotocoltimingdiagram

Parameter Description Min Max Unit

fSCLK SerialClockfrequency 4 MHz

tSCLK SerialClockperiod 250 ns

tSTH Holdtimeforstartcondition 50 ns

tSSD ChipSelectdeassertionmin.time 7 µs

tSSD ChipSelectdeassertionmax.time 500 ms

tSPH Holdtimeforstopcondition 50 ns

Table4-5–SPItimingrequirements

!

SPI_SS

SPI_MOSI

SPI_MISO

SPI_SCK

t(STH)

t(SCL)

t(SSD) t(SPH)



4.4 RegisterTypes

Registers are entry points to access different types of data. There are three data types: Byte, String andBuffer.TheByteisthesimplesttypeandisusedwhereasingledatabyteisneeded,forinstancewithstatusregister,volumecontrolandvolumelevel.TheStringtypeconsistsofatableofASCII-encodedchars.AsinstandardClanguage,thelastbyteisazero.Whenaccessingaregisterthat implementsastring,burstreadmodemustbeusedanddatamustbereaduntiladatazeroisread.TheStringtypeisusedforArtist/Album/TrackNamesandTrackFormat.

Figure4-5–stringregisterreadoperation

TheBuffertypeiscomposedoftwosections:LengthandData.Lengthisanunsignedintegerof4bytessentLSB first. It indicates thesizeof theData table.Whenaccessinga register that implementsabuffer,burstreadmodemustbeusedtoreadtheentireDatatable.TheBuffertypeisusedfortheCover.

Figure4-6–bufferregisterreadoperation

WhenaccessingaStringorBufferRegisterType,itisimportanttonotethatthedatashouldbereaduntiltheend.Ifnot,atimeoutconditionwilloccurandthenextaccessshallrestartfromthebeginning.

!

SPI_SS

SPI_MOSI Header

SPI_MISO

Header HeaderDummy HeaderDummy HeaderDummy HeaderDummy

HeaderStatus Status char 0 Status char 1 Status char n Status 0x00

char 0 char 1 char n 0x00n-char string:

!

SPI_SS

SPI_MOSI Header

SPI_MISO

Header HeaderDummy HeaderDummy HeaderDummy HeaderDummy

HeaderStatus Status len 0 Status len 1 Status len 2 Status len 3

SPI_SS

SPI_MOSI Header

SPI_MISO

Dummy HeaderDummy HeaderDummy HeaderDummy

Header Status data 1 Status data 2 Status data nStatus data 0

"n" data bytes, where "n" is given by len0 to len4



4.5 RegisterMap

Table4-6summarizestheMR-MODregisters.

Addr Name Description Direction Type

0x40 VOL DigitalVolumeLevel OUT Byte

0x41 DVC DigitalVolumeControl IN Byte

0x42 ETL ElapsedTimeLSB OUT Byte

0x43 ETH ElapsedTimeMSB OUT Byte

0x44 TDL TrackDurationLSB OUT Byte

0x45 TDH TrackDurationMSB OUT Byte

0x46 PS PlayerStatus OUT Byte

0x47 ARN ArtistName OUT String

0x48 ALN AlbumName OUT String

0x49 TRN TrackName OUT String

0x4A COV Cover OUT Buffer

0x4B TRF TrackFormat OUT String

0x4C IP0 IPAddressbyte0 OUT Byte

0x4D IP1 IPAddressbyte1 OUT Byte

0x4E IP2 IPAddressbyte2 OUT Byte

0x4F IP3 IPAddressbyte3 OUT Byte

0x50 IF0 InterruptFlagsregister0 OUT Byte



0x59 OFMT OutputFormat OUT Byte

0x60 ELS EthernetLinkStatus OUT Byte

0x61 SR SampleRate OUT Byte

0x62 BPS BitperSample OUT Byte

0x65 MAG Magic OUT Byte

0x66 SCR Scratch IN/OUT Byte

0x68 MAC0 EthernetMACAddressByte0 OUT Byte

0x69 MAC1 EthernetMACAddressByte1 OUT Byte

0x6A MAC2 EthernetMACAddressByte2 OUT Byte

0x6B MAC3 EthernetMACAddressByte3 OUT Byte

0x6C MAC4 EthernetMACAddressByte4 OUT Byte

0x6D MAC5 EthernetMACAddressByte5 OUT Byte

0x6F FIRM FirmwareVersion OUT String

Table4-6–registermap



4.6 RegistersDefinition

Thissectiongivesdetailsandbitsdefinitionforeachregisteraswellastheirdefaultsettingafterpower-up.

4.6.1 Register0x40:VOLDescription :DigitalVolumeLevelType :ByteDetails :TheVolumeLevelisexpressedinpercent.Thisisanunsigned8-bitinteger.Thevolume rangeis0...100.Thedefaultvalueis100.

4.6.2 Register0x41:DVCDescription :DigitalVolumeControlType :ByteMode :0=DigitalVolumeON 1=DigitalVolumeOFFDVC 7 6 5 4 3 2 1 0BitName X X X X X X X ModeAccessType R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

4.6.3 Register0x42:ETLDescription :ElapsedTimeLSBType :ByteDetails :TheElapsedTimeisexpressedinseconds.Thisisa16-bitunsignedintegervalueformedby thetwobytesofregistersETHandETL.

4.6.4 Register0x43:ETHDescription :ElapsedTimeMSBType :ByteDetails :TheElapsedTimeisexpressedinseconds.Thisisa16-bitunsignedintegervalueformedby thetwobytesofregistersETHandETL.

4.6.5 Register0x44:TDLDescription :TrackDurationLSBType :ByteDetails :TheTrackDurationisexpressedinseconds.Thisisa16-bitunsignedintegervalueformed bythetwobytesofregistersTDHandTDL.

4.6.6 Register0x45:TDHDescription :TrackDurationMSBType :ByteDetails :TrackDuration isexpressed inseconds.This isa16-bitunsigned integervalue formedby thetwobytesofregistersTDHandTDL.



4.6.7 Register0x46:PSDescription :PlayerStatusType :BytePS :00=STOPPED 01=PLAYING 10=PAUSEDPS 7 6 5 4 3 2 1 0BitName X X X X X X PS1 PS0AccessType R R R R R R R RDefault 0 0 0 0 0 0 0 0

4.6.8 Register0x47:ARNDescription :ArtistNameType :StringDetails :TheArtistNameisaStringcomposedofASCII-encodedprintablecharactersandterminated byanullcharacter.

4.6.9 Register0x48:ALNDescription :AlbumNameType :StringDetails :TheAlbumNameisaStringcomposedofASCII-encodedprintablecharactersand terminatedbyanullcharacter.

4.6.10 Register0x49:TRNDescription :TrackNameType :StringDetails :TheTrackNameisaStringcomposedofASCII-encodedprintablecharactersandterminated byanullcharacter.

4.6.11 Register0x4A:COVDescription :CoverType :BufferDetails :TheCoverisactuallynotimplementedandwillreturnanemptybuffer.

4.6.12 Register0x4B:TRFDescription :TrackFormatType :StringDetails :TheTrackFormatisaStringcomposedofASCII-encodedprintablecharactersand terminatedbyanullcharacter.

4.6.13 Register0x4C:IP0Description :IPAddressbyte0Type :ByteDetails :TheIPaddressismadeoffourIPByteRegisterstoformthecompleteMR-MODIPaddress accordingtothestructure:IP3.IP2.IP1.IP0



4.6.14 Register0x4D:IP1Description :IPAddressbyte1Type :ByteDetails :TheIPaddressismadeoffourIPByteRegisterstoformthecompleteMR-MODIPaddress accordingtothestructure:IP3.IP2.IP1.IP0

4.6.15 Register0x4E:IP2Description :IPAddressbyte2Type :ByteDetails :TheIPaddressismadeoffourIPByteRegisterstoformthecompleteMR-MODIPaddress accordingtothestructure:IP3.IP2.IP1.IP0

4.6.16 Register0x4F:IP3Description :IPAddressbyte3Type :ByteDetails :TheIPaddressismadeoffourIPByteRegisterstoformthecompleteMR-MODIPaddress accordingtothestructure:IP3.IP2.IP1.IP0

4.6.17 Register0x50:IF0Description :InterruptFlagsRegister0Type :ByteVOL :VolumechangedET :ElapsedTimechangedTD :TrackDurationchangedPS :PlayerStatuschangedARN :ArtistNamechangedALN :AlbumNamechangedTRN :TrackNamechangedCOV :CoverchangedIF0 7 6 5 4 3 2 1 0BitName COV TRN ALN ARN PS TD ET VOLAccessType R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0



4.6.18 Register0x51:IF1Description :InterruptFlagsRegister1Type :ByteTRF :TrackFormatchangedIP :IPaddresschangedELS :EthernetLinkStatuschangedSR :SampleRatechangedBPS :BitspersamplechangedMAC :MACaddresschangedIF1 7 6 5 4 3 2 1 0BitName X X MAC BPS SR ELS IP TRFAccessType R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0Refertosection4.2“Interrupts”formoreinformationaboutinterrupthandling.

4.6.19 Register0x52:IF2Description :InterruptFlagsRegister2Type :ByteOFMT :OutputFormatchangedIF2 7 6 5 4 3 2 1 0BitName X X X X X X X OFMTAccessType R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0Refertosection4.2“Interrupts”formoreinformationaboutinterrupthandling.

4.6.20 Register0x59:OFMTDescription :OutputFormatType :BytenD/P :DSD/PCMindicator

0=outputsignalPCM1=outputsignalDSD

OFMT 7 6 5 4 3 2 1 0BitName X X X X X X X nD/PAccessType R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0



4.6.21 Register0x60:ELSDescription :EthernetLinkStatusType :ByteELS :0=linkisdown

1=linkisupELS 7 6 5 4 3 2 1 0BitName X X X X X X X ELSAccessType R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

4.6.22 Register0x61:SRDescription :SampleRateType :ByteSR :0=44100Hz;1=48000Hz;2=88200Hz;3=96000Hz

4=176400Hz;5=192000Hz;6=352800Hz;7=384000HzSR 7 6 5 4 3 2 1 0BitName X X X X X SR2 SR1 SR0AccessType R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

4.6.23 Register0x62:BPSDescription :BitsPerSampleType :ByteBPS :0=16-bitsample

1=24-bitsample2=32-bitsample

BPS 7 6 5 4 3 2 1 0BitName X X X X X X BPS1 BPS0AccessType R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

4.6.24 Register0x65:MAGDescription :MagicType :ByteDetails :TheMagicregisterisusedfordebuggingpurpose.Italwaysreturnthevalue0xA5.Itcannot bewritten.MAG 7 6 5 4 3 2 1 0BitName MAG7 MAG6 MAG5 MAG4 MAG3 MAG2 MAG1 MAG0AccessType R R R R R R R RDefault 1 0 1 0 0 1 0 1



4.6.25 Register0x66:SCRDescription :ScratchType :ByteDetails :TheScratchregisterisusedfordebuggingpurpose.Onreaditwillreturnthepreviously writtenvalue.SCR 7 6 5 4 3 2 1 0BitName SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0AccessType R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

4.6.26 Register0x68:MAC0Description :MACAddressbyte0Type :ByteDetails :TheMACaddressismadeofsixMACByteRegisterstoformthecompleteMR-MODMAC addressaccordingtothestructure:MAC0:MAC1:MAC2:MAC3:MAC4:MAC5

4.6.27 Register0x69:MAC1Description :MACAddressbyte1Type :ByteDetails :TheMACaddressismadeofsixMACByteRegisterstoformthecompleteMR-MODMAC addressaccordingtothestructure:MAC0:MAC1:MAC2:MAC3:MAC4:MAC5

4.6.28 Register0x6A:MAC2Description :MACAddressbyte2Type :ByteDetails :TheMACaddressismadeofsixMACByteRegisterstoformthecompleteMR-MODMAC addressaccordingtothestructure:MAC0:MAC1:MAC2:MAC3:MAC4:MAC5

4.6.29 Register0x6B:MAC3Description :MACAddressbyte3Type :ByteDetails :TheMACaddressismadeofsixMACByteRegisterstoformthecompleteMR-MODMAC addressaccordingtothestructure:MAC0:MAC1:MAC2:MAC3:MAC4:MAC5

4.6.30 Register0x6C:MAC4Description :MACAddressbyte4Type :ByteDetails :TheMACaddressismadeofsixMACByteRegisterstoformthecompleteMR-MODMAC addressaccordingtothestructure:MAC0:MAC1:MAC2:MAC3:MAC4:MAC5

4.6.31 Register0x6D:MAC5Description :MACAddressbyte5Type :ByteDetails :TheMACaddressismadeofsixMACByteRegisterstoformthecompleteMR-MODMAC addressaccordingtothestructure:MAC0:MAC1:MAC2:MAC3:MAC4:MAC5



4.6.32 Register0x6F:FIRMDescription :FirmwareVersionType :StringDetails :TheFirmwareVersionisaStringcomposedofASCII-encodedprintablecharactersand terminatedbyanullcharacter.



5 FirmwareUpdateThefirmwareupdaterequiresacomputerconnectedonthesamenetworkastheMR-MOD.Oncethedevicehas booted and is registered on the network, its informationWebpage can be accessedwith an Internetbrowser.Thispagecontainsthefirmwareupdateinterface.OnMSWindows-basedcomputers,browsingthenetworkgiveseasyaccesstothemediarenderer,displayedin theNetworkwindowunder the label "MediaDevices".Adouble-clickon the "AudioRenderer-XX" iconshowstheinformationWebpage.Onotheroperatingsystems, itmayberequired toaccess therouter'sDHCP table toget the renderer's IPaddress.ThensimplyentertheIPaddressinyourbrowsertoaccessit.Theinformationpagecontainsthefirmwareupdateinterface.

Figure5-1–firmwareupdatepage

Download the latest firmware on ourWeb site and save the file on your computer, then extract the ZIParchive.Selectthe“nmr-abc__vX.XX-...bin”fileandclickonthe“StartFirmwareUpdate”button.



6 MechanicalData

6.1 BoardDimensions

Figure6-1–boarddimensions

6.2 ModuleBottomView

Figure6-2–modulebottomview



6.3 ModuleSidesView

Figure6-3–modulesidesview

6.4 BackplaneFootprintTopView

Figure6-4–recommendedbackplanefootprinttopview



7 RelatedProducts

7.1 Kitsandevaluationplatforms

engineeredoffersvarioussolutionstoevaluatetheMR-MODstreamingtechnologyinfull-digitalandanalogaudioenvironments.TheNMRboardismainlyabackplanefortheMR-MODmodulewithon-boardclockmanagementandfacilitatedconnexions.Itprovidesdigitalaudiosignalsonaflex-cableconnectoraswellasbufferedandisolatedS/PDIFoutputforeasyevaluation.Pleasecheckwww.engineered.chforlatestinformationaboutevaluationboardsavailability.

7.2 CustomApplications

TheMR-MODcore is basedonamodernDSP,which runs engineered’s software framework fornetwork-baseddigitalaudioplayback.Thissoftwarecanbecustomizedondemandforspecificrequirements.The NMR hardware platform is mainly foreseen as an evaluation board for engineered’s streamingtechnology. Please check our Web site for more information and contact us for development of customhardwareandsoftwaresolutionsthatmeetsyourproductrequirements.

7.3 S8andQ8Upsamplers

TheS8Moduleintegratesfourkeytechnologiestodeliverahighlyintegratedasynchronousupsampleranddigitalsynchronizerwithbestlow-levelsignallinearityandhighperformancemulti-DACdifferentialoutput.The module features a single audio input port capable of supporting PCM data up to 384kHz or stereoDSD64(2.8224MHz)andDSD128(5.6448MHz).Twodigital8xFSupsampledoutputportsareavailableforinterfacing to external D/A hardware. It provides highest quality Digital to Analog conversion using twoDAC's per channel in differential mode and is a perfect match for theMR-MOD streaming technology inbuildingaHighEndDACcompatiblewithlatesthighdefinitionformats.The Q8 Module shares the software and hardware technology with the S8 Module, but is optimized forprojectsrequiringadown-sampledoutput.Thefirstdigitalaudiooutputportprovidesup-sampleddataat384kHzfordrivingadual-DACsystem.Theseconddigitalaudiooutputportprovidesadirectdown-sampledstreamconfigurablefor1xFS(48kHz),2xFS(96kHz)or4xFS(192kHz)operation.

7.4 DMCKDualMasterClockModule

TheDMCKModulehasbeendevelopedbyengineeredincollaborationwithanexperimentedSwissquartzmanufacturer.Thankstospecialcrystalcut,customoscillatorandclockmuxcircuitsaswellasultimatepowersupplyfiltering,theDMCKmoduleprovidesboth22.5792MHzand24.5760MHzfrequencieswithlowestphase-noisefigures.



8 OrderingInformation

8.1 PartNumber

PartNumber DescriptionMR-MOD EthernetMediaRendererModule

8.2 ContactInformation

engineeredSAAvenuedesSports281400Yverdon-les-BainsSwitzerland+41215343966info@engineered.chwww.engineered.ch

mr-mod · mr-mod ethernet media renderer module 8/38 engineered sa - switzerland doc. v.117e/rev....

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