msp430x5xx family user guide

MSP430x5xx/MSP430x6xx Family

User's Guide

Literature Number: SLAU208J June 2008 Revised December 2011

2

Copyright 20082011, Texas Instruments Incorporated

SLAU208J June 2008 Revised December 2011 Submit Documentation Feedback

ContentsPreface 1

2

...................................................................................................................................... 25 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) ...................... 27 1.1 System Control Module (SYS) Introduction ............................................................................ 28 1.2 System Reset and Initialization .......................................................................................... 28 1.2.1 Device Initial Conditions After System Reset ................................................................. 30 1.3 Interrupts .................................................................................................................... 30 1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 31 1.3.2 SNMI Timing ...................................................................................................... 32 1.3.3 Maskable Interrupts .............................................................................................. 33 1.3.4 Interrupt Processing .............................................................................................. 33 1.3.5 Interrupt Nesting .................................................................................................. 34 1.3.6 Interrupt Vectors .................................................................................................. 34 1.3.7 SYS Interrupt Vector Generators ............................................................................... 35 1.4 Operating Modes .......................................................................................................... 36 1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4 ............................................ 39 1.4.2 Entering and Exiting Low-Power Modes LPMx.5 ............................................................. 39 1.4.3 Extended Time in Low-Power Modes .......................................................................... 40 1.5 Principles for Low-Power Applications .................................................................................. 41 1.6 Connection of Unused Pins .............................................................................................. 41 1.7 Reset Pin (RST/NMI) Configuration ..................................................................................... 41 1.8 Configuring JTAG pins .................................................................................................... 42 1.9 Boot Code .................................................................................................................. 42 1.10 Bootstrap Loader (BSL) .................................................................................................. 42 1.11 Memory Map Uses and Abilities ...................................................................................... 43 1.11.1 Vacant Memory Space ......................................................................................... 43 1.11.2 JTAG Lock Mechanism via the Electronic Fuse ............................................................. 43 1.12 JTAG Mailbox (JMB) System ............................................................................................ 44 1.12.1 JMB Configuration ............................................................................................... 44 1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox ................................................................ 44 1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox ...................................................................... 44 1.12.4 JMB NMI Usage ................................................................................................. 45 1.13 Device Descriptor Table .................................................................................................. 45 1.13.1 Identifying Device Type ......................................................................................... 46 1.13.2 TLV Descriptors ................................................................................................. 47 1.13.3 Peripheral Discovery Descriptor ............................................................................... 48 1.13.4 Calibration Values ............................................................................................... 52 1.14 Special Function Registers (SFRs) ..................................................................................... 54 1.15 SYS Configuration Registers ............................................................................................. 58 Power Management Module and Supply Voltage Supervisor ................................................... 65 2.1 Power Management Module (PMM) Introduction ..................................................................... 66 2.2 PMM Operation ............................................................................................................ 68 2.2.1 VCORE and the Regulator ......................................................................................... 68 2.2.2 Supply Voltage Supervisor and Monitor ....................................................................... 68 2.2.3 Supply Voltage Supervisor and Monitor - Power-Up ........................................................ 73 2.2.4 Increasing VCORE to Support Higher MCLK Frequencies ..................................................... 73Contents 3



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2.3

2.2.5 Decreasing VCORE for Power Optimization ..................................................................... 2.2.6 Transition From LPM3 and LPM4 Modes to AM ............................................................. 2.2.7 LPM3.5, LPM4.5 .................................................................................................. 2.2.8 Brownout Reset (BOR), Software BOR, Software POR ..................................................... 2.2.9 SVS/SVM Performance Modes and Wakeup Times ......................................................... 2.2.10 PMM Interrupts .................................................................................................. 2.2.11 Port I/O Control .................................................................................................. 2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional) ...................................................... PMM Registers ............................................................................................................ Battery Backup Introduction .............................................................................................. Battery Backup Operation ................................................................................................ 3.2.1 Battery Backup Switch Control ................................................................................. 3.2.2 LPMx.5 and Backup Operation ................................................................................. 3.2.3 Resistive Charger ................................................................................................ Battery Backup Registers ................................................................................................

75 75 75 75 76 77 77 77 78 86 86 87 88 88 89

3

Battery Backup System3.1 3.2

...................................................................................................... 85

3.3

4

Auxiliary Supply System (AUX)4.1 4.2

........................................................................................... 91

4.3

Auxiliary Supply System Introduction ................................................................................... 92 Auxiliary Supply Operation ............................................................................................... 93 4.2.1 Startup ............................................................................................................. 94 4.2.2 Switching Control ................................................................................................. 94 4.2.3 Software-Controlled Switching .................................................................................. 94 4.2.4 Hardware-Controlled Switching ................................................................................. 95 4.2.5 Interactions Among fSYS, VCORE, VDSYS, SVMH, and AUXxLVL ................................................ 96 4.2.6 Auxiliary Supply Monitor ......................................................................................... 98 4.2.7 LPMx.5 and Auxiliary Supply Operation ....................................................................... 99 4.2.8 Digital I/Os and Auxiliary Supplies ............................................................................ 100 4.2.9 Measuring the Supplies ........................................................................................ 101 4.2.10 Resistive Charger .............................................................................................. 102 4.2.11 Auxiliary Supply Interrupts .................................................................................... 102 4.2.12 Software Flow .................................................................................................. 103 4.2.13 Examples of AUX Operation ................................................................................. 105 Auxiliary Supply Registers .............................................................................................. 107

5

Unified Clock System (UCS)5.1 5.2

.............................................................................................. 117118 120 120 120 121 121 122 123 124 124 125 125 125 128 130 131 131 132

5.3 5.4

Unified Clock System (UCS) Introduction ............................................................................ UCS Operation ........................................................................................................... 5.2.1 UCS Module Features for Low-Power Applications ........................................................ 5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ............................................... 5.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO) ......................................... 5.2.4 XT1 Oscillator ................................................................................................... 5.2.5 XT2 Oscillator ................................................................................................... 5.2.6 Digitally-Controlled Oscillator (DCO) ......................................................................... 5.2.7 Frequency Locked Loop (FLL) ................................................................................ 5.2.8 DCO Modulator .................................................................................................. 5.2.9 Disabling FLL Hardware and Modulator ..................................................................... 5.2.10 FLL Operation From Low-Power Modes .................................................................... 5.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules ............................... 5.2.12 UCS Module Fail-Safe Operation ............................................................................ 5.2.13 Synchronization of Clock Signals ............................................................................ Module Oscillator (MODOSC) .......................................................................................... 5.3.1 MODOSC Operation ............................................................................................ UCS Module Registers ..................................................................................................

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CPUX .............................................................................................................................. 1416.1 6.2 6.3 MSP430X CPU (CPUX) Introduction .................................................................................. Interrupts .................................................................................................................. CPU Registers ............................................................................................................ 6.3.1 Program Counter (PC) ......................................................................................... 6.3.2 Stack Pointer (SP) .............................................................................................. 6.3.3 Status Register (SR) ............................................................................................ 6.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 6.3.5 General-Purpose Registers (R4 R15) ...................................................................... Addressing Modes ....................................................................................................... 6.4.1 Register Mode ................................................................................................... 6.4.2 Indexed Mode ................................................................................................... 6.4.3 Symbolic Mode .................................................................................................. 6.4.4 Absolute Mode .................................................................................................. 6.4.5 Indirect Register Mode ......................................................................................... 6.4.6 Indirect Autoincrement Mode .................................................................................. 6.4.7 Immediate Mode ................................................................................................ MSP430 and MSP430X Instructions .................................................................................. 6.5.1 MSP430 Instructions ............................................................................................ 6.5.2 MSP430X Extended Instructions .............................................................................. Instruction Set Description .............................................................................................. 6.6.1 Extended Instruction Binary Descriptions .................................................................... 6.6.2 MSP430 Instructions ............................................................................................ 6.6.3 Extended Instructions .......................................................................................... 6.6.4 Address Instructions ............................................................................................ Flash Flash 7.2.1 Flash 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 Flash Memory Introduction ............................................................................................. Memory Segmentation ........................................................................................... Segment A ....................................................................................................... Memory Operation ................................................................................................ Erasing Flash Memory ......................................................................................... Writing Flash Memory .......................................................................................... Flash Memory Access During Write or Erase ............................................................... Stopping Write or Erase Cycle ................................................................................ EMEX with Multiple Bank Flash Memory .................................................................... Checking Flash Memory ....................................................................................... Configuring and Accessing the Flash Memory Controller ................................................. Flash Memory Controller Interrupts ........................................................................... Programming Flash Memory Devices ........................................................................ Memory Registers ................................................................................................ 142 144 145 145 145 147 148 149 151 152 153 157 162 164 165 166 168 168 173 184 185 187 239 282 298 299 300 301 301 305 312 313 313 313 314 314 315 316

6.4

6.5

6.6

7

Flash Memory Controller7.1 7.2 7.3

.................................................................................................. 297

7.4

8

RAM Controller (RAMCTL)8.1 8.2 8.3

................................................................................................ 321

RAM Controller (RAMCTL) Introduction .............................................................................. 322 RAMCTL Operation ...................................................................................................... 322 RAMCTL Registers ...................................................................................................... 323

9

10

................................................................................................................... 325 9.1 Backup RAM Introduction and Operation ............................................................................. 326 9.2 Battery Backup Registers ............................................................................................... 326 Direct Memory Access (DMA) Controller Module ................................................................. 327 10.1 Direct Memory Access (DMA) Introduction ........................................................................... 328 10.2 DMA Operation ........................................................................................................... 330 10.2.1 DMA Addressing Modes ...................................................................................... 330 10.2.2 DMA Transfer Modes .......................................................................................... 330Backup RAMContents 5



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10.3

10.2.3 Initiating DMA Transfers ...................................................................................... 10.2.4 Halting Executing Instructions for DMA Transfers ......................................................... 10.2.5 Stopping DMA Transfers ...................................................................................... 10.2.6 DMA Channel Priorities ....................................................................................... 10.2.7 DMA Transfer Cycle Time .................................................................................... 10.2.8 Using DMA With System Interrupts ......................................................................... 10.2.9 DMA Controller Interrupts ..................................................................................... 10.2.10 Using the USCI_B I2C Module With the DMA Controller ................................................ 10.2.11 Using ADC12 With the DMA Controller ................................................................... 10.2.12 Using DAC12 With the DMA Controller ................................................................... DMA Registers ........................................................................................................... Digital I/O Introduction ................................................................................................... Digital I/O Operation ..................................................................................................... 11.2.1 Input Registers PxIN ........................................................................................... 11.2.2 Output Registers PxOUT ..................................................................................... 11.2.3 Direction Registers PxDIR .................................................................................... 11.2.4 Pullup/Pulldown Resistor Enable Registers PxREN ...................................................... 11.2.5 Output Drive Strength Registers PxDS ..................................................................... 11.2.6 Function Select Registers PxSEL ........................................................................... 11.2.7 P1 and P2 Interrupts, Port Interrupts ........................................................................ 11.2.8 Configuring Unused Port Pins ................................................................................ I/O Configuration and LPMx.5 Low-Power Modes ................................................................... Digital I/O Registers ..................................................................................................... Port Mapping Controller Introduction .................................................................................. Port Mapping Controller Operation .................................................................................... 12.2.1 Access ........................................................................................................... 12.2.2 Mapping ......................................................................................................... Port Mapping Controller Registers ..................................................................................... Cyclic Redundancy Check (CRC) Module Introduction ............................................................. CRC Checksum Generation ............................................................................................ 13.2.1 CRC Implementation .......................................................................................... 13.2.2 Assembler Examples .......................................................................................... CRC Module Registers .................................................................................................. WDT_A Introduction ..................................................................................................... WDT_A Operation ....................................................................................................... 14.2.1 Watchdog Timer Counter (WDTCNT) ....................................................................... 14.2.2 Watchdog Mode ................................................................................................ 14.2.3 Interval Timer Mode ........................................................................................... 14.2.4 Watchdog Timer Interrupts ................................................................................... 14.2.5 Clock Fail-Safe Feature ....................................................................................... 14.2.6 Operation in Low-Power Modes ............................................................................. 14.2.7 Software Examples ............................................................................................ WDT_A Registers ........................................................................................................ Timer_A Introduction .................................................................................................... Timer_A Operation ....................................................................................................... 15.2.1 16-Bit Timer Counter .......................................................................................... 15.2.2 Starting the Timer ..............................................................................................

336 336 337 337 338 338 338 340 340 340 341 350 351 351 351 351 351 352 352 352 354 354 356 368 368 368 368 370 374 375 375 376 378 382 384 384 384 384 384 385 385 385 386 388 390 390 390

11

Digital I/O Module11.1 11.2

............................................................................................................ 349

11.3 11.4

12

Port Mapping Controller12.1 12.2

................................................................................................... 367

12.3

13

Cyclic Redundancy Check (CRC) Module13.1 13.2

........................................................................... 373

13.3

14

Watchdog Timer (WDT_A)14.1 14.2

................................................................................................. 381

14.3

15

Timer_A15.1 15.2

.......................................................................................................................... 387

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15.3

15.2.3 Timer Mode Control ........................................................................................... 15.2.4 Capture/Compare Blocks ..................................................................................... 15.2.5 Output Unit ...................................................................................................... 15.2.6 Timer_A Interrupts ............................................................................................. Timer_A Registers ....................................................................................................... Timer_B Introduction .................................................................................................... 16.1.1 Similarities and Differences From Timer_A ................................................................ Timer_B Operation ....................................................................................................... 16.2.1 16-Bit Timer Counter .......................................................................................... 16.2.2 Starting the Timer .............................................................................................. 16.2.3 Timer Mode Control ........................................................................................... 16.2.4 Capture/Compare Blocks ..................................................................................... 16.2.5 Output Unit ...................................................................................................... 16.2.6 Timer_B Interrupts ............................................................................................. Timer_B Registers ....................................................................................................... Timer_D Introduction .................................................................................................... 17.1.1 Differences From Timer_B .................................................................................... Timer_D Operation ...................................................................................................... 17.2.1 16-Bit Timer Counter .......................................................................................... 17.2.2 High-Resolution Generator ................................................................................... 17.2.3 Starting the Timer .............................................................................................. 17.2.4 Timer Mode Control ........................................................................................... 17.2.5 PWM Generation ............................................................................................... 17.2.6 Capture/Compare Blocks ..................................................................................... 17.2.7 Compare Mode ................................................................................................. 17.2.8 Switching From Capture to Compare Mode ................................................................ 17.2.9 Output Unit ...................................................................................................... 17.2.10 Synchronization Between Timer_D Instances ............................................................ 17.2.11 Timer_D Interrupts ........................................................................................... Timer_D Registers ....................................................................................................... Timer Event Control Introduction ...................................................................................... TEC Operation ........................................................................................................... 18.2.1 AUXCLK Selection Sub-Block ................................................................................ 18.2.2 External Clear Sub-Block ..................................................................................... 18.2.3 Channel Event Sub-Block .................................................................................... 18.2.4 Module Level Connection Between TEC and Timer_D ................................................... 18.2.5 Synchronization Mechanism Between Timer_D Instances ............................................... 18.2.6 Timer Event Control Interrupts ............................................................................... Timer Event Control Registers ......................................................................................... RTC Overview

391 394 396 400 402 408 408 410 410 410 411 414 417 421 423 430 430 433 433 434 436 436 440 443 446 447 447 454 454 456 468 469 469 469 469 470 472 474 475

16

Timer_B16.1 16.2

.......................................................................................................................... 407

16.3

17

Timer_D17.1 17.2

.......................................................................................................................... 429

17.3

18

Timer Event Control (TEC)18.1 18.2

................................................................................................ 467

18.3

19 20

....................................................................................... 481 ............................................................................................................ 481 Real-Time Clock (RTC_A) .................................................................................................. 483 20.1 RTC_A Introduction ...................................................................................................... 484 20.2 RTC_A Operation ........................................................................................................ 486 20.2.1 Counter Mode .................................................................................................. 486 20.2.2 Calendar Mode ................................................................................................. 486 20.2.3 Real-Time Clock Interrupts ................................................................................... 488 20.2.4 Real-Time Clock Calibration .................................................................................. 490 20.3 Real-Time Clock Registers ............................................................................................. 492Real-Time Clock (RTC) Overview19.1Contents 7



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Real-Time Clock B (RTC_B) ............................................................................................... 50321.1 21.2 Real-Time Clock RTC_B Introduction ................................................................................. RTC_B Operation ........................................................................................................ 21.2.1 Real-Time Clock and Prescale Dividers .................................................................... 21.2.2 Real-Time Clock Alarm Function ............................................................................ 21.2.3 Reading or Writing Real-Time Clock Registers ............................................................ 21.2.4 Real-Time Clock Interrupts ................................................................................... 21.2.5 Real-Time Clock Calibration .................................................................................. 21.2.6 Real-Time Clock Operation in LPMx.5 Low Power Mode ................................................ Real-Time Clock Registers ............................................................................................. Real-Time Clock (RTC_C) Introduction ............................................................................... RTC_C Operation ........................................................................................................ 22.2.1 Real-Time Clock and Prescale Dividers ................................................................... 22.2.2 Real-Time Clock Alarm Function ............................................................................ 22.2.3 Real-Time Clock Protection .................................................................................. 22.2.4 Reading or Writing Real-Time Clock Registers ........................................................... 22.2.5 Real-Time Clock Interrupts ................................................................................... 22.2.6 Real-Time Clock Calibration for Crystal Offset Error ...................................................... 22.2.7 Real-Time Clock Compensation for Crystal Temperature Drift .......................................... 22.2.8 Real-Time Clock Operation in LPM3.5 Low-Power Mode ................................................ Real-Time Clock Registers ............................................................................................. 32-Bit Hardware Multiplier (MPY32) Introduction .................................................................... MPY32 Operation ........................................................................................................ 23.2.1 Operand Registers ............................................................................................. 23.2.2 Result Registers ................................................................................................ 23.2.3 Software Examples ............................................................................................ 23.2.4 Fractional Numbers ............................................................................................ 23.2.5 Putting It All Together ......................................................................................... 23.2.6 Indirect Addressing of Result Registers ..................................................................... 23.2.7 Using Interrupts ................................................................................................ 23.2.8 Using DMA ...................................................................................................... MPY32 Registers ........................................................................................................ 504 506 506 506 507 507 509 511 512 524 526 526 526 527 527 528 529 530 533 534 546 548 549 550 551 551 555 558 558 559 560

21.3

22

Real-Time Clock C (RTC_C) ............................................................................................... 52322.1 22.2

22.3

23

32-Bit Hardware Multiplier (MPY32)23.1 23.2

.................................................................................... 545

23.3

24

25

................................................................................................................................ 565 24.1 REF Introduction ......................................................................................................... 565 24.2 Principle of Operation ................................................................................................... 567 24.2.1 Low-Power Operation ......................................................................................... 567 24.2.2 REFCTL ......................................................................................................... 568 24.2.3 Reference System Requests ................................................................................. 569 24.3 REF Registers ............................................................................................................ 572 ADC10_A ........................................................................................................................ 575 25.1 ADC10_A Introduction ................................................................................................... 576 25.2 ADC10_A Operation ..................................................................................................... 578 25.2.1 10-Bit ADC Core ............................................................................................... 578 25.2.2 ADC10_A Inputs and Multiplexer ............................................................................ 578 25.2.3 Voltage Reference Generator ................................................................................ 579 25.2.4 Auto Power Down .............................................................................................. 579 25.2.5 Sample and Conversion Timing .............................................................................. 579 25.2.6 Conversion Result ............................................................................................. 581 25.2.7 ADC10_A Conversion Modes ................................................................................ 581 25.2.8 Window Comparator ........................................................................................... 586REFContents SLAU208J June 2008 Revised December 2011 Submit Documentation Feedback

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25.3

25.2.9 Using the Integrated Temperature Sensor ................................................................. 25.2.10 ADC10_A Grounding and Noise Considerations ......................................................... 25.2.11 ADC10_A Interrupts .......................................................................................... ADC10_A Registers .....................................................................................................

587 588 588 590

26

27

28

29

........................................................................................................................ 26.1 ADC12_A Introduction ................................................................................................... 26.2 ADC12_A Operation ..................................................................................................... 26.2.1 12-Bit ADC Core ............................................................................................... 26.2.2 ADC12_A Inputs and Multiplexer ............................................................................ 26.2.3 Voltage Reference Generator ................................................................................ 26.2.4 Auto Power Down .............................................................................................. 26.2.5 Sample and Conversion Timing .............................................................................. 26.2.6 Conversion Memory ........................................................................................... 26.2.7 ADC12_A Conversion Modes ................................................................................ 26.2.8 Using the Integrated Temperature Sensor ................................................................. 26.2.9 ADC12_A Grounding and Noise Considerations .......................................................... 26.2.10 ADC12_A Interrupts .......................................................................................... 26.3 ADC12_A Registers ..................................................................................................... SD24_B ........................................................................................................................... 27.1 SD24_B Introduction ..................................................................................................... 27.2 SD24_B Operation ....................................................................................................... 27.2.1 Principle of Operation ......................................................................................... 27.2.2 ADC Core ....................................................................................................... 27.2.3 Voltage Reference ............................................................................................. 27.2.4 Modulator Clock ................................................................................................ 27.2.5 Auto Power-Down .............................................................................................. 27.2.6 Analog Inputs ................................................................................................... 27.2.7 Digital Filter ..................................................................................................... 27.2.8 Bit-Stream Input and Output .................................................................................. 27.2.9 Conversion Modes ............................................................................................. 27.2.10 Conversion Operation Using Preload ...................................................................... 27.2.11 Grounding and Noise Considerations ..................................................................... 27.2.12 Trigger Generator ............................................................................................ 27.2.13 SD24_B Interrupts ............................................................................................ 27.2.14 Using SD24_B With DMA ................................................................................... 27.3 SD24_B Registers ....................................................................................................... DAC12_A ........................................................................................................................ 28.1 DAC12_A Introduction ................................................................................................... 28.2 DAC12_A Operation ..................................................................................................... 28.2.1 DAC12_A Core ................................................................................................. 28.2.2 DAC12_A Port Selection ...................................................................................... 28.2.3 DAC12_A Reference .......................................................................................... 28.2.4 Updating the DAC12_A Voltage Output .................................................................... 28.2.5 DAC12_xDAT Data Formats ................................................................................. 28.2.6 DAC12_A Output Amplifier Offset Calibration ............................................................. 28.2.7 Grouping Multiple DAC12_A Modules ...................................................................... 28.2.8 DAC12_A Interrupts ........................................................................................... 28.3 DAC Outputs .............................................................................................................. 28.4 DAC12_A Registers ..................................................................................................... Comp_B .......................................................................................................................... 29.1 Comp_B Introduction .................................................................................................... 29.2 Comp_B Operation ......................................................................................................ADC12_AContents

599600 602 602 602 603 603 604 606 606 612 613 614 616

625626 630 630 631 631 631 631 631 632 635 636 638 639 640 641 641 642

653654 657 657 657 657 657 658 658 659 660 661 662

669670 6719



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29.3

29.2.1 Comparator ..................................................................................................... 29.2.2 Analog Input Switches ......................................................................................... 29.2.3 Port Logic ....................................................................................................... 29.2.4 Input Short Switch ............................................................................................. 29.2.5 Output Filter .................................................................................................... 29.2.6 Reference Voltage Generator ................................................................................ 29.2.7 Comp_B, Port Disable Register CBPD ..................................................................... 29.2.8 Comp_B Interrupts ............................................................................................. 29.2.9 Comp_B Used to Measure Resistive Elements ............................................................ Comp_B Registers ....................................................................................................... LCD_B Controller Introduction ......................................................................................... LCD_B Controller Operation ............................................................................................ 30.2.1 LCD Memory ................................................................................................... 30.2.2 LCD Timing Generation ....................................................................................... 30.2.3 Blanking the LCD .............................................................................................. 30.2.4 LCD Blinking .................................................................................................... 30.2.5 LCD_B Voltage And Bias Generation ....................................................................... 30.2.6 LCD Outputs .................................................................................................... 30.2.7 LCD_B Interrupts .............................................................................................. 30.2.8 Static Mode ..................................................................................................... 30.2.9 2-Mux Mode .................................................................................................... 30.2.10 3-Mux Mode ................................................................................................... 30.2.11 4-Mux Mode ................................................................................................... LCD Controller Registers ...............................................................................................

671 671 671 671 672 673 674 674 674 676 682 684 684 684 685 685 686 688 688 690 693 696 699 702

30

LCD_B Controller30.1 30.2

............................................................................................................. 681

30.3

31

32

............................................................................................................. 713 31.1 LCD_C Introduction ...................................................................................................... 714 31.2 LCD_C Operation ........................................................................................................ 716 31.2.1 LCD Memory ................................................................................................... 716 31.2.2 LCD Timing Generation ....................................................................................... 717 31.2.3 Blanking the LCD .............................................................................................. 718 31.2.4 LCD Blinking .................................................................................................... 718 31.2.5 LCD Voltage And Bias Generation .......................................................................... 719 31.2.6 LCD Outputs .................................................................................................... 722 31.2.7 LCD Interrupts .................................................................................................. 723 31.2.8 Static Mode ..................................................................................................... 725 31.2.9 2-Mux Mode .................................................................................................... 726 31.2.10 3-Mux Mode ................................................................................................... 727 31.2.11 4-Mux Mode ................................................................................................... 728 31.2.12 6-Mux Mode ................................................................................................... 729 31.2.13 8-Mux Mode ................................................................................................... 730 31.3 LCD_C Registers ........................................................................................................ 732 Universal Serial Communication Interface UART Mode ...................................................... 745 32.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 746 32.2 USCI Introduction UART Mode ...................................................................................... 747 32.3 USCI Operation UART Mode ........................................................................................ 749 32.3.1 USCI Initialization and Reset ................................................................................. 749 32.3.2 Character Format .............................................................................................. 749 32.3.3 Asynchronous Communication Format ..................................................................... 749 32.3.4 Automatic Baud-Rate Detection ............................................................................. 752 32.3.5 IrDA Encoding and Decoding ................................................................................ 753 32.3.6 Automatic Error Detection .................................................................................... 754 32.3.7 USCI Receive Enable ......................................................................................... 755LCD_C ControllerContentsCopyright 20082011, Texas Instruments Incorporated

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32.4

32.3.8 USCI Transmit Enable ........................................................................................ 32.3.9 UART Baud-Rate Generation ................................................................................ 32.3.10 Setting a Baud Rate .......................................................................................... 32.3.11 Transmit Bit Timing ........................................................................................... 32.3.12 Receive Bit Timing ........................................................................................... 32.3.13 Typical Baud Rates and Errors ............................................................................. 32.3.14 Using the USCI Module in UART Mode With Low-Power Modes ..................................... 32.3.15 USCI Interrupts ............................................................................................... USCI Registers UART Mode ......................................................................................... Universal Serial Communication Interface (USCI) Overview ....................................................... USCI Introduction SPI Mode ......................................................................................... USCI Operation SPI Mode ........................................................................................... 33.3.1 USCI Initialization and Reset ................................................................................. 33.3.2 Character Format .............................................................................................. 33.3.3 Master Mode .................................................................................................... 33.3.4 Slave Mode ..................................................................................................... 33.3.5 SPI Enable ...................................................................................................... 33.3.6 Serial Clock Control ........................................................................................... 33.3.7 Using the SPI Mode With Low-Power Modes .............................................................. 33.3.8 SPI Interrupts ................................................................................................... USCI Registers SPI Mode ............................................................................................ Universal Serial Communication Interface (USCI) Overview ....................................................... USCI Introduction I2C Mode .......................................................................................... USCI Operation I2C Mode ............................................................................................ 34.3.1 USCI Initialization and Reset ................................................................................. 34.3.2 I2C Serial Data .................................................................................................. 34.3.3 I2C Addressing Modes ......................................................................................... 34.3.4 I2C Module Operating Modes ................................................................................. 34.3.5 I2C Clock Generation and Synchronization ................................................................. 34.3.6 Using the USCI Module in I2C Mode With Low-Power Modes ........................................... 34.3.7 USCI Interrupts in I2C Mode .................................................................................. USCI Registers I2C Mode ............................................................................................. Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview .................................. eUSCI_A Introduction UART Mode ................................................................................. eUSCI_A Operation UART Mode .................................................................................... 35.3.1 eUSCI_A Initialization and Reset ............................................................................ 35.3.2 Character Format .............................................................................................. 35.3.3 Asynchronous Communication Format ..................................................................... 35.3.4 Automatic Baud-Rate Detection ............................................................................. 35.3.5 IrDA Encoding and Decoding ................................................................................ 35.3.6 Automatic Error Detection .................................................................................... 35.3.7 eUSCI_A Receive Enable .................................................................................... 35.3.8 eUSCI_A Transmit Enable .................................................................................... 35.3.9 UART Baud-Rate Generation ................................................................................ 35.3.10 Setting a Baud Rate .......................................................................................... 35.3.11 Transmit Bit Timing - Error calculation .................................................................... 35.3.12 Receive Bit Timing Error Calculation .................................................................... 35.3.13 Typical Baud Rates and Errors ............................................................................. 35.3.14 Using the eUSCI_A Module in UART Mode With Low-Power Modes .................................Contents

755 756 758 758 759 760 763 763 765 774 775 777 777 777 778 779 779 780 780 781 782 788 789 790 791 791 793 794 805 806 806 809 818 818 820 820 820 820 823 824 825 826 826 827 829 830 830 831 83311

33

Universal Serial Communication Interface SPI Mode33.1 33.2 33.3

......................................................... 773

33.4

34

Universal Serial Communication Interface I2C Mode34.1 34.2 34.3

.......................................................... 787

34.4

35

Enhanced Universal Serial Communication Interface (eUSCI) UART Mode35.1 35.2 35.3

........................... 817



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35.4

35.3.15 eUSCI_A Interrupts .......................................................................................... 833 eUSCI_A Registers UART Mode .................................................................................... 835

36

Enhanced Universal Serial Communication Interface (eUSCI) SPI Mode36.1 36.2 36.3

.............................. 843844 844 846 846 846 847 848 848 849 850 850 852

36.4

Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview ....................... eUSCI Introduction SPI Mode ........................................................................................ eUSCI Operation SPI Mode .......................................................................................... 36.3.1 eUSCI Initialization and Reset ............................................................................... 36.3.2 Character Format .............................................................................................. 36.3.3 Master Mode .................................................................................................... 36.3.4 Slave Mode ..................................................................................................... 36.3.5 SPI Enable ...................................................................................................... 36.3.6 Serial Clock Control ........................................................................................... 36.3.7 Using the SPI Mode With Low-Power Modes .............................................................. 36.3.8 SPI Interrupts ................................................................................................... eUSCI Registers SPI Mode ..........................................................................................

37

38

39

............................... 857 37.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview .................................. 858 37.2 eUSCI_B Introduction I2C Mode ..................................................................................... 858 37.3 eUSCI_B Operation I2C Mode ....................................................................................... 859 37.3.1 eUSCI_B Initialization and Reset ............................................................................ 860 37.3.2 I2C Serial Data .................................................................................................. 860 37.3.3 I2C Addressing Modes ......................................................................................... 861 37.3.4 I2C Quick Setup ................................................................................................ 862 37.3.5 I2C Module Operating Modes ................................................................................. 863 37.3.6 Glitch Filtering .................................................................................................. 873 37.3.7 I2C Clock Generation and Synchronization ................................................................. 873 37.3.8 Byte Counter .................................................................................................... 874 37.3.9 Multiple Slave Addresses ..................................................................................... 875 37.3.10 Using the eUSCI_B Module in I2C Mode With Low-Power Modes ..................................... 876 37.3.11 eUSCI_B Interrupts in I2C Mode ............................................................................ 876 37.4 eUSCI_B Registers I2C Mode ........................................................................................ 879 USB Module .................................................................................................................... 889 38.1 USB Introduction ......................................................................................................... 890 38.2 USB Operation ........................................................................................................... 892 38.2.1 USB Transceiver (PHY) ....................................................................................... 892 38.2.2 USB Power System ............................................................................................ 893 38.2.3 USB Phase-Locked Loop (PLL) .............................................................................. 896 38.2.4 USB Controller Engine ........................................................................................ 898 38.2.5 USB Vector Interrupts ......................................................................................... 902 38.2.6 Power Consumption ........................................................................................... 902 38.2.7 Suspend and Resume ......................................................................................... 903 38.3 USB Transfers ............................................................................................................ 903 38.3.1 Control Transfers .............................................................................................. 903 38.3.2 Interrupt Transfers ............................................................................................. 907 38.3.3 Bulk Transfers .................................................................................................. 908 38.4 Registers .................................................................................................................. 910 38.4.1 USB Configuration Registers ................................................................................. 910 38.4.2 USB Control Registers ........................................................................................ 916 38.4.3 USB Buffer Registers and Memory .......................................................................... 923 LDO-PWR Module ............................................................................................................ 931 39.1 LDO-PWR Introduction .................................................................................................. 932 39.2 LDO-PWR Operation .................................................................................................... 933Enhanced Universal Serial Communication Interface (eUSCI) I2C ModeContents SLAU208J June 2008 Revised December 2011 Submit Documentation Feedback

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39.3

39.2.1 Enabling/Disabling ............................................................................................. 39.2.2 Powering the Rest of the MSP430 from the LDO-PWR .................................................. 39.2.3 Powering Other Components in the System from LDO-PWR ........................................... 39.2.4 Applications Not Requiring LDO-PWR ...................................................................... 39.2.5 Current Limitation / Overload Protection .................................................................... 39.2.6 LDO-PWR Interrupts .......................................................................................... 39.2.7 Port U Control .................................................................................................. Registers .................................................................................................................. 39.3.1 LDO-PWR Configuration Registers .......................................................................... Embedded Emulation Module (EEM) Introduction ................................................................... EEM Building Blocks .................................................................................................... 40.2.1 Triggers ......................................................................................................... 40.2.2 Trigger Sequencer ............................................................................................. 40.2.3 State Storage (Internal Trace Buffer) ........................................................................ 40.2.4 Cycle Counter .................................................................................................. 40.2.5 Clock Control ................................................................................................... EEM Configurations .....................................................................................................

933 933 934 934 934 935 935 936 936 940 942 942 942 942 942 943 943

40

Embedded Emulation Module (EEM)40.1 40.2

.................................................................................. 939

40.3

Revision History

....................................................................................................................... 945


Contents

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List of Figures1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. 2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 2-7. 3-1. 3-2. 4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 4-7. 4-8. 4-9. 5-1. 5-2. 5-3. 5-4. 5-5. 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 6-8. 6-9. 6-10. 6-11. 6-12. 6-13. 6-14. 6-15. 6-16. 6-17.14

BOR/POR/PUC Reset Circuit ............................................................................................ 29 Interrupt Priority ............................................................................................................ 31 NMIs With Reentrance Protection ....................................................................................... 32 Interrupt Processing ....................................................................................................... 33 Return From Interrupt ..................................................................................................... 34 Operation Modes .......................................................................................................... 37 Devices Descriptor Table ................................................................................................. 46 System Frequency and Supply/Core Voltages - See Device Specific Datasheet

................................

66

PMM Block Diagram ...................................................................................................... 67 High-Side and Low-Side Voltage Failure and Resulting PMM Actions ............................................. 70 High-Side SVS and SVM ................................................................................................. 71 Low-Side SVS and SVM.................................................................................................. 72 PMM Action at Device Power-Up

.......................................................................................

73

Changing VCORE and SVML and SVSL Levels ........................................................................... 74 Battery Backup Switch Overview ........................................................................................ 87 Charger Block Diagram ................................................................................................... 88 Auxiliary Supply Switch Overview ....................................................................................... 93 System Frequency vs Supply Voltage .................................................................................. 97 Available SVMH Settings vs VCORE Settings ............................................................................. 97 Available AUXxLVL Settings vs SVMH Settings ....................................................................... 98 Auxiliary Supply Monitor Block Diagram

...............................................................................

99

I/Os Powered by Auxiliary Supplies ................................................................................... 101 AUX Connection to ADC ................................................................................................ 101 Charger Block Diagram ................................................................................................. 102 Software Flow Chart ..................................................................................................... 104 UCS Block Diagram

..................................................................................................... ........................................................................................

119 126

Modulator Patterns ....................................................................................................... 125 Module Request Clock System Oscillator Fault Logic .................................................................................................... 129 Switch MCLK from DCOCLK to XT1CLK ............................................................................. 130

........................................................................................ ............................................................................... Program Counter ......................................................................................................... PC Storage on the Stack for CALLA .................................................................................. Stack Pointer ............................................................................................................. Stack Usage .............................................................................................................. PUSHX.A Format on the Stack ........................................................................................ PUSH SP, POP SP Sequence ......................................................................................... SR Bits .................................................................................................................... Register-Byte/Byte-Register Operation ............................................................................... Register-Word Operation ............................................................................................... Word-Register Operation ............................................................................................... Register Address-Word Operation .................................................................................. Address-Word Register Operation .................................................................................. Indexed Mode in Lower 64 KB ......................................................................................... Indexed Mode in Upper Memory ....................................................................................... Overflow and Underflow for Indexed Mode ...........................................................................MSP430X CPU Block Diagram PC Storage on the Stack for Interrupts

143 144 145 145 146 146 146 146 147 149 149 150 150 151 153 154 155

List of Figures



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6-18. 6-19. 6-20. 6-21. 6-22. 6-23. 6-24. 6-25. 6-26. 6-27. 6-28. 6-29. 6-30. 6-31. 6-32. 6-33. 6-34. 6-35. 6-36. 6-37. 6-38. 6-39. 6-40. 6-41. 6-42. 6-43. 6-44. 6-45. 6-46. 6-47. 6-48. 6-49. 6-50. 6-51. 6-52. 6-53. 6-54. 6-55. 6-56. 6-57. 6-58. 6-59. 6-60. 7-1. 7-2. 7-3. 7-4. 7-5. 7-6.

Example for Indexed Mode ............................................................................................. 156 Symbolic Mode Running in Lower 64 KB ............................................................................. 158 Symbolic Mode Running in Upper Memory

..........................................................................

159

Overflow and Underflow for Symbolic Mode ......................................................................... 160 MSP430 Double-Operand Instruction Format ........................................................................ 168 MSP430 Single-Operand Instructions ................................................................................. 169 Format of Conditional Jump Instructions.............................................................................. 170 Extension Word for Register Modes ................................................................................... 173 Extension Word for Non-Register Modes ............................................................................. 173 Example for Extended Register/Register Instruction ................................................................ 174 Example for Extended Immediate/Indexed Instruction .............................................................. 175 Extended Format I Instruction Formats ............................................................................... 176 20-Bit Addresses in Memory

........................................................................................... ....................................................................................

176 178

Extended Format II Instruction Format ................................................................................ 177 PUSHM/POPM Instruction Format RRCM, RRAM, RRUM, and RLAM Instruction Format ............................................................. 178 BRA Instruction Format ................................................................................................. 178 CALLA Instruction Format .............................................................................................. 178 Decrement Overlap ...................................................................................................... 204

.......................................................................................... .......................................................................... Destination OperandCarry Left Shift ................................................................................ Rotate Right Arithmetically RRA.B and RRA.W ..................................................................... Rotate Right Through Carry RRC.B and RRC.W .................................................................... Swap Bytes in Memory .................................................................................................. Swap Bytes in a Register ............................................................................................... Rotate Left ArithmeticallyRLAM[.W] and RLAM.A ................................................................ Destination Operand-Arithmetic Shift Left ............................................................................ Destination Operand-Carry Left Shift .................................................................................. Rotate Right Arithmetically RRAM[.W] and RRAM.A ............................................................... Rotate Right Arithmetically RRAX(.B,.A) Register Mode ......................................................... Rotate Right Arithmetically RRAX(.B,.A) Non-Register Mode ................................................... Rotate Right Through Carry RRCM[.W] and RRCM.A .............................................................. Rotate Right Through Carry RRCX(.B,.A) Register Mode ....................................................... Rotate Right Through Carry RRCX(.B,.A) Non-Register Mode ................................................. Rotate Right Unsigned RRUM[.W] and RRUM.A .................................................................... Rotate Right Unsigned RRUX(.B,.A) Register Mode ............................................................. Swap Bytes SWPBX.A Register Mode ................................................................................ Swap Bytes SWPBX.A In Memory .................................................................................... Swap Bytes SWPBX[.W] Register Mode ............................................................................. Swap Bytes SWPBX[.W] In Memory .................................................................................. Sign Extend SXTX.A .................................................................................................... Sign Extend SXTX[.W] .................................................................................................. Flash Memory Module Block Diagram ................................................................................ 256-KB Flash Memory Segments Example .......................................................................... Erase Cycle Timing ...................................................................................................... Erase Cycle From Flash ................................................................................................ Erase Cycle From RAM ................................................................................................. Byte/Word/Long-Word Write Timing ...................................................................................Stack After a RET Instruction Destination OperandArithmetic Shift LeftList of FiguresCopyright 20082011, Texas Instruments Incorporated

223 225 226 227 228 235 235 262 263 264 265 267 267 269 271 271 272 273 277 277 278 278 279 279 298 299 302 303 304 30515


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7-7. 7-8. 7-9. 7-10. 7-11. 7-12. 7-13. 10-1. 10-2. 10-3. 10-4. 10-5. 13-1. 13-2. 14-1. 15-1. 15-2. 15-3. 15-4. 15-5. 15-6. 15-7. 15-8. 15-9. 15-10. 15-11. 15-12. 15-13. 15-14. 15-15. 16-1. 16-2. 16-3. 16-4. 16-5. 16-6. 16-7. 16-8. 16-9. 16-10. 16-11. 16-12. 16-13. 16-14. 16-15. 17-1. 17-2. 17-3. 17-4.16

Initiating a Byte/Word Write From Flash .............................................................................. 306 Initiating a Byte/Word Write From RAM ............................................................................... 307 Initiating Long-Word Write From Flash ................................................................................ 308 Initiating Long-Word Write from RAM ................................................................................. 309 Block-Write Cycle Timing ............................................................................................... 310 Block Write Flow ......................................................................................................... 311 User-Developed Programming Solution

..............................................................................

315

DMA Controller Block Diagram......................................................................................... 329 DMA Addressing Modes ................................................................................................ 330 DMA Single Transfer State Diagram .................................................................................. 332 DMA Block Transfer State Diagram ................................................................................... 333 DMA Burst-Block Transfer State Diagram ............................................................................ 335 LFSR Implementation of CRC-CCITT Standard, Bit 0 is the MSB of the Result ................................ 374 Implementation of CRC-CCITT Using the CRCDI and CRCINIRES Registers .................................. 376 Watchdog Timer Block Diagram ....................................................................................... 383 Timer_A Block Diagram ................................................................................................. 389 Up Mode

..................................................................................................................

391

Up Mode Flag Setting ................................................................................................... 391 Continuous Mode ........................................................................................................ 392 Continuous Mode Flag Setting ......................................................................................... 392

...................................................................................... Up/Down Mode ........................................................................................................... Up/Down Mode Flag Setting............................................................................................ Output Unit in Up/Down Mode ......................................................................................... Capture Signal (SCS = 1) ............................................................................................... Capture Cycle ............................................................................................................ Output Example Timer in Up Mode ................................................................................. Output Example Timer in Continuous Mode ....................................................................... Output Example Timer in Up/Down Mode .......................................................................... Capture/Compare TAxCCR0 Interrupt Flag .......................................................................... Timer_B Block Diagram ................................................................................................. Up Mode .................................................................................................................. Up Mode Flag Setting ................................................................................................... Continuous Mode ........................................................................................................ Continuous Mode Flag Setting ......................................................................................... Continuous Mode Time Intervals ...................................................................................... Up/Down Mode ........................................................................................................... Up/Down Mode Flag Setting............................................................................................ Output Unit in Up/Down Mode ......................................................................................... Capture Signal (SCS = 1) ............................................................................................... Capture Cycle ............................................................................................................ Output Example Timer in Up Mode ................................................................................. Output Example Timer in Continuous Mode ....................................................................... Output Example Timer in Up/Down Mode .......................................................................... Capture/Compare TBxCCR0 Interrupt Flag .......................................................................... Timer_D Block Diagram ................................................................................................. High Resolution Clock Generator ...................................................................................... Up Mode .................................................................................................................. Up Mode Flag Setting ...................................................................................................Continuous Mode Time IntervalsCopyright 20082011, Texas Instruments Incorporated

392 393 393 394 395 395 397 398 399 400 409 411 411 412 412 412 413 413 414 415 415 418 419 420 421 431 434 436 437

List of Figures


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17-5. 17-6. 17-7. 17-8. 17-9. 17-10. 17-11. 17-12. 17-13. 17-14. 17-15. 17-16. 17-17. 17-18. 17-19. 17-20. 17-21. 17-22. 17-23. 18-1. 18-2. 18-3. 18-4. 18-5. 20-1. 21-1. 22-1. 22-2. 23-1. 23-2. 23-3. 23-4. 23-5. 24-1. 25-1. 25-2. 25-3. 25-4. 25-5. 25-6. 25-7. 25-8. 25-9. 25-10. 25-11. 26-1. 26-2. 26-3. 26-4.

Continuous Mode ........................................................................................................ 437 Continuous Mode Flag Setting ......................................................................................... 437

...................................................................................... ............................................................. Up/Down Mode ........................................................................................................... Up/Down Mode Flag Setting............................................................................................ Output Unit in Up/Down Mode ......................................................................................... Controlling Rising and Falling Edge of PWM Output in Up Mode ................................................. Deadband Generation (TDxCMB = 1) ................................................................................. Capture Signal (SCS = 1) ............................................................................................... Single Capture Cycle .................................................................................................... Sequential Capture Events in Dual Capture Mode .................................................................. COV in Dual Capture Mode ............................................................................................ Output Example, Channel 1 Timer in Up Mode ................................................................... Output Example, Channel 1 - Timer in Up Mode With External Fault Signal .................................... Output Example - Timer in Up Mode with External Timer Clear Signal .......................................... Output Example Timer in Continuous M

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