msp4324x family technical reference manual

Preliminary Information

MSP432P4xx Family

Technical Reference Manual

Literature Number: SLAU356AMarch 2015Revised April 2015


Contents

Preface....................................................................................................................................... 391 Cortex-M4F Processor ........................................................................................................ 40

1.1 Introduction.................................................................................................................. 411.1.1 Block Diagram ..................................................................................................... 43

1.2 Overview..................................................................................................................... 441.2.1 Bus Interface ....................................................................................................... 441.2.2 Integrated Configurable Debug.................................................................................. 441.2.3 Cortex-M4F System Component Details ....................................................................... 45

1.3 Programming Model ....................................................................................................... 451.3.1 Processor Mode and Privilege Levels for Software Execution .............................................. 451.3.2 Stacks............................................................................................................... 451.3.3 Register Map....................................................................................................... 461.3.4 Register Descriptions ............................................................................................. 461.3.5 Exceptions and Interrupts ........................................................................................ 491.3.6 Data Types ......................................................................................................... 49

1.4 Memory Model .............................................................................................................. 491.4.1 Memory Regions, Types, and Attributes ....................................................................... 491.4.2 Memory System Ordering of Memory Accesses .............................................................. 501.4.3 Behavior of Memory Accesses .................................................................................. 501.4.4 Software Ordering of Memory Accesses ....................................................................... 501.4.5 Bit-Banding......................................................................................................... 511.4.6 Data Storage ....................................................................................................... 53

1.5 Exception Model............................................................................................................ 541.5.1 Exception States .................................................................................................. 541.5.2 Exception Types................................................................................................... 551.5.3 Exception Handlers ............................................................................................... 561.5.4 Vector Table ....................................................................................................... 561.5.5 Exception Priorities................................................................................................ 571.5.6 Interrupt Priority Grouping........................................................................................ 581.5.7 Level and Pulse Interrupts ....................................................................................... 581.5.8 Exception Entry and Return...................................................................................... 58

1.6 Fault Handling .............................................................................................................. 611.6.1 Fault Types......................................................................................................... 611.6.2 Fault Escalation and Hard Faults ............................................................................... 621.6.3 Fault Status Registers and Fault Address Registers ......................................................... 631.6.4 Lockup .............................................................................................................. 63

1.7 Power Management........................................................................................................ 631.8 Instruction Set Summary .................................................................................................. 63

2 Cortex-M4F Peripherals....................................................................................................... 692.1 Cortex-M4F Peripherals Introduction .................................................................................... 702.2 Functional Peripherals Description....................................................................................... 70

2.2.1 System Timer (SysTick) .......................................................................................... 702.2.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 712.2.3 System Control Block (SCB)..................................................................................... 72

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2.2.4 Memory Protection Unit (MPU) .................................................................................. 722.2.5 Floating-Point Unit (FPU)......................................................................................... 77

2.3 Debug Peripherals Description ........................................................................................... 802.3.1 FPB ................................................................................................................. 802.3.2 DWT................................................................................................................. 802.3.3 ITM .................................................................................................................. 812.3.4 TPIU................................................................................................................. 81

2.4 Functional Peripherals Register Map .................................................................................... 822.4.1 FPU Registers ..................................................................................................... 822.4.2 MPU Registers..................................................................................................... 882.4.3 NVIC Registers .................................................................................................... 982.4.4 SYSTICK Registers.............................................................................................. 1272.4.5 SCB Registers.................................................................................................... 1322.4.6 SCnSCB Registers .............................................................................................. 1672.4.7 COREDEBUG Registers........................................................................................ 170

2.5 Debug Peripherals Register Map ....................................................................................... 1772.5.1 FPB Registers .................................................................................................... 1772.5.2 DWT Registers ................................................................................................... 1882.5.3 ITM Registers .................................................................................................... 2142.5.4 TPIU Registers ................................................................................................... 238

3 Reset Controller (RSTCTL)................................................................................................. 2393.1 Introduction ................................................................................................................ 2403.2 Reset Classification....................................................................................................... 240

3.2.1 Class 0 : Power On/Off Reset (POR) Class.................................................................. 2403.2.2 Class 1 : Reboot Reset ......................................................................................... 2413.2.3 Class 2 : Hard Reset ............................................................................................ 2413.2.4 Class 3 : Soft Reset ............................................................................................. 242

3.3 RSTCTL Registers........................................................................................................ 2433.3.1 RSTCTL_RESET_REQ Register (offset = 00h) ............................................................ 2443.3.2 RSTCTL_HARDRESET_STAT Register (offset = 04h) .................................................... 2453.3.3 RSTCTL_HARDRESET_CLR Register (offset = 08h) ...................................................... 2463.3.4 RSTCTL_HARDRESET_SET Register (offset = 0Ch)...................................................... 2473.3.5 RSTCTL_SOFTRESET_STAT Register (offset = 10h) ..................................................... 2483.3.6 RSTCTL_SOFTRESET_CLR Register (offset = 14h) ...................................................... 2493.3.7 RSTCTL_SOFTRESET_SET Register (offset = 18h)....................................................... 2503.3.8 RSTCTL_PSSRESET_STAT Register (offset = 100h) ..................................................... 2513.3.9 RSTCTL_PSSRESET_CLR Register (offset = 104h)....................................................... 2513.3.10 RSTCTL_PCMRESET_STAT Register (offset = 108h).................................................... 2523.3.11 RSTCTL_PCMRESET_CLR Register (offset = 10Ch)..................................................... 2523.3.12 RSTCTL_PINRESET_STAT Register (offset = 110h) ..................................................... 2533.3.13 RSTCTL_PINRESET_CLR Register (offset = 114h)....................................................... 2533.3.14 RSTCTL_REBOOTRESET_STAT Register (offset = 118h) .............................................. 2543.3.15 RSTCTL_REBOOTRESET_CLR Register (offset = 11Ch) ............................................... 254

4 System Controller (SYSCTL) .............................................................................................. 2554.1 SYSCTL Introduction ..................................................................................................... 2564.2 Device Memory Configuration and Status ............................................................................. 256

4.2.1 Flash............................................................................................................... 2564.2.2 SRAM ............................................................................................................. 256

4.3 NMI Configuration ........................................................................................................ 2574.4 Watchdog Timer Reset Configuration.................................................................................. 2574.5 Clock Run or Stop Configuration ....................................................................................... 2574.6 Reset Status and Override Control..................................................................................... 2574.7 Device Security ........................................................................................................... 257

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4.7.1 Device Security Introduction.................................................................................... 2584.7.2 Device Security Components .................................................................................. 2584.7.3 JTAG and SWD Lock Based Security ........................................................................ 2584.7.4 IP Protection through Secure Memory Zones................................................................ 2584.7.5 Boot Overrides ................................................................................................... 2604.7.6 In-Field Updates ................................................................................................. 2664.7.7 Device Security and Boot Overrides User Considerations ................................................. 269

4.8 Device Descriptor Table ................................................................................................. 2704.8.1 TLV Descriptors .................................................................................................. 270

4.9 ARM Cortex-M4F ROM Table Based Part Number .................................................................. 2714.10 SYSCTL Registers........................................................................................................ 273

4.10.1 SYS_REBOOT_CTL Register (offset = 0000h) ............................................................ 2744.10.2 SYS_NMI_CTLSTAT Register (offset = 0004h) ........................................................... 2754.10.3 SYS_WDTRESET_CTL Register (offset = 0008h) ........................................................ 2764.10.4 SYS_PERIHALT_CTL Register (offset = 000Ch) ......................................................... 2774.10.5 SYS_SRAM_SIZE Register (offset = 0010h) .............................................................. 2784.10.6 SYS_SRAM_BANKEN Register (offset = 0014h) ......................................................... 2794.10.7 SYS_SRAM_BANKRET Register (offset = 0018h) ........................................................ 2804.10.8 SYS_FLASH_SIZE Register (offset = 0020h) .............................................................. 2814.10.9 SYS_DIO_GLTFLT_CTL Register (offset = 0030h) ....................................................... 2824.10.10 SYS_SECDATA_UNLOCK Register (offset = 0040h) ................................................... 2834.10.11 SYS_MASTER_UNLOCK Register (offset = 1000h) .................................................... 2844.10.12 SYS_BOOTOVER_REQ0 Register (offset = 1004h) ..................................................... 2854.10.13 SYS_BOOTOVER_REQ1 Register (offset = 1008h) ..................................................... 2864.10.14 SYS_BOOTOVER_ACK Register (offset = 100Ch) ..................................................... 2874.10.15 SYS_RESET_REQ Register (offset = 1010h) ............................................................ 2884.10.16 SYS_RESET_STATOVER Register (offset = 1014h) ................................................... 2894.10.17 SYS_SYSTEM_STAT Register (offset = 1020h) ......................................................... 290

5 Clock System (CS) ............................................................................................................ 2915.1 Clock System Introduction ............................................................................................... 2925.2 Clock System Operation ................................................................................................. 294

5.2.1 CS Module Features for Low-Power Applications ........................................................... 2945.2.2 LFXT Oscillator (Device Specific).............................................................................. 2945.2.3 HFXT Oscillator (Device Specific) ............................................................................. 2955.2.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ................................................ 2965.2.5 Internal Low-Power Low-Frequency Oscillator (REFO) .................................................... 2975.2.6 Module Oscillator (MODOSC).................................................................................. 2975.2.7 System Oscillator (SYSOSC) .................................................................................. 2985.2.8 Digitally Controlled Oscillator (DCO) .......................................................................... 2985.2.9 Module Clock Request System ................................................................................ 3005.2.10 CS Module Fail-Safe Operation............................................................................... 3015.2.11 Start-Up Counters .............................................................................................. 3035.2.12 Synchronization of Clock Signals............................................................................. 3035.2.13 Clock Status ..................................................................................................... 303

5.3 CS Registers .............................................................................................................. 3055.3.1 CSACC Register (offset = 00h) [reset = 0000_A596h] ..................................................... 3065.3.2 CSCTL0 Register (offset = 04h) [reset = 0001_0000h]..................................................... 3075.3.3 CSCTL1 Register (offset = 08h) [reset = 0000_0033h]..................................................... 3095.3.4 CSCTL2 Register (offset = 0Ch) [reset = 0007_0007h] .................................................... 3115.3.5 CSCTL3 Register (offset = 10h) [reset = 0000_00BBh] .................................................... 3135.3.6 CSCLKEN Register (offset = 30h) [reset = 0000_000Fh] .................................................. 3145.3.7 CSSTAT Register (offset = 34h) [reset = 0000_0003h] .................................................... 3155.3.8 CSIE Register (offset = 40h) [reset = 0000_0000h]......................................................... 317




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5.3.9 CSIFG Register (offset = 48h) [reset = 0000_0001h]....................................................... 3185.3.10 CSCLRIFG Register (offset = 50h) [reset = 0000_0000h] ................................................ 3195.3.11 CSSETIFG Register (offset = 58h) [reset = 0000_0000h] ................................................ 3205.3.12 CSDCOERCAL Register (offset=60h) [reset = 0100_0000h] ............................................ 321

6 Power Supply System (PSS) .............................................................................................. 3226.1 PSS Introduction .......................................................................................................... 3236.2 PSS Operation ............................................................................................................ 324

6.2.1 Supply Voltage Supervisor / Monitor .......................................................................... 3246.2.2 Supply Voltage Supervisor during Power-Up ................................................................ 3256.2.3 VCCDET .......................................................................................................... 3266.2.4 PSS Interrupts.................................................................................................... 326

6.3 PSS Registers............................................................................................................. 3276.3.1 PSSKEY Register (offset = 00h) [reset = 0000A596h] ..................................................... 3286.3.2 PSSCTL0 Register (offset = 04h) [reset = 00002000h]..................................................... 3296.3.3 PSSIE Register (offset = 34h) [reset = 0000h]............................................................... 3316.3.4 PSSIFG Register (offset = 38h) [reset = 0000h]............................................................. 3326.3.5 PSSCLRIFG Register (offset = 3Ch) [reset = 0000h]....................................................... 333

7 Power Control Manager (PCM) ........................................................................................... 3347.1 PCM Introduction ......................................................................................................... 3357.2 PCM Overview ............................................................................................................ 3357.3 Core Voltage Regulators................................................................................................. 336

7.3.1 DC-DC Regulator Care Abouts ................................................................................ 3367.4 Power Modes.............................................................................................................. 337

7.4.1 Active Modes (AM) .............................................................................................. 3377.4.2 LPM0 .............................................................................................................. 3377.4.3 LPM3 and LPM4 ................................................................................................. 3387.4.4 LPM3.5 and LPM4.5............................................................................................. 3387.4.5 Summary of Power Modes ..................................................................................... 338

7.5 Power Mode Transitions ................................................................................................. 3407.5.1 Active Mode Transitions ........................................................................................ 3417.5.2 Transitions To and From LPM0 ................................................................................ 3427.5.3 Transitions To and From LPM3 and LPM4................................................................... 3437.5.4 Transitions To and From LPM3.5 and LPM4.5 .............................................................. 343

7.6 Changing Core Voltages................................................................................................. 3447.6.1 Increasing VCORE for Higher MCLK Frequencies ............................................................. 3447.6.2 Decreasing VCORE for Power Optimization .................................................................... 344

7.7 ARM Cortex Processor Sleep Modes .................................................................................. 3457.7.1 WFI, Wait For Interrupt.......................................................................................... 3457.7.2 WFE, Wait For Event............................................................................................ 3457.7.3 Sleep On Exit..................................................................................................... 3457.7.4 SLEEPDEEP ..................................................................................................... 346

7.8 Changing Power Modes ................................................................................................. 3467.9 Power Mode Selection ................................................................................................... 3467.10 Power Mode Transition Checks......................................................................................... 3477.11 Power Mode Clock Checks.............................................................................................. 3477.12 Clock Configuration Changes ........................................................................................... 3487.13 Changing Active Modes.................................................................................................. 348

7.13.1 DC-DC Error Checking......................................................................................... 3497.14 Entering LPM0 Modes ................................................................................................... 3507.15 Exiting LPM0 Modes ..................................................................................................... 3507.16 Entering LPM3 and LPM4 Modes ...................................................................................... 3507.17 Exiting LPM3 and LPM4 Modes ........................................................................................ 3517.18 Entering LPM3.5 and LPM4.5 Modes.................................................................................. 351




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7.19 Exiting LPM3.5 and LPM4.5 Modes.................................................................................... 3527.20 Supply Voltage Supervisor/Monitor and Power Modes .............................................................. 3537.21 Low-Power Reset ......................................................................................................... 3547.22 Power Requests During Debug ......................................................................................... 354

7.22.1 Debug During Active Modes .................................................................................. 3547.22.2 Debug During LPM0 Modes................................................................................... 3547.22.3 Debug During LPM3, LPM4, and LPMx.5 Modes. ......................................................... 355

7.23 Wake-up Sources from Low Power Modes ........................................................................... 3557.24 PCM Registers ............................................................................................................ 356

7.24.1 PCMCTL0 Register (offset = 00h) [reset = A5960000h]................................................... 3577.24.2 PCMCTL1 Register (offset = 04h) [reset = A5960000h]................................................... 3597.24.3 PCMIE Register (offset = 08h) [reset = 00000000h] ....................................................... 3617.24.4 PCMIFG Register (offset = 0Ch) [reset = 00000000h] .................................................... 3627.24.5 PCMCLRIFG Register (offset = 10h) [reset = 00000000h]................................................ 363

8 Flash Controller (FLCTL) .................................................................................................. 3648.1 Introduction ................................................................................................................ 3658.2 Flash Memory Organization ............................................................................................. 3658.3 Flash Controller Clocking ................................................................................................ 365

8.3.1 Bus Interface Clock.............................................................................................. 3658.3.2 Timing Clock...................................................................................................... 365

8.4 Flash Controller Address Mapping ..................................................................................... 3668.5 Flash Controller Access Privileges ..................................................................................... 3668.6 Flash Read Modes and Features....................................................................................... 366

8.6.1 Flash Read Modes............................................................................................... 3668.6.2 Flash Read Timing Control ..................................................................................... 3678.6.3 Read Buffering ................................................................................................... 3688.6.4 Burst Read/Compare Feature.................................................................................. 368

8.7 Flash Program Modes and Features ................................................................................... 3708.7.1 Program Modes .................................................................................................. 3708.7.2 Burst Program Feature.......................................................................................... 3728.7.3 Program Protection Features................................................................................... 372

8.8 Flash Erase Modes and Features ...................................................................................... 3728.8.1 Sector Erase Mode .............................................................................................. 3728.8.2 Mass Erase Mode ............................................................................................... 3728.8.3 Erase Protection Features ...................................................................................... 372

8.9 Flash Write/Erase Protection ............................................................................................ 3738.10 Recommended Settings and Flow for Program and Erase Operations ........................................... 3738.11 Application Benchmarking Features.................................................................................... 3748.12 Handling and Ordering of Flash operations ........................................................................... 374

8.12.1 Out of Order Processing of Application initiated Read and Write Commands ......................... 3748.12.2 Simultaneous Read and Write conditions ................................................................... 374

8.13 Interrupts ................................................................................................................... 3758.14 Support for Low Frequency Active and Low Frequency LPM0 Modes ............................................ 3758.15 Flash Functionality during Resets ...................................................................................... 375

8.15.1 Soft Reset........................................................................................................ 3758.15.2 Hard Reset ...................................................................................................... 3758.15.3 POR Reset ...................................................................................................... 376

8.16 FLCTL Registers .......................................................................................................... 3778.16.1 FLCTL_POWER_STAT Register (offset = 0000h) ........................................................ 3798.16.2 FLCTL_BANK0_RDCTL Register (offset = 0010h) ........................................................ 3808.16.3 FLCTL_BANK1_RDCTL Register (offset = 0014h) ........................................................ 3828.16.4 FLCTL_RDBRST_CTLSTAT Register (offset = 0020h) .................................................. 3848.16.5 FLCTL_RDBRST_STARTADDR Register (offset = 0024h) .............................................. 385




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8.16.6 FLCTL_RDBRST_LEN Register (offset = 0028h) ......................................................... 3868.16.7 FLCTL_RDBRST_FAILADDR Register (offset = 003Ch) ................................................. 3878.16.8 FLCTL_RDBRST_FAILCNT Register (offset = 0040h) ................................................... 3888.16.9 FLCTL_PRG_CTLSTAT Register (offset = 0050h) ........................................................ 3898.16.10 FLCTL_PRGBRST_CTLSTAT Register (offset = 0054h) ............................................... 3908.16.11 FLCTL_PRGBRST_STARTADDR Register (offset = 0058h) .......................................... 3928.16.12 FLCTL_PRGBRST_DATA0_0 Register (offset = 060h) ................................................. 3938.16.13 FLCTL_PRGBRST_DATA0_1 Register (offset = 064h) ................................................. 3938.16.14 FLCTL_PRGBRST_DATA0_2 Register (offset = 068h) ................................................. 3948.16.15 FLCTL_PRGBRST_DATA0_3 Register (offset = 06Ch) ................................................ 3948.16.16 FLCTL_PRGBRST_DATA1_0 Register (offset = 070h) ................................................. 3958.16.17 FLCTL_PRGBRST_DATA1_1 Register (offset = 074h) ................................................. 3958.16.18 FLCTL_PRGBRST_DATA1_2 Register (offset = 078h) ................................................. 3968.16.19 FLCTL_PRGBRST_DATA1_3 Register (offset = 07Ch) ................................................ 3968.16.20 FLCTL_PRGBRST_DATA2_0 Register (offset = 080h) ................................................. 3978.16.21 FLCTL_PRGBRST_DATA2_1 Register (offset = 084h) ................................................. 3978.16.22 FLCTL_PRGBRST_DATA2_2 Register (offset = 088h) ................................................. 3988.16.23 FLCTL_PRGBRST_DATA2_3 Register (offset = 08Ch) ................................................ 3988.16.24 FLCTL_PRGBRST_DATA3_0 Register (offset = 090h) ................................................. 3998.16.25 FLCTL_PRGBRST_DATA3_1 Register (offset = 094h) ................................................. 3998.16.26 FLCTL_PRGBRST_DATA3_2 Register (offset = 098h) ................................................. 4008.16.27 FLCTL_PRGBRST_DATA3_3 Register (offset = 09Ch) ................................................ 4008.16.28 FLCTL_ERASE_CTLSTAT Register (offset = 00A0h) .................................................. 4018.16.29 FLCTL_ERASE_SECTADDR Register (offset = 00A4h) ................................................ 4028.16.30 FLCTL_BANK0_INFO_WEPROT Register (offset = 00B0h) ........................................... 4038.16.31 FLCTL_BANK0_MAIN_WEPROT Register (offset = 00B4h) ........................................... 4048.16.32 FLCTL_BANK1_INFO_WEPROT Register (offset = 00C0h) ........................................... 4068.16.33 FLCTL_BANK1_MAIN_WEPROT Register (offset = 00C4h) ........................................... 4078.16.34 FLCTL_BMRK_CTLSTAT Register (offset = 00D0h) .................................................... 4098.16.35 FLCTL_BMRK_IFETCH Register (offset = 00D4h) ...................................................... 4108.16.36 FLCTL_BMRK_DREAD Register (offset = 00D8h) ...................................................... 4118.16.37 FLCTL_BMRK_CMP Register (offset = 00DCh) ......................................................... 4128.16.38 FLCTL_IFG Register (offset = 0F0h) ...................................................................... 4138.16.39 FLCTL_IE Register (offset = 0F4h) ........................................................................ 4148.16.40 FLCTL_CLRIFG Register (offset = 0F8h) ................................................................. 4158.16.41 FLCTL_SETIFG Register (offset = 0FCh) ................................................................. 4168.16.42 FLCTL_READ_TIMCTL Register (offset = 0100h) ....................................................... 4178.16.43 FLCTL_READMARGIN_TIMCTL Register (offset = 0104h) ............................................ 4188.16.44 FLCTL_PRGVER_TIMCTL Register (offset = 0108h) ................................................... 4198.16.45 FLCTL_ERSVER_TIMCTL Register (offset = 010Ch) ................................................... 4208.16.46 FLCTL_LKGVER_TIMCTL Register (offset = 0110h) ................................................... 4218.16.47 FLCTL_PROGRAM_TIMCTL Register (offset = 0114h) ................................................ 4228.16.48 FLCTL_ERASE_TIMCTL Register (offset = 0118h) ..................................................... 4238.16.49 FLCTL_MASSERASE_TIMCTL Register (offset = 011Ch) ............................................. 4248.16.50 FLCTL_BURSTPRG_TIMCTL Register (offset = 0120h) ............................................... 425

9 DMA ................................................................................................................................ 4269.1 DMA Introduction ......................................................................................................... 4279.2 DMA Operation............................................................................................................ 428

9.2.1 APB Slave Interface ............................................................................................. 4289.2.2 AHB Master Interface ........................................................................................... 4289.2.3 DMA Control Interface .......................................................................................... 4309.2.4 Channel Control Data Structure ............................................................................... 4449.2.5 Peripheral Triggers .............................................................................................. 451




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9.2.6 Interrupts .......................................................................................................... 4519.3 DMA Registers ............................................................................................................ 452

9.3.1 DMA_DEVICE_CFG Register (offset = 000h) .............................................................. 4539.3.2 DMA_SW_CHTRIG Register (offset = 004h) ................................................................ 4549.3.3 DMA_CHn_SRCCFG Register (offset = 010h + 4h*n, n = 0 through NUM_DMA_CHANNELS) .... 4569.3.4 DMA_INT1_SRCCFG Register (offset = 100h) ............................................................. 4579.3.5 DMA_INT2_SRCCFG Register (offset = 104h) ............................................................. 4589.3.6 DMA_INT3_SRCCFG Register (offset = 108h) ............................................................. 4599.3.7 DMA_INT0_SRCFLG Register (offset = 110h) ............................................................. 4609.3.8 DMA_INT0_CLRFLG Register (offset = 114h) .............................................................. 4619.3.9 DMA_STAT Register (offset = 1000h) [reset = 0h].......................................................... 4639.3.10 DMA_CFG Register (offset = 1004h) [reset = 0h].......................................................... 4649.3.11 DMA_CTLBASE Register (offset = 1008h) [reset = 0h] ................................................... 4659.3.12 DMA_ALTBASE Register (offset = 100Ch) [reset = 0h] ................................................... 4669.3.13 DMA_WAITSTAT Register (offset = 1010h) [reset = 0h] .................................................. 4679.3.14 DMA_SWREQ Register (offset = 1014h) [reset = 0h] ..................................................... 4689.3.15 DMA_USEBURSTSET Register (offset = 1018h) [reset = 0h]............................................ 4699.3.16 DMA_USEBURSTCLR Register (offset = 101Ch) [reset = 0h] ........................................... 4709.3.17 DMA_REQMASKSET Register (offset = 1020h) [reset = 0h]............................................. 4719.3.18 DMA_REQMASKCLR Register (offset = 1024h) [reset = 0h]............................................. 4729.3.19 DMA_ENASET Register (offset = 1028h) [reset = 0h]..................................................... 4739.3.20 DMA_ENACLR Register (offset = 102Ch) [reset = 0h] .................................................... 4749.3.21 DMA_ALTSET Register (offset = 1030h) [reset = 0h] ..................................................... 4759.3.22 DMA_ALTCLR Register (offset = 1034h) [reset = 0h] ..................................................... 4769.3.23 DMA_PRIOSET Register (offset = 1038h) [reset = 0h].................................................... 4779.3.24 DMA_PRIOCLR Register (offset = 103Ch) [reset = 0h] ................................................... 4789.3.25 DMA_ERRCLR Register (offset = 104Ch) [reset = 0h] .................................................... 479

10 Digital I/O......................................................................................................................... 48010.1 Digital I/O Introduction ................................................................................................... 48110.2 Digital I/O Operation...................................................................................................... 482

10.2.1 Input Registers (PxIN).......................................................................................... 48210.2.2 Output Registers (PxOUT) .................................................................................... 48210.2.3 Direction Registers (PxDIR) ................................................................................... 48210.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) .................................................. 48210.2.5 Output Drive Strength Selection Registers (PxDS) ........................................................ 48310.2.6 Function Select Registers (PxSEL0, PxSEL1).............................................................. 48310.2.7 Port Interrupts ................................................................................................... 484

10.3 I/O Configuration .......................................................................................................... 48510.3.1 Configuration After Reset...................................................................................... 48510.3.2 Configuration of Unused Port Pins ........................................................................... 48510.3.3 Configuration of I/Os for Ultra-Low-Power Modes of Operation .......................................... 485

10.4 Digital I/O Registers ...................................................................................................... 48710.4.1 PxIV Register.................................................................................................... 49910.4.2 PxIN Register ................................................................................................... 50010.4.3 PxOUT Register ................................................................................................ 50010.4.4 PxDIR Register ................................................................................................. 50010.4.5 PxREN Register ................................................................................................ 50110.4.6 PxDS Register .................................................................................................. 50110.4.7 PxSEL0 Register ............................................................................................... 50110.4.8 PxSEL1 Register ............................................................................................... 50210.4.9 PxSELC Register .............................................................................................. 50210.4.10 PxIES Register ................................................................................................ 50210.4.11 PxIE Register .................................................................................................. 503




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10.4.12 PxIFG Register ............................................................................................... 50311 Port Mapping Controller (PMAP)......................................................................................... 504

11.1 Port Mapping Controller Introduction................................................................................... 50511.2 Port Mapping Controller Operation ..................................................................................... 505

11.2.1 Access ........................................................................................................... 50511.2.2 Mapping .......................................................................................................... 505

11.3 PMAP Registers .......................................................................................................... 50811.3.1 PMAPKEYID Register (offset = 00h) [reset = 96A5h] ..................................................... 51011.3.2 PMAPCTL Register (offset = 02h) [reset = 0001h]......................................................... 51011.3.3 P1MAP0 to P1MAP7 Register (offset = 08h to 0Fh) [reset = Device dependent] ..................... 51011.3.4 P2MAP0 to P2MAP7 Register (offset = 10h to 17h) [reset = Device dependent]...................... 51111.3.5 P3MAP0 to P3MAP7 Register (offset = 18h to 1Fh) [reset = Device dependent] ..................... 51111.3.6 P4MAP0 to P4MAP7 Register (offset = 20h to 27h) [reset = Device dependent]...................... 51111.3.7 P5MAP0 to P5MAP7 Register (offset = 28h to 2Fh) [reset = Device dependent] ..................... 51111.3.8 P6MAP0 to P6MAP7 Register (offset = 30h to 37h) [reset = Device dependent]...................... 51211.3.9 P7MAP0 to P7MAP7 Register (offset = 38h to 3Fh) [reset = Device dependent] ..................... 51211.3.10 PxMAPyz Register [reset = Device dependent] ........................................................... 512

12 Capacitive Touch IO (CAPTIO)............................................................................................ 51412.1 Capacitive Touch IO Introduction ....................................................................................... 51512.2 Capacitive Touch IO Operation ......................................................................................... 51612.3 CapTouch Registers...................................................................................................... 517

12.3.1 CAPTIOxCTL Register (offset = 0Eh) [reset = 0000h]..................................................... 51813 CRC32 Module.................................................................................................................. 519

13.1 Cyclic Redundancy Check (CRC32) Module Introduction........................................................... 52013.2 CRC Checksum Generation............................................................................................. 520

13.2.1 CRC Standard and Bit Order.................................................................................. 52113.2.2 CRC Implementation ........................................................................................... 521

13.3 CRC32 Registers ......................................................................................................... 52214 AES256 Accelerator .......................................................................................................... 533

14.1 AES Accelerator Introduction............................................................................................ 53414.2 AES Accelerator Operation.............................................................................................. 535

14.2.1 Load the Key (128-Bit, 192-Bit, or 256-Bit Keylength)..................................................... 53614.2.2 Load the Data (128-Bit State) ................................................................................. 53614.2.3 Read the Data (128-Bit State) ................................................................................ 53714.2.4 Trigger an Encryption or Decryption ......................................................................... 53714.2.5 Encryption ....................................................................................................... 53814.2.6 Decryption ....................................................................................................... 53814.2.7 Decryption Key Generation.................................................................................... 53914.2.8 AES Key Buffer ................................................................................................. 54014.2.9 Using the AES Accelerator With Low-Power Modes....................................................... 54114.2.10 AES Accelerator Interrupts................................................................................... 54114.2.11 DMA Operation and Implementing Block Cipher Modes................................................. 541

14.3 AES256 Registers ........................................................................................................ 55214.3.1 AESACTL0 Register............................................................................................ 55314.3.2 AESACTL1 Register............................................................................................ 55514.3.3 AESASTAT Register ........................................................................................... 55614.3.4 AESAKEY Register............................................................................................. 55714.3.5 AESADIN Register ............................................................................................. 55814.3.6 AESADOUT Register .......................................................................................... 55914.3.7 AESAXDIN Register............................................................................................ 56014.3.8 AESAXIN Register.............................................................................................. 561

15 Watchdog Timer (WDT_A).................................................................................................. 562




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15.1 WDT_A Introduction ...................................................................................................... 56315.2 WDT_A Operation ........................................................................................................ 565

15.2.1 Watchdog Timer Counter (WDTCNT)........................................................................ 56515.2.2 Watchdog Mode ................................................................................................ 56515.2.3 Interval Timer Mode ............................................................................................ 56515.2.4 Watchdog Related Interrupts and Flags ..................................................................... 56615.2.5 Clock Sources of the WDT_A ................................................................................. 56615.2.6 WDT_A Operation in Different Device Power Modes...................................................... 566

15.3 WDT_A Registers......................................................................................................... 56815.3.1 WDTCTL Register .............................................................................................. 569

16 Timer32 ........................................................................................................................... 57016.1 Introduction ................................................................................................................ 57116.2 Functional Description.................................................................................................... 57116.3 Operation .................................................................................................................. 57116.4 Interrupt Generation ...................................................................................................... 57216.5 Timer32 Registers ........................................................................................................ 573

16.5.1 T32LOAD1 Register (offset = 00h) [reset = 0h] ............................................................ 57416.5.2 T32VALUE1 Register (offset = 04h) [reset = FFFFFFFFh] ............................................... 57516.5.3 T32CONTROL1 Register (offset = 08h) [reset = 20h] ..................................................... 57616.5.4 T32INTCLR1 Register (offset = 0Ch) [reset = undefined]................................................. 57716.5.5 T32RIS1 Register (offset = 10h) [reset = 0h] ............................................................... 57816.5.6 T32MIS1 Register (offset = 14h) [reset = 0h] ............................................................... 57916.5.7 T32BGLOAD1 Register (offset = 18h) [reset = 0h]......................................................... 58016.5.8 T32LOAD2 Register (offset = 20h) [reset = 0h] ............................................................ 58116.5.9 T32VALUE2 Register (offset = 24h) [reset = FFFFFFFFh] ............................................... 58216.5.10 T32CONTROL2 Register (offset = 28h) [reset = 20h].................................................... 58316.5.11 T32INTCLR2 Register (offset = 2Ch) [reset = undefined] ............................................... 58416.5.12 T32RIS2 Register (offset = 30h) [reset = 0h].............................................................. 58516.5.13 T32MIS2 Register (offset = 34h) [reset = 0h] ............................................................. 58616.5.14 T32BGLOAD2 Register (offset = 38h) [reset = 0h] ....................................................... 587

17 Timer_A........................................................................................................................... 58817.1 Timer_A Introduction ..................................................................................................... 58917.2 Timer_A Operation ....................................................................................................... 591

17.2.1 16-Bit Timer Counter ........................................................................................... 59117.2.2 Starting the Timer............................................................................................... 59117.2.3 Timer Mode Control ............................................................................................ 59217.2.4 Capture/Compare Blocks ...................................................................................... 59517.2.5 Output Unit ...................................................................................................... 59717.2.6 Timer_A Interrupts.............................................................................................. 601

17.3 Timer_A Registers ........................................................................................................ 60217.3.1 TAxCTL Register ............................................................................................... 60317.3.2 TAxR Register................................................................................................... 60417.3.3 TAxCCTL0 to TAxCCTL6 Register........................................................................... 60517.3.4 TAxCCR0 to TAxCCR6 Register ............................................................................ 60717.3.5 TAxIV Register .................................................................................................. 60717.3.6 TAxEX0 Register ............................................................................................... 608

18 Real-Time Clock (RTC_C) .................................................................................................. 60918.1 RTC_C Introduction ...................................................................................................... 61018.2 RTC_C Operation......................................................................................................... 612

18.2.1 Calendar Mode.................................................................................................. 61218.2.2 Real-Time Clock and Prescale Dividers .................................................................... 61218.2.3 Real-Time Clock Alarm Function ............................................................................ 61218.2.4 Real-Time Clock Protection ................................................................................... 613




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18.2.5 Reading or Writing Real-Time Clock Registers ............................................................ 61318.2.6 Real-Time Clock Interrupts .................................................................................... 61418.2.7 Real-Time Clock Calibration for Crystal Offset Error....................................................... 61518.2.8 Real-Time Clock Compensation for Crystal Temperature Drift ........................................... 61518.2.9 Real-Time Clock Operation in Low-Power Modes ......................................................... 618

18.3 RTC_C Registers ......................................................................................................... 61918.3.1 RTCCTL0_L Register .......................................................................................... 62118.3.2 RTCCTL0_H Register.......................................................................................... 62218.3.3 RTCCTL1 Register ............................................................................................. 62318.3.4 RTCCTL3 Register ............................................................................................. 62418.3.5 RTCOCAL Register ............................................................................................ 62518.3.6 RTCTCMP Register ............................................................................................ 62618.3.7 RTCSEC Register Hexadecimal Format .................................................................. 62718.3.8 RTCSEC Register BCD Format ............................................................................ 62718.3.9 RTCMIN Register Hexadecimal Format................................................................... 62818.3.10 RTCMIN Register BCD Format ........................................................................... 62818.3.11 RTCHOUR Register Hexadecimal Format .............................................................. 62918.3.12 RTCHOUR Register BCD Format ........................................................................ 62918.3.13 RTCDOW Register ........................................................................................... 63018.3.14 RTCDAY Register Hexadecimal Format................................................................. 63018.3.15 RTCDAY Register BCD Format........................................................................... 63018.3.16 RTCMON Register Hexadecimal Format ................................................................ 63118.3.17 RTCMON Register BCD Format .......................................................................... 63118.3.18 RTCYEAR Register Hexadecimal Format ............................................................... 63218.3.19 RTCYEAR Register BCD Format......................................................................... 63218.3.20 RTCAMIN Register Hexadecimal Format ............................................................... 63318.3.21 RTCAMIN Register BCD Format ......................................................................... 63318.3.22 RTCAHOUR Register Hexadecimal Format ............................................................ 63418.3.23 RTCAHOUR Register BCD Format ...................................................................... 63418.3.24 RTCADOW Register Calendar Mode .................................................................... 63518.3.25 RTCADAY Register Hexadecimal Format ............................................................... 63518.3.26 RTCADAY Register BCD Format......................................................................... 63518.3.27 RTCPS0CTL Register ........................................................................................ 63618.3.28 RTCPS1CTL Register ........................................................................................ 63718.3.29 RTCPS0 Register ............................................................................................. 63818.3.30 RTCPS1 Register ............................................................................................. 63818.3.31 RTCIV Register................................................................................................ 63918.3.32 RTCBIN2BCD Register....................................................................................... 64018.3.33 RTCBCD2BIN Register....................................................................................... 640

19 Reference Module (REF_A) ................................................................................................ 64119.1 REF_A Introduction....................................................................................................... 64219.2 Principle of Operation .................................................................................................... 643

19.2.1 Low-Power Operation .......................................................................................... 64319.2.2 Reference System Requests.................................................................................. 643

19.3 REF_A Registers ......................................................................................................... 64519.3.1 REFCTL0 Register (offset = 00h) [reset = 0008h] ......................................................... 646

20 ADC14 ............................................................................................................................. 64820.1 ADC14 Introduction....................................................................................................... 64920.2 ADC14 Operation ......................................................................................................... 650

20.2.1 14-Bit ADC Core ................................................................................................ 65120.2.2 ADC14 Inputs and Multiplexer ................................................................................ 65120.2.3 Voltage References ............................................................................................ 65220.2.4 Auto Power Down .............................................................................................. 652




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20.2.5 Power Modes.................................................................................................... 65220.2.6 Sample and Conversion Timing .............................................................................. 65220.2.7 Conversion Memory ............................................................................................ 65420.2.8 ADC14 Conversion Modes .................................................................................... 65520.2.9 Window Comparator............................................................................................ 66020.2.10 Using the Integrated Temperature Sensor................................................................. 66220.2.11 ADC14 Grounding and Noise Considerations............................................................. 66320.2.12 ADC14 Interrupts.............................................................................................. 664

20.3 ADC14 Registers ......................................................................................................... 66520.3.1 ADC14CTL0 Register (offset = 00h) [reset = 00000000h] ................................................ 66620.3.2 ADC14CTL1 Register (offset = 04h) [reset = 00000030h] ................................................ 66920.3.3 ADC14LO0 Register (offset = 08h) [reset = 00000000h].................................................. 67120.3.4 ADC14HI0 Register (offset = 0Ch) [reset = 00003FFFh] ................................................. 67220.3.5 ADC14LO1 Register (offset = 10h) [reset = 00000000h].................................................. 67320.3.6 ADC14HI1 Register (offset = 14h) [reset = 00003FFFh] .................................................. 67420.3.7 ADC14MCTL0 to ADC14MCTL31 Register (offset = 018h to 094h) [reset = 00000000h]............ 67520.3.8 ADC14MEM0 to ADC14MEM31 Register (offset = 098h to 104h) [reset = Undefined] ............... 67720.3.9 ADC14IER0 Register (offset = 13Ch) [reset = 00000000h]............................................... 67820.3.10 ADC14IER1 Register (offset = 140h) [reset = 00000000h].............................................. 68120.3.11 ADC14IFGR0 Register (offset = 144h) [reset = 00000000h]............................................ 68220.3.12 ADC14IFGR1 Register (offset = 148h) [reset = 00000000h]............................................ 68620.3.13 ADC14CLRIFGR0 Register (offset = 14Ch) [reset = 00000000h] ...................................... 68720.3.14 ADC14CLRIFGR1 Register (offset = 150h) [reset = 00000000h] ...................................... 69020.3.15 ADC14IV Register (offset = 154h) [reset = 00000000h] ................................................. 691

21 Comparator E Module (COMP_E) ........................................................................................ 69321.1 COMP_E Introduction .................................................................................................... 69421.2 COMP_E Operation ...................................................................................................... 695

21.2.1 Comparator ...................................................................................................... 69521.2.2 Analog Input Switches ......................................................................................... 69521.2.3 Port Logic ........................................................................................................ 69521.2.4 Input Short Switch .............................................................................................. 69521.2.5 Output Filter ..................................................................................................... 69621.2.6 Reference Voltage Generator ................................................................................. 69721.2.7 Comparator, Port Disable Register CEPD .................................................................. 69821.2.8 Comparator Interrupts.......................................................................................... 69821.2.9 Comparator Used to Measure Resistive Elements......................................................... 698

21.3 COMP_E Registers....................................................................................................... 70121.3.1 CExCTL0 Register (offset = 00h) [reset = 0000h].......................................................... 70221.3.2 CExCTL1 Register (offset = 02h) [reset = 0000h].......................................................... 70321.3.3 CExCTL2 Register (offset = 04h) [reset = 0000h].......................................................... 70421.3.4 CExCTL3 Register (offset = 06h) [reset = 0000h].......................................................... 70521.3.5 CExINT Register (offset = 0Ch) [reset = 0000h]............................................................ 70721.3.6 CExIV Register (offset = 0Eh) [reset = 0000h] ............................................................. 708

22 Enhanced Universal Serial Communication Interface (eUSCI) UART Mode............................ 70922.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview .................................. 71022.2 eUSCI_A Introduction UART Mode .................................................................................. 71022.3 eUSCI_A Operation UART Mode .................................................................................... 712

22.3.1 eUSCI_A Initialization and Reset ............................................................................. 71222.3.2 Character Format ............................................................................................... 71222.3.3 Asynchronous Communication Format ...................................................................... 71222.3.4 Automatic Baud-Rate Detection .............................................................................. 71522.3.5 IrDA Encoding and Decoding ................................................................................. 71622.3.6 Automatic Error Detection ..................................................................................... 717




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22.3.7 eUSCI_A Receive Enable ..................................................................................... 71822.3.8 eUSCI_A Transmit Enable .................................................................................... 71822.3.9 UART Baud-Rate Generation ................................................................................. 71922.3.10 Setting a Baud Rate .......................................................................................... 72122.3.11 Transmit Bit Timing - Error calculation ..................................................................... 72222.3.12 Receive Bit Timing Error Calculation ..................................................................... 72222.3.13 Typical Baud Rates and Errors.............................................................................. 72322.3.14 Using the eUSCI_A Module in UART Mode With Low-Power Modes ................................. 72522.3.15 eUSCI_A Interrupts ........................................................................................... 725

22.4 eUSCI_A UART Registers............................................................................................... 72722.4.1 UCAxCTLW0 Register ......................................................................................... 72822.4.2 UCAxCTLW1 Register ......................................................................................... 72922.4.3 UCAxBRW Register ............................................................................................ 73022.4.4 UCAxMCTLW Register ........................................................................................ 73022.4.5 UCAxSTATW Register ......................................................................................... 73122.4.6 UCAxRXBUF Register ......................................................................................... 73222.4.7 UCAxTXBUF Register ......................................................................................... 73222.4.8 UCAxABCTL Register.......................................................................................... 73322.4.9 UCAxIRCTL Register........................................................................................... 73422.4.10 UCAxIE Register .............................................................................................. 73522.4.11 UCAxIFG Register ............................................................................................ 73622.4.12 UCAxIV Register .............................................................................................. 737

23 Enhanced Universal Serial Communication Interface (eUSCI) SPI Mode ............................... 73823.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview ....................... 73923.2 eUSCI Introduction SPI Mode ........................................................................................ 73923.3 eUSCI Operation SPI Mode........................................................................................... 741

23.3.1 eUSCI Initialization and Reset ................................................................................ 74123.3.2 Character Format ............................................................................................... 74223.3.3 Master Mode .................................................................................................... 74223.3.4 Slave Mode ...................................................................................................... 74323.3.5 SPI Enable....................................................................................................... 74423.3.6 Serial Clock Control ............................................................................................ 74423.3.7 Using the SPI Mode With Low-Power Modes............................................................... 74523.3.8 SPI Interrupts.................................................................................................... 745

23.4 eUSCI_A SPI Registers.................................................................................................. 74723.4.1 UCAxCTLW0 Register ......................................................................................... 74823.4.2 UCAxBRW Register ............................................................................................ 75023.4.3 UCAxSTATW Register ......................................................................................... 75123.4.4 UCAxRXBUF Register ......................................................................................... 75223.4.5 UCAxTXBUF Register ......................................................................................... 75323.4.6 UCAxIE Register................................................................................................ 75423.4.7 UCAxIFG Register.............................................................................................. 75523.4.8 UCAxIV Register................................................................................................ 756

23.5 eUSCI_B SPI Registers.................................................................................................. 75723.5.1 UCBxCTLW0 Register ......................................................................................... 75823.5.2 UCBxBRW Register ............................................................................................ 76023.5.3 UCBxSTATW Register ......................................................................................... 76023.5.4 UCBxRXBUF Register ......................................................................................... 76123.5.5 UCBxTXBUF Register ......................................................................................... 76123.5.6 UCBxIE Register ............................................................................................... 76223.5.7 UCBxIFG Register.............................................................................................. 76223.5.8 UCBxIV Register................................................................................................ 763

24 Enhanced Universal Serial Communication Interface (eUSCI) I2C Mode ................................ 76413SLAU356AMarch 2015Revised April 2015 Contents

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24.0.9 Glitch Filtering ................................................................................................... 77924.0.10 Byte Counter .................................................................................................. 78024.0.11 Multiple Slave Addresses .................................................................................... 781

24.1 eUSCI_B I2C Registers .................................................................................................. 78424.1.1 UCBxCTLW0 Register ......................................................................................... 78524.1.2 UCBxCTLW1 Register ......................................................................................... 78724.1.3 UCBxBRW Register ............................................................................................ 78924.1.4 UCBxSTATW.................................................................................................... 78924.1.5 UCBxTBCNT Register ......................................................................................... 79024.1.6 UCBxRXBUF Register ......................................................................................... 79124.1.7 UCBxTXBUF .................................................................................................... 79124.1.8 UCBxI2COA0 Register......................................................................................... 79224.1.9 UCBxI2COA1 Register......................................................................................... 79324.1.10 UCBxI2COA2 Register ....................................................................................... 79324.1.11 UCBxI2COA3 Register ....................................................................................... 79424.1.12 UCBxADDRX Register ....................................................................................... 79424.1.13 UCBxADDMASK Register ................................................................................... 79524.1.14 UCBxI2CSA Register ......................................................................................... 79524.1.15 UCBxIE Register .............................................................................................. 79624.1.16 UCBxIFG Register ............................................................................................ 79824.1.17 UCBxIV Register .............................................................................................. 800

Revision History ........................................................................................................................ 801




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List of Figures1-1. CPU Block Diagram........................................................................................................ 431-2. Cortex-M4F Register Set .................................................................................................. 461-3. Bit-Band Mapping .......................................................................................................... 531-4. Data Storage ................................................................................................................ 541-5. Vector Table ................................................................................................................ 571-6. Exception Stack Frame.................................................................................................... 602-1. SRD Use Example ......................................................................................................... 752-2. FPU Register Bank......................................................................................................... 782-3. TPIU Block Diagram ....................................................................................................... 812-4. FPCCR Register............................................................................................................ 832-5. FPCAR Register............................................................................................................ 842-6. FPDSCR Register .......................................................................................................... 852-7. MVFR0 Register............................................................................................................ 862-8. MVFR1 Register............................................................................................................ 872-9. TYPE Register .............................................................................................................. 892-10. CTRL Register .............................................................................................................. 902-11. RNR Register ............................................................................................................... 912-12. RBAR Register ............................................................................................................. 922-13. RASR Register ............................................................................................................. 932-14. RBAR_A1 Register......................................................................................................... 952-15. RASR_A1 Register......................................................................................................... 952-16. RBAR_A2 Register......................................................................................................... 962-17. RASR_A2 Register......................................................................................................... 962-18. RBAR_A3 Register......................................................................................................... 972-19. RASR_A3 Register......................................................................................................... 972-20. ISER0 Register............................................................................................................ 1002-21. ISER1 Register............................................................................................................ 1012-22. ICER0 Register ........................................................................................................... 1022-23. ICER1 Register ........................................................................................................... 1032-24. ISPR0 Register............................................................................................................ 1042-25. ISPR1 Register............................................................................................................ 1052-26. ICPR0 Register ........................................................................................................... 1062-27. ICPR1 Register ........................................................................................................... 1072-28. IABR0 Register............................................................................................................ 1082-29. IABR1 Register............................................................................................................ 1092-30. IPR0 Register ............................................................................................................. 1102-31. IPR1 Register ............................................................................................................. 1112-32. IPR2 Register ............................................................................................................. 1122-33. IPR3 Register ............................................................................................................. 1132-34. IPR4 Register ............................................................................................................. 1142-35. IPR5 Register ............................................................................................................. 1152-36. IPR6 Register ............................................................................................................. 1162-37. IPR7 Register ............................................................................................................. 1172-38. IPR8 Register ............................................................................................................. 1182-39. IPR9 Register ............................................................................................................. 1192-40. IPR10 Register ............................................................................................................ 1202-41. IPR11 Register ............................................................................................................ 121

15SLAU356AMarch 2015Revised April 2015 List of FiguresSubmit Documentation Feedback



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2-42. IPR12 Register ............................................................................................................ 1222-43. IPR13 Register ............................................................................................................ 1232-44. IPR14 Register ............................................................................................................ 1242-45. IPR15 Register ............................................................................................................ 1252-46. STIR Register ............................................................................................................. 1262-47. STCSR Register .......................................................................................................... 1282-48. STRVR Register .......................................................................................................... 1292-49. STCVR Register .......................................................................................................... 1302-50. STCR Register ............................................................................................................ 1312-51. CPUID Register ........................................................................................................... 1332-52. ICSR Register ............................................................................................................. 1342-53. VTOR Register ............................................................................................................ 1362-54. AIRCR Register ........................................................................................................... 1372-55. SCR Register.............................................................................................................. 1392-56. CCR Register.............................................................................................................. 1402-57. SHPR1 Register .......................................................................................................... 1412-58. SHPR2 Register .......................................................................................................... 1422-59. SHPR3 Register .......................................................................................................... 1432-60. SHCSR Register .......................................................................................................... 1442-61. CFSR Register ............................................................................................................ 1462-62. HFSR Register ........................................................

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