mt46v32m16

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512M b: x4, x8, x16 DDR SDRAMFeatures

PDF: 09005a ef80a 1d 9d 4/Source : 09005a ef82a 95a 3a Micron Technolog y, Inc., reserves t he rig ht to cha ng e pro ducts or specif ica t ions w ithout no t ice.

512Mb_DDR_x4x8x16_D1.f m - 512Mb D DR: Rev. N; Co re DD R Rev. B 2/09 EN 1 2000 Micron Technolo gy, Inc. All rights reserved.

Double Data Rate (DDR) SDRAMM T46V128M4 32 M eg x 4 x 4 banks

M T46V64M8 16 M eg x 8 x 4 banksM T46V32M16 8 M eg x 16 x 4 banks

Features VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V VDD = +2.6V 0.1V, VDDQ = +2.6V 0.1V (DDR400) Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous datacapture (x16 has two one per byte)

Internal, pipelined double-data-rate (DDR)architecture; two data accesses per clock cycle

Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-

aligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) for masking write data

(x16 has two one per byte) Programmable burst lengths: 2, 4, or 8 Auto refresh 64ms, 8192-cycle(Commercial and industrial) 16ms, 8192-cycle (Automotive)

Self refresh (not available on AT devices) Longer-lead TSOP for improved reliability (OCPL) 2.5V I/O (SSTL_2 compatible) Concurrent auto precharge option is supported tRAS lockout supported (tRAP = tRCD)

Notes: 1. End of life.

Options M arking Configuration 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16

Plastic package 66-pin TSOP TG 66-pin TSOP (Pb-free) P

60-ball FBGA (10mm x 12.5mm) FN 60-ball FBGA (10mm x 12.5mm) (Pb-free) BN

Timing cycle time 5ns @ CL = 3 (DDR400B) -5B 6ns @ CL = 2.5 (DDR333) (FBGA only) -6 6ns @ CL = 2.5 (DDR333) (TSOP only) -6T 7.5ns @ CL = 2 (DDR266) -75E1

7.5ns @ CL = 2 (DDR266A) -75Z1

7.5ns @ CL = 2.5 (DDR266B) -751

Self refresh Standard None Low-power self refresh L

Temperature rating Commercial (0C to +70C) None

Industrial (40C to +85C) IT Automotive (40C to +105C) AT

Revision x4, x8 :D1

x4, x8, x16 :F

Table 1: Key Timing Param etersCL = CAS (READ) lat en cy; da ta -ou t w indo w is MIN clock ra te w ith 50% duty cycle a t CL = 2, CL = 2.5, or CL = 3

SpeedGrade

Clock Rate (M Hz)Data-OutWindow

AccessWindow

DQSDQSkewCL = 2 CL = 2.5 CL = 3

-5B 133 167 200 1.6ns 0.70ns + 0.40ns

-6 133 167 n/a 2.1ns 0.70ns + 0.40ns

6T 133 167 n/a 2.0ns 0.70ns + 0.45ns

-75E/-75Z 133 133 n/a 2.5ns 0.75ns + 0.50ns

-75 100 133 n/a 2.5ns 0.75ns + 0.50ns

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512M b: x4, x8, x16 DDR SDRAMFeatures

Notes : 1 . The -5B device is backward compat ib le w i th a l l slower speed grades . The volt ag e range o f

-5B device operat ing a t slow er speed g rad es is VDD = VDDQ = 2.5V 0.2V.

Figure 1: 512M b DDR SDRAM Part Num bers

FBGA Part Number System

Due to space limitations, FBGA-packaged components have an abbreviated partmarking that is different from the part number. For a quick conversion of an FBGA code,see the FBGA Part Marking Decoder on Microns Web site:www.micron.com.

Table 2: Addressing

Parameter 128 M eg x 4 64 M eg x 8 32 M eg x 16

Configurat ion 32 Meg x 4 x 4 b a nks 16 Meg x 8 x 4 b a nks 8 Meg x 16 x 4 b a nks

Refresh count 8K 8K 8KRow ad dress 8K (A0A12) 8K (A0A12) 8K (A0A12)

Bank ad dress 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Column a ddress 4K (A0A9, A11, A12) 2K (A0-A9, A11) 1K (A0A9)

Table 3: Speed Grade Compat ibil it y

Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2)

-5B1 Yes Yes Yes Yes Yes Yes

-6 Yes Yes Yes Yes Yes

-6T Yes Yes Yes Yes Yes

-75E Yes Yes Yes Yes-75Z Yes Yes Yes

-75 Yes Yes

-5B -6/-6T -75E -75Z -75 -75

Example Part Number: MT46V32M16P-6T:F

L

Special Options

Standard

Lo w po w e r

Speed Grade

t CK = 5ns, CL = 3

t CK = 6ns, CL = 2.5

t CK = 6ns, CL = 2.5

t CK = 7.5ns, CL = 2

t CK = 7.5ns, CL = 2

t CK = 7.5ns, CL = 2.5

-5B

-6

-6T

-75E

-75Z

-75

IT

AT

Operating Temp

Commercial

Industrial

Automotive

Revision

x4, x8

x4, x8, x16

:D

:F

Configurat ionMT46V Pa cka g e Speed RevisionSp.

Op .Tem p.

Configuration

128 Meg x 4

64 Meg x 8

32 Meg x 16

128M4

64M8

32M16

Package

400-mil TSOP

400-mil TSOP (Pb -free )

10mm x 12.5mm FBGA

10mm x 12.5mm FBGA (Pb-free)

TG

P

FN

BN

- :
http://www.micron.com/http://www.micron.com/http://www.micron.com/http://www.micron.com/http://www.micron.com/http://www.micron.com/

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512Mb_DDRTOC.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 3 2000 Micron Technolo gy, Inc. All rights reserved.

512M b: x4, x8, x16 DDR SDRAMTable of Contents

Table of ContentsState Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Automotive Tempature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Pin and Ball Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Electrical Specifications IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Electrical Specifications DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

ACTIVE (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50PRECHARGE (PRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51BURST TERMINATE (BST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

AUTO REFRESH (AR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52REGISTER DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88Power-down (CKE Not Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

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DDR_x4x8x16_Core 1.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN 4 2000 Micron Technolo gy, Inc. All rights reserved.

512M b: x4, x8, x16 DDR SDRAMStat e Diagram

State Diagram

Figure 2: Simpli fied Stat e Diagram

Note: This d iagram represents opera t ions w ith in a single bank only and does not cap ture concur-

rent opera t ions in o ther ba nks.

P o w e ro n

P o w e r

applied

REFS

LMRREFA

REFSX

ACT

CKE LOW

CKEL

CKE HIGH

CKEH

PRE

Precha rgea ll banks

MR

EMR

Sel frefresh

Idlea ll banks

pr echa rged

Rowa ctive

Burststop

Rea d

Rea d A

Automat ic sequenceCo m m a nd sequence

Write

WRITE

WRITE

Write A

WRITE A

Precha rgePREALL

Activep owe r-do w n

Precha rgep owe r-do w n

Auto

refresh

PRE

WRITE A READ A

READ A

PRE

PRE

READ A

READ

READ

READ

BST

ACT= ACTIVEBST= BURSTTERMINATECKEH = Exit po w er-do w nCKEL = Enter pow er-do w nEMR = Extended mode registerLMR = LOAD MO DE REGISTERMR = Mode register

PRE = PRECHARGEPREALL = PRECHARGE all banksREAD A = READ with au to precha rgeREFA = AUTO REFRESHREFS = Enter self refreshREFSX = Exit self refre shWRITE A = WRITE w ith a ut o pre cha rge

PRE

LMR

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512M b: x4, x8, x16 DDR SDRAMFunctional Descript ion

Functional Descript ion

The DDR SDRAM uses a double data rate architecture to achieve high-speed operation.The double data rate architecture is essentially a 2n-prefetch architecture with an inter-face designed to transfer two data words per clock cycle at the I/O pins. A single read or

write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two correspondingn-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use indata capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM duringREADs and by the memory controller during WRITEs. DQS is edge-aligned with data forREADs and center-aligned with data for WRITEs. The x16 offering has two data strobes,one for the lower byte and one for the upper byte.

The DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CKgoing HIGH and CK# going LOW will be referred to as the positive edge of CK.Commands (address and control signals) are registered at every positive edge of CK.Input data is registered on both edges of DQS, and output data is referenced to bothedges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at aselected location and continue for a programmed number of locations in a programmedsequence. Accesses begin with the registration of an ACTIVE command, which may thenbe followed by a READ or WRITE command. The address bits registered coincident withthe ACTIVE command are used to select the bank and row to be accessed. The addressbits registered coincident with the READ or WRITE command are used to select the bankand the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8locations. An auto precharge function may be enabled to provide a self-timed rowprecharge that is initiated at the end of the burst access.

As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMsallows for concurrent operation, thereby providing high effective bandwidth by hidingrow precharge and activation time.

An auto refresh mode is provided, along with a power-saving power-down mode. Allinputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputsare SSTL_2, Class II compatible.

General Notes The functionality and the timing specifications discussed in this data sheet are for the

DLL-enabled mode of operation.

Throughout the data sheet, the various figures and text refer to DQs as DQ. The DQterm is to be interpreted as any and all DQ collectively, unless specifically statedotherwise. Additionally, the x16 is divided into two bytes, the lower byte and upperbyte. For the lower byte (DQ0DQ7) DM refers to LDM and DQS refers to LDQS. Forthe upper byte (DQ8DQ15) DM refers to UDM and DQS refers to UDQS.

Complete functionality is described throughout the document and any page ordiagram may have been simplified to convey a topic and may not be inclusive of allrequirements.

Any specific requirement takes precedence over a general statement.

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512M b: x4, x8, x16 DDR SDRAMFunctional Descript ion

Automot ive Tempat ure

The automotive temperature (AT) option adheres to the following specifications:

16ms refresh rate

Self refresh not supported

Ambient and case temperatures cannot be less than 40C or greater than +105C

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512M b: x4, x8, x16 DDR SDRAMFunctional Block Diagram s

Functional Block Diagram s

The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memorycontaining 536,870,912 bits. It is internally configured as a 4-bank DRAM.

Figure 3: 128 M eg x 4 Functional Block Diagram

13

RAS#

CAS#

ROW-ADDRESS

MUX

CK

CS#

WE#

CK#

CONTROLLOGIC

COLUMN-ADDRESSCOUNTER/

LATCH

MODE REGISTERS

12

COMMAND

DECODE

A0A12,BA0, BA1

CKE

13

ADDRESSREGISTER

15

2048(x8)

16384

I/O GATINGDM MASK LOGIC

COLUMNDECODER

BANK0MEMORY

ARRAY(8,192 x 2,048 x 8)

BANK0ROW-ADDRESS

LATCH&

DECODER

8192

SENSE AMPLIFIERS

BANKCONTROL

LOGIC

15

BANK1BANK2

BANK3

13

11

1

2

2

REFRESHCOUNTER

4

4

4

1

INPUTREGIS TERS

1

1

1

1

RCVRS

1

8

8

28

DATA

DQS

MASK

DATA

CK

CK

COL0

DRVRS

DLL

MUX

DQSGENERATOR

4

4

4

4

48

1

READ

LATCH

WRITEFIFO

&DRIVERS

COL0

DQ0DQ3

CKOut

CKIn

DQS

DM

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512M b: x4, x8, x16 DDR SDRAMPin and Ball Assignments and Descript ions

Pin and Ball Assignm ents and Descript ions

Figure 6: 66-Pin TSOP Pin Assignment (Top View )

x4 x16 x4x8x16VSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ 9VDDQDQ 8NCVSSQUDQS

DNUVREFVSSUD MCK#CKCKENCA12A11A9A8A7A6A5A4VSS

VSSDQ 7VSSQNCDQ 6VDDQNCDQ 5VSSQNCDQ 4VDDQNCNCVSSQDQ S

DNUVREFVSSDMCK#CKCKENCA12A11A9A8A7A6A5A4VSS

VSSNFVSSQNCDQ 3VDDQNCNFVSSQNCDQ 2VDDQNCNCVSSQDQ S

DNUVREFVSSDMCK#CKCKENCA12A11A9A8A7A6A5A4VSS

6665

6463

6261

6059

58

5756

5554

5352

51

5049

4847

4645

4443

4241

40

3938

3736

3534

12

34

56

78

9

1011

1213

1415

16

1718

1920

2122

2324

2526

27

2829

3031

3233

VDDDQ 0

VDDQDQ 1DQ 2VSSQ

DQ 3DQ 4

VDDQDQ 5DQ 6VSSQDQ 7

NCVDDQLDQS

NCVDD

DNULDMWE#

CAS#

RAS#CS#

NCBA0BA1

A10/APA0A1A2A3

VDD

x8VDD

DQ 0VDDQ

NCDQ 1VSSQ

NCDQ 2

VDDQNC

DQ 3VSSQ

NCNC

VDDQNC

NCVDD

DNUNC

WE#CAS#RAS#

CS#NC

BA0BA1

A10/APA0A1A2A3

VDD

VDDNF

VDDQNC

DQ 0VSSQ

NCNF

VDDQNC

DQ 1VSSQ

NCNC

VDDQNC

NCVDD

DNUNC

WE#CAS#RAS#

CS#NC

BA0BA1

A10/APA0A1A2A3

VDD

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VSSQ

DQ14

DQ12

DQ10

DQ8

VREF

DQ15

VDD Q

VSSQVDD Q

VSSQ

VSSCK

A12

A11

A8

A6

A4

VSSDQ13DQ11

DQ 9

UDQS

UD MCK#

CKE

A9A7

A5

VSS

VDD

DQ 2

DQ 4

DQ 6

LDQS

LDM

WE#

RAS#

BA1

A0

A2

VDD

DQ 0

VSSQVDD Q

VSSQ

VDD Q

VDDCAS#

CS#

BA0

A10

A1A3

VDD Q

DQ1DQ3

DQ5

DQ7

x16 (Top View )

VSSQNC

NC

NC

NC

VREF

NFVDD Q

VSSQVDD Q

VSSQ

VSSCK

A12

A11

A8

A6

A4

VSSDQ3

NFDQ2

DQS

DMCK#

CKE

A9A7

A5

VSS

VDD

DQ 0

NF

DQ 1

NC

NC

WE#

RAS#

BA1

A0

A2

VDD

NFVSSQVDD Q

VSSQ

VDD Q

VDDCAS#

CS#

BA0

A10

A1A3

VDD QNCNC

NC

NC

x4 (Top View)

VSSQ

NC

NC

NC

NC

VREF

DQ 7

VDD Q

VSSQ

VDD Q

VSSQVSSCK

A12

A11

A8

A6

A4

VSSDQ6

DQ5DQ4

DQS

DM

CK#CKE

A9

A7A5

VSS

VDDDQ 1

DQ 2

DQ 3

NC

NC

WE#

RAS#

BA1

A0

A2

VDD

DQ 0

VSSQ

VDD Q

VSSQVDD Q

VDDCAS#

CS#

BA0

A10

A1

A3

VDD Q

NC

NCNC

NC

x8 (Top View)

A

1 2 3 4 5 6 7 8 9

B

C

D

E

F

G

H

J

K

L

M

A

1 2 3 4 5 6 7 8 9

B

C

D

E

F

G

H

J

K

L

M

A

1 2 3 4 5 6 7 8 9

B

C

D

E

F

G

H

J

K

L

M

DNU

DNU

DNU


512Mb_DDR_x4x8x16_D2.f m - 512Mb D DR: Rev. N; Co re D DR Rev. B 2/09 EN 10 2000 Micron Technolo gy, Inc. All rights reserved.


Figure 7: 60-Ball FBGA Ball Assignment (Top View )

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Table 4: Pin and Ball Descriptions

FBGANumbers

TSOPNumbers Symbol Type Description

K7, L8, L7,

M8, M 2, L3,L2, K3, K2,

J3, K8,

J2, H2

29, 30, 31,

32, 35, 36,37, 38, 39,

40, 28

41, 42

A0, A1, A2,

A3, A4, A5,A6, A7, A8,

A9, A10,

A11, A12

Input Address inputs: Provide the row ad dress fo r ACTIVE comma nds, and the

column ad dre ss and a uto precha rge bit (A10) fo r READ/WRITEcommand s, to select one locat ion out o f the memory array in the

respective bank. A10 sampled during a PRECHARGE command

de te rmines w het her t he PRECHARGE applies to on e ba nk (A10 LOW,

ba nk selecte d b y BA0, BA1) or a ll ba nks (A10 HIGH). The a dd ress inpu ts

a lso p rovide th e o p-cod e d uring a LOAD MODE REGISTER com ma nd .

J8, J7 26, 27 BA0, BA1 Input Bank address inputs: BA0 a nd BA1 de fine to w hich ba nk a n ACTIVE,

READ, WRITE, o r PRECHARGE co mm a nd is bein g a pplie d. BA0 an d B A1

also d efine w hich mod e register (mod e register or extended mod e

reg ister) is loa d ed du ring th e LOAD MODE REGISTER (LMR) com ma nd .

G2, G3 45, 46 CK, CK# Input Clock: CK an d CK# are diff erent ial clock input s. All ad dress and control

input sig na ls are sampled o n the crossing of the po sitive edg e of CK and

neg at ive edg e of CK#. Output da ta (DQ and DQS) is referenced t o th e

crossing s of CK an d CK#.H3 44 CKE Input Clock enable: CKE HIGH act ivate s a nd CKE LOW de a ctivat es the int erna l

clock, input buf fe rs, a nd ou tpu t d rivers. Ta king CKE LOW provides

PRECHARGE POWER-DOWN a nd SELF REFRESH op era t io ns (a ll ba nks

id le), o r ACTIVE POWER-DOWN (row ACTIVE in a ny b a nk). CKE is

synchronous for POWER-DOWN entry and exit, and for SELF REFRESH

ent ry. CKE is asynchro no us fo r SELF REFRESH exit a nd fo r disab ling th e

outputs . CKE must b e ma inta ined HIGH througho ut read and w rite

a ccesses. Input b uff ers (excluding CK, CK#, an d CKE) a re d isa bled during

POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF

REFRESH. CKE is an SSTL_2 inp ut bu t w ill de t ect a n LVCMOS LOW levela f t er VDD is a pplied a nd unt il CKE is first broug ht HIGH, af ter w hich itbe com es a SSTL_2 inpu t o nly.

H8 24 CS# Input Chip select: CS# enables (registered LOW) and disables (registered

HIGH) the comma nd d ecode r. All comma nds are m asked w hen CS# isregistered HIGH. CS# provides fo r externa l ban k selection on systems w ith

multiple banks. CS# is conside red pa rt of the com ma nd cod e.

F3

F7, F3

47

20,47

DM

LDM, U DM

Input Input data m ask: DM is an input mask s igna l for w rite d at a . Input da ta

is masked w hen DM is sampled HIGH along w ith that input dat a d uring a

w rite a ccess. DM is sam pled o n bo th e dg es of DQS. Althoug h DM pins are

input-only, the DM load ing is designe d t o ma tch that of DQ and DQS

pins. For t he x16, LDM is DM fo r DQ0DQ7 a nd UDM is DM for DQ 8

DQ15. Pin 20 is a NC on x4 and x8.

H7, G8,

G7

23, 22,

21

RAS#, CAS#,

WE#

Input Command inputs: RAS#, CAS#, and WE# (alon g w ith CS#) de fine th e

command being entered.

A8, B9, B7,

C9, C7, D9,

D7, E9, E1,D3, D1, C3,

C1, B3, B1,

A2

2, 4, 5,

7, 8, 10,

11, 13, 54,56, 57, 59,

60, 62, 63,

65

DQ0DQ2

DQ3DQ5

DQ6DQ8DQ9DQ11

DQ12DQ14

DQ15

I/O Data input/output: Dat a b us for x16.

A8, B7, C7,

D7, D3, C3,

B3, A2

2, 5, 8,

11, 56, 59,

62, 65

DQ0DQ2

DQ3DQ5

DQ6, DQ7

I/O Data input/output: Data bus for x8.

B7, D7, D3,

B3

5, 11, 56,

62

DQ0DQ2

DQ 3

I/O Data input/output: Data bus for x4.

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E3

E7E3

51

1651

DQ S

LDQSUDQS

I/O Data strobe: Output w ith read d at a , input w ith write data . DQS is edg e-

aligne d w ith read da ta , centered in w rite da ta . I t is used to capture dat a .For th e x16, LDQS is DQS for DQ 0DQ7 a nd UDQS is DQS for DQ8DQ15.

Pin 16 (E7) is NC on x4 a nd x8.

F8, M7, A7 1, 18, 33 VDD Supply Pow er supply: + 2.5V 0.2V. (+ 2.6V 0.1V fo r DDR400).

B2, D2, C8,

E8, A9

3, 9, 15, 55,

61

VDD Q Supply DQ power supply: + 2.5V 0.2V (+ 2.6V 0.1V fo r DDR400). Isolat ed onthe d ie for improved noise immunity.

F1 49 VREF Supply SSTL_2 ref ere nce vo lta g e.

A3, F2, M3 34, 48, 66 VSS Supply Ground.

A1, C2, E2,

B8, D8

6, 12, 52,

58, 64

VSSQ Supply DQ ground: Isolated on t he die fo r improved n oise immun ity.

14, 17, 25,

43, 53

NC No connect for x16: These pins shou ld be left unconne cted.

B1, B9, C1,C9, D1, D9,

E1, E7, E9,

F7

4, 7, 10,13, 14, 16,

17, 20, 25,

43, 53, 54,

57, 60, 63

NC No connect for x8 : These pins should be lef t un connecte d.

B1, B9, C1,

C9, D1, D9,

E1, E7, E9,

F7

4, 7, 10, 13,

14, 16, 17,

20, 25, 43,

53, 54, 57,

60, 63

NC No connect for x4 : These pins should be lef t un connecte d.

A2, A8, C3,

C7

2, 8, 59, 65 NF No function f or x4: These pins should be lef t un connected .

F9 19, 50 DNU Do not use: Must f loat to minimize noise on VREF.

Table 5: Reserved NC Pin and Ball Descript ionsNC pins not listed ma y also be reserved fo r oth er uses; this ta ble de fines NC pins of impo rtan ce


17 A13 Input Addre ss input A13 fo r 1Gb d evices.

Table 4: Pin and Ball Descript ions (cont inued)

FBGANumbers


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512M b: x4, x8, x16 DDR SDRAMPackage Dimensions

Package Dimensions

Figure 8: 66-Pin Plastic TSOP (400 mil)

No t es: 1. All d imen sio n s a re in millime t ers.

2 . Package w idth a nd length d o no t include mold prot rusion ; a llow ab le mold prot rusion is

0.25mm p er side .

3 . Not a ll packages wi ll have the ha lf moo n shaped no tches as show n.

SEE D ETAIL A

0.10

0.65 TYP0.71

10.16 0.08

0.15

0.50 0.10

PIN #1 ID

DETAIL A

22.22 0.08

0.32 .075 TYP

+ 0.03

0.02

+ 0.10

0.05

1.20 MAX

0.10

0.25

0.80 TYP

0.10 (2X)

GAGE PLANE

11.76 0.20

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512M b: x4, x8, x16 DDR SDRAMPackage Dimensions

Figure 9: 60-Ball FBGA (10m m x 12.5m m)

No t es: 1. All d imen sio n s a re in millime t ers.

2. Topside pa rt ma rking de coder can be found on Microns Web s ite.

BALL #1 ID

SOLDER BALL MATERIAL:62% Sn, 36% Pb, 2% Ag OR96.5% Sn, 3% Ag, 0.5% CuSOLDER BALL PAD: .33NON SO LDER MASK D EFINED

MOLD COMPOUND: EPOXY NOVOLAC

SUBS TRATE: PLASTIC LAM INATE

1.20 MAX

0.85 0.05

0.10 C C

SEATING P LANE

BALL A1 ID

BALL A1

CL

CL

.4560X SOLDER BALL DIAMETER

REFERS TO POSTREFLOWCON DITION. THE P RE-REFLOW

DIAMETER IS 0.40.

BALL A9

11.00

5.50 0.05

6.25 0.05

12.50 0.10

1.00TYP

6.40

1.80CTR

0.80 (TYP)

3 .2 0 0 .05 5 .0 0 0 .0 5

10.00 0.10

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512M b: x4, x8, x16 DDR SDRAMElectrical Specif ications IDD

Electrical Specifications IDD

Table 6: IDD Specifications and Condit ions (x4, x8)VDDQ = + 2.6V 0.1V, VDD = + 2.6V 0.1V (-5B); VDD Q = + 2.5V 0.2V, VDD = + 2.5V 0.2V (-6, -6T, -75E, -75Z, -75);

0 C TA + 70 C; Not es: 15, 11, 13, 15, 47; Notes appea r on pag es 3540; See a lso Tab le 8 on pa g e 17

Parameter/Condit ion Symbol -5B -6/6T -75E -75Z/-75 Units Notes

Operating one-bank active-precharge current:tRC = tRC (MIN); tCK = tCK (MIN); DQ, D M, a nd DQS input schang ing o nce per clock cycle; Add ress and con trol inputs

chang ing on ce every tw o clock cycles

IDD 0 155 130 130 115 mA 23, 48

Operating one-bank active-read-precharge current:

Burst = 4; tRC = t RC (MIN); tCK = tCK (MIN); IOU T = 0mA;Address and control inputs chang ing once per clock cycle

IDD 1 185 160 160 145 mA 23, 48

Precharge pow er-down standby current: All ba nks idle;

Power-dow n mode; tCK = tCK (MIN); CKE = (LOW)

IDD 2P 5 5 5 5 mA 24, 33

Idle standby current: CS# = HIGH; All ba nks are idle ;t

CK =t

CK (MIN); CKE = HIGH; Add ress an d o the r controlinputs cha ng ing o nce per clock cycle; VIN = VREF fo r DQ, DQS,and DM

IDD 2F 55 45 45 40 mA 51

Active power-down standby current: One ba nk act ive;

Power-dow n mode; tCK = tCK (MIN); CKE = LOW

IDD 3P 45 35 35 30 mA 24, 33

Active stand by current: CS# = HIGH; CKE = HIGH; One b an k

active ; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQSinputs cha ng ing t w ice per clock cycle; Add ress an d o the r

contro l inputs chang ing o nce per clock cycle

IDD 3N 60 50 50 45 mA 23

Operating burst read current : Burst = 2; Continuou s burstread s; One ba nk active; Add ress an d cont rol inputs chang ing

on ce per clock cycle; tCK = tCK (MIN); IOU T = 0mA

IDD 4R 190 165 165 145 mA 23, 48

Operating burst w rite current: Burst = 2; Cont inuous burst

w rites; One bank active; Add ress an d cont rol input s cha ng ingon ce per clock cycle; tCK = tCK (MIN); DQ, DM, a nd DQS input s

chang ing t w ice per clock cycle

IDD 4W 195 175 155 135 mA 23

Auto ref resh burst current: tRFC = tRFC (MIN) IDD 5 345 290 290 280 mA 50tRFC = 7.8s IDD 5A 11 10 10 10 mA 28, 50tRFC = 1.95s (AT) IDD 5A 16 15 15 15 mA 28, 50

Self refresh current: CKE 0.2V Standard IDD 6 5 5 5 5 mA 12

Low pow er (L) IDD 6A 3 3 3 3 mA 12

Operating bank interleave read current: Four ba nk

interleaving READs (burst = 4) w ith a uto precharg e,tRC = minimum tRC allow ed; tCK = tCK (MIN); Add ress a nd

cont rol input s cha ng e o nly du ring a ctive READ or WRITE

commands

IDD 7 450 405 400 350 mA 23, 49

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Table 7: IDD Specifications and Condit ions (x16)VDDQ = + 2.6V 0.1V, VDD = + 2.6V 0.1V (-5B); VDD Q = + 2.5V 0.2V, VDD = + 2.5V 0.2V (-6, -6T, -75E, -75Z, -75);

0 C TA + 70 C; Not es: 15, 11, 13, 15, 47; Notes appea r on pag es 3540; See a lso Tab le 8 on pa g e 17

Parameter/Condit ion Symbol -5B -6/6T -75E -75Z/-75 Units Notes

Operating one-bank active-precharge current:tRC = tRC (MIN); tCK = tCK (MIN); DQ, D M, a nd DQS input schang ing o nce per clock cycle; Add ress and con trol inputs

chang ing on ce every tw o clock cycles

IDD 0 155 130 130 115 mA 23, 48

Operating one-bank active-read-precharge current:

Burst = 4; tRC = t RC (MIN); tCK = tCK (MIN); IOU T = 0mA;Address and control inputs chang ing once per clock cycle

IDD 1 195 160 160 145 mA 23, 48

Precharge pow er-down standby current: All ba nks idle;

Power-dow n mode; tCK = tCK (MIN); CKE = (LOW)

IDD 2P 5 5 5 5 mA 24, 33

Idle standby current: CS# = HIGH; All ba nks are idle ;tCK = tCK (MIN); CKE = HIGH; Add ress an d o the r controlinputs cha ng ing o nce per clock cycle; VIN = VREF fo r DQ, DQS,and DM

IDD 2F 55 45 45 40 mA 51

Active power-down standby current: One ba nk act ive;

Power-dow n mode; tCK = tCK (MIN); CKE = LOW

IDD 3P 45 35 35 30 mA 24, 33

Active standby current: CS# = HIGH; CKE = HIGH; One b a nk

active ; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQSinputs cha ng ing t w ice per clock cycle; Add ress an d o the r

contro l inputs chang ing o nce per clock cycle

IDD 3N 60 50 50 45 mA 23

Operating burst read current : Burst = 2; Continuousburst reads; One ba nk active; Add ress and cont rol inputs

chang ing o nce per clock cycle; tCK = tCK (MIN); IOU T = 0mA

IDD 4R 210 165 165 145 mA 23, 48

Operating burst w rite current: Burst = 2; Cont inuous burst

w rites; One bank active; Add ress an d cont rol inputs chang ingon ce per clock cycle; tCK = tCK (MIN); DQ, DM, a nd DQS input s

chang ing t w ice per clock cycle

IDD 4W 215 195 160 135 mA 23

Auto ref resh burst current: tRFC = tRFC (MIN) IDD 5 345 290 290 280 mA 50tRFC = 7.8s IDD 5A 11 10 10 10 mA 28, 50tRFC = 1.95s (AT) IDD 5A 16 15 15 15 mA 28, 50

Self refresh current: CKE 0.2V Standard IDD 6 6 5 5 5 mA 12

Low pow er (L) IDD 6A 4 3 3 3 mA 12

Operating bank interleave read current: Four ba nk

interleaving READs (burst = 4) w ith a uto precharg e,tRC = minimum tRC allow ed; tCK = tCK (MIN); Add ress a nd

cont rol input s cha ng e o nly du ring a ctive READ or WRITE

commands

IDD 7 480 405 400 350 mA 23, 49

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Table 8: IDD Test Cycle TimesValues reflect num ber o f clock cycles for ea ch test

IDD TestSpeedGrade

Clock CycleTime tRRD tRCD tRAS tRP tRC tRFC tREFI CL

IDD 0 -75/75Z 7.5ns n/a n/a 6 3 9 n/a n/a n/a

-75E 7.5ns n/a n/a 6 2 8 n/a n/a n/a

-6/-6T 6ns n/a n/a 7 3 10 n/a n/a n/a

-5B 5ns n/a n/a 8 3 11 n/a n/a n/a

IDD 1 -75 7.5ns n/a n/a 6 3 9 n/a n/a 2.5

-75Z 7.5ns n/a n/a 6 3 9 n/a n/a 2

-75E 7.5ns n/a n/a 6 2 8 n/a n/a 2

-6/-6T 6ns n/a n/a 7 3 10 n/a n/a 2.5

-5B 5ns n/a n/a n/a n/a n/a n/a n/a 3

IDD 4R -75 7.5ns n/a n/a n/a n/a n/a n/a n/a 2.5

-75Z 7.5ns n/a n/a n/a n/a n/a n/a n/a 2

-75E 7.5ns n/a n/a n/a n/a n/a n/a n/a 2

-6/-6T 6ns n/a n/a n/a n/a n/a n/a n/a 2.5

-5B 5ns n/a n/a n/a n/a n/a n/a n/a 3

IDD 4W -75 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a

-75Z 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a

-75E 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a

-6/-6T 6ns n/a n/a n/a n/a n/a n/a n/a n/a

-5B 5ns n/a n/a n/a n/a n/a n/a n/a n/a

IDD 5 -75/75Z 7.5ns n/a n/a n/a n/a n/a 10 10 n/a

-75E 7.5ns n/a n/a n/a n/a n/a 9 9 n/a

-6/-6T 6ns n/a n/a n/a n/a n/a 12 12 n/a

-5B 5ns n/a n/a n/a n/a n/a 14 14 n/a

IDD

5A -75/75Z 7.5ns n/a n/a n/a n/a n/a 10 1,029 n/a-75E 7.5ns n/a n/a n/a n/a n/a 10 1,029 n/a

-6/-6T 6ns n/a n/a n/a n/a n/a 12 1,288 n/a

-5B 5ns n/a n/a n/a n/a n/a 14 1,546 n/a

IDD 7 -75 7.5ns 2 3 n/a 3 10 n/a n/a 2.5

-75Z 7.5ns 2 3 n/a 3 10 n/a n/a 2

-75E 7.5ns 2 3 n/a 2 8 n/a n/a 2

-6/-6T 6ns 2 3 n/a 3 10 n/a n/a 2.5

-5B 5ns 2 3 n/a 3 11 n/a n/a 3

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512M b: x4, x8, x16 DDR SDRAMElectrical Specifications DC and AC

Electrical Specificat ions DC and AC

Stresses greater than those listed in Table 9 may cause permanent damage to the device.This is a stress rating only, and functional operation of the device at these or any otherconditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods mayaffect reliability.

Table 9: Absolute M aximum Ratings

Parameter M in M ax Units

VDD supply voltag e relative to VSS 1V + 3.6V V

VDDQ supply volta ge rela tive to VSS 1V + 3.6V V

VREF and inputs voltag e rela t ive to VSS 1V + 3.6V V

I/O pins volta g e rela tive t o VSS 0.5V VDD Q + 0.5V V

Storage temperature (plastic) 55 + 150 C

Short circuit o utput current 50 mA

Table 10: DC Electr ical Character istics and Operat ing Condit ions (-5B)Notes: 15 a nd 17 apply to the ent ire table; Notes appea r on page 35; VDD Q = + 2.6V 0.1V, VDD = + 2.6V 0.1V

Parameter/Condit ion Symbol M in M ax Units Notes

Supply volta ge VDD + 2.5 + 2.7 V 37, 42

I/O supply vo lta g e VDDQ + 2.5 + 2.7 V 37, 42, 45

I/O ref eren ce volta g e VREF 0.49 VDDQ 0.51 VDD Q V 7, 45

I/O term ina tion vo lta g e (syste m) VTT VREF - 0.04 VREF + 0.04 V 8, 45

Input high (logic 1) volta ge VIH(DC) VREF + 0.15 VDD + 0.3 V 29

Input low (logic 0) voltag e VIL(DC) 0.3 VREF - 0.15 V 29

Input leakage current:

Any input 0V VIN VDD , VREF pin 0V VIN 1.35V(All other pins not unde r test = 0V)

II 2 + 2 A

Output leakag e current :

(DQ are disabled; 0V VOU TVDD Q)IOZ 5 + 5 A

Full-drive option output

levels (x4, x8, x16):

Hig h current (VOU T =VDD Q - 0.373V, m inim umVREF, minimum VTT)

IOH 16.8 mA 38, 40

Low current (VOU T =0.373V, m a ximum VREF,maximum VTT)

IOL + 16.8 mA

Redu ced-drive op tion

out put levels:


IOHR 9 mA 39, 40


IOLR + 9 mA

Ambient operat ing

temperatures

Commercial TA 0 + 70 C

Industrial TA 40 + 85 C

Automotive TA 40 + 105 C

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Table 11: DC Electr ical Characterist ics and Operat ing Condit ions (-6, -6T, -75E, -75Z, -75)Notes: 15, 17 apply to the e nt ire ta ble; Notes appea r on page 35; VDD Q = + 2.5V 0.2V, VDD = + 2.5V 0.2V


Supply volta ge VDD + 2.3 + 2.7 V 37, 42

I/O supply vo lta g e VDDQ + 2.3 + 2.7 V 37, 42, 45

I/O ref eren ce volta g e VREF 0.49 VDDQ 0.51 VDD Q V 7, 45

I/O term ina tion vo lta g e (syste m) VTT VREF - 0.04 VREF + 0.04 V 8, 45

Input high (logic 1) volta ge VIH(DC) VREF + 0.15 VDD + 0.3 V 29

Input low (logic 0) voltag e VIL(DC) 0.3 VREF - 0.15 V 29

Input leakage current:

Any input 0V VIN VDD , VREF pin 0V VIN 1.35V

(All other pins not unde r test = 0V)

II 2 + 2 A

Output leakag e current :

(DQ are disabled; 0V VOU TVDD Q)IOZ 5 + 5 A

Full-drive option output

levels (x4, x8, x16):

Hig h current (VOU T =VDD Q - 0.373V, m inim um

VREF, minimum VTT)

IOH 16.8 mA 38, 40


IOL + 16.8 mA

Redu ced-drive op tion

out put levels:


IOHR 9 mA 39, 40


IOLR + 9 mA

Ambient operat ing

temperatures

Commercial TA 0 + 70 C

Industrial TA 40 + 85 C

Automotive TA

40 + 105 C

Table 12: AC Input Operating Condit ionsNotes: 15, 17 apply to the e nt ire ta ble; Notes appea r on page 35;

0 C TA + 70 C; VDD Q = + 2.5V 0.2V, VDD = + 2.5V 0.2V (VDD Q = + 2.6V 0.1V, VDD = + 2.6V 0.1V for -5B)


Input high (logic 1) volta ge VIH(AC) VREF + 0.310 V 15, 29, 41

Input low (logic 0) voltag e VIL(AC) VREF - 0.310 V 15, 29, 41

I/O ref eren ce volta g e VREF(AC) 0.49 VDDQ 0.51 VDD Q V 7

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Figure 10: Input Voltage Waveform

No t es: 1. VOH (MIN) w ith te st loa d is 1.927V.

2. VOL (MAX) w ith t est lo a d is 0.373V.

3. Numbers in d iagram reflect no minal values ut iliz ing circuit below for a ll devices other t han

-5B.

0.940V

1.100V

1.200V

1.225V

1.250V1.275V

1.300V

1.400V

1.560V

VIL(AC)

VIL(DC)

VREF - AC noiseVREF - DC errorVREF + DC errorV

REF+ AC noise

Receiver

Tra nsmitt er

VIH(DC)

VIH(AC)

VOH(MIN) (1.670V1for SSTL_2 termination)

VIN(AC)- provides margin between VOL(MAX)

and VIL(AC)

VssQ

VDDQ (2.3V MIN)

VOL (MAX)(0.83V2

for SSTL_2termination)

System noise margin (pow er/ground,crosstalk, signal integr ity a t tenua tion)

Referencepoint

25

25

VTT

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Figure 11: SSTL_2 Clock Input

No t es: 1. CK or CK# may n ot be m ore po sitive tha n VDD Q + 0 .3V or more nega t ive tha n VSS - 0.3V.

2. This provides a m inimum of 1.15V to a m a ximum o f 1.35V a nd is alw a ys half o f VDD Q.

3. CK an d CK# must cross in this region .

4. CK an d CK# must meet at least VID(DC) MIN when static and is centered aro und VMP(DC).

5. CK and CK# must ha ve a minimum 700mV peak-to-peak swing.

6. For AC ope ration , all DC clock requirements must also be sat isfied.

7. Numbers in diag ram reflect no minal values for a ll devices other t han -5B.

Table 13: Clock Input Operating Condit ionsNotes: 15, 16, 17, 31 apply to the en t ire ta ble; Notes appea r on page 35;

0 C TA + 70 C; VDD Q = + 2.5V 0.2V, VDD = + 2.5V 0.2V (VDD Q = + 2.6V 0.1V, VDD = + 2.6V 0.1V for -5B)


Clock input mid-point volta ge : CK and CK# VMP(DC) 1.15 1.35 V 7, 10

Clock input voltage level: CK and CK# VIN(DC) 0.3 VDD Q + 0.3 V 7

Clock input d ifferent ial voltag e: CK an d CK# VID(DC) 0.36 VDD Q + 0.6 V 7, 9

Clock input d ifferent ial voltag e: CK an d CK# VID(AC) 0.7 VDD Q + 0.6 V 9

Clock input crossing point voltag e: CK and CK# VIX(AC) 0.5 VDD Q - 0.2 0.5 VDD Q + 0.2 V 10

CK

CK#

2.80V

Maximu m clo ck level1

Minimum clo ck level10.30V

1.25V

1.45V

1.05V

VID(AC)5

VID(DC)4

X

VMP (DC)2 VIX(AC)

3

X

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Table 14: Capacitance (x4, x8 TSOP)Note: 14 applies to the ent ire table; Notes appea r on page 35

Parameter Symbol M in M ax Units Notes

Delta input /ou tpu t capa citan ce: DQ0DQ3 (x4), DQ0DQ7 (x8) DCIO 0.50 pF 25

Delta input capa cita nce: Command and ad dress DCI1 0.50 pF 30

Delta input ca pacita nce: CK, CK# DCI2 0.25 pF 30

Input /ou tpu t capa citan ce: DQ, DQS, DM CIO 4.0 5.0 pF

Input capacitance: Comma nd a nd a ddress CI1 2.0 3.0 pF

Input capacitance: CK, CK# CI2 2.0 3.0 pF

Input capa cita nce: CKE CI3 2.0 3.0 pF

Table 15: Capacit ance (x4, x8 FBGA)Note: 14 applies to the ent ire table; Notes appea r on page 35


Delta input/out put capa cita nce: DQ, DQS, DM DCIO 0.50 pF 25



Input /ou tpu t capa citan ce: DQ, DQS, DM CIO 3.5 4.5 pF




Table 16: Capacit ance (x16 TSOP)Note: 14 applies to the ent ire table; Notes appea r on page 35


Delta input /ou tpu t ca pa citan ce: DQ0DQ7, LDQS, LDM DCIOL 0.50 pF 25

Delta input /ou tpu t capa citan ce: DQ8DQ15, UDQS, UDM DC IOU 0.50 pF 25



Input /ou tpu t ca pa citan ce: DQ, LDQS, UDQS, LDM, UDM CIO 4.0 5.0 pF




Table 17: Capacitance (x16 FBGA)Note: 14 applies to the ent ire table; Notes appea r on page 35


Delta input /ou tpu t ca pa citan ce: DQ0DQ7, LDQS, LDM DCIOL 0.50 pF 25

Delta input /ou tpu t capa citan ce: DQ8DQ15, UDQS, UDM DC IOU 0.50 pF 25



Input /ou tpu t ca pa citan ce: DQ, LDQS, UDQS, LDM, UDM CIO 3.5 4.5 pF




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Table 18: Electr ical Characterist ics and Recomm ended AC Operating Condit ions (-5B)Notes 16, 1618, 34 apply to the e nt ire ta ble; Notes appea r on page 35;

0 C TA + 70 C; VDD Q = + 2.6V 0.1V, VDD = + 2.6V 0.1V

AC Characteristics -5B

Units NotesParameter Symbol M in M ax

Access w indo w of DQ f rom CK/CK# tAC 0.70 + 0.70 ns

CK hig h-level wid th tCH 0.45 0.55 tCK 31

Clo ck cycle t ime CL = 3 tCK (3) 5 7.5 ns 52

CL = 2.5 tCK (2.5) 6 13 ns 46, 52

CL = 2 tCK (2) 7.5 13 ns 46, 52

CK low -level widt h tCL 0.45 0.55 tCK 31

DQ and DM input ho ld t ime rela t ive to DQS tDH 0.40 ns 27, 32

DQ and DM input pulse w idth ( for each input) tDIPW 1.75 ns 32

Access w indo w of DQS fro m CK/CK# tDQSCK 0.60 + 0.60 ns

DQS input high pulse w idth tDQSH 0.35 tCK

DQS input low pulse w idth tDQSL 0.35 tCK

DQSDQ skew, DQS to last DQ valid, per g roup, per a ccess tDQSQ 0.40 ns 26, 27

WRITE comm an d t o f irst DQS lat ching tra nsition tDQSS 0.72 1.28 tCK

DQ and DM input setup t ime rela t ive to DQS tDS 0.40 ns 27, 32

DQS fa lling ed ge from CK rising hold time tDSH 0.2 tCK

DQS falling edg e to CK rising setu p time tDSS 0.2 tCK

Half-clock perio d tHP tCH, tCL ns 35

Da ta -ou t High -Z w indo w fro m CK/CK# tHZ + 0.70 ns 19, 43

Add ress an d cont rol input h old time (slew ra te 0.5 V/ns) tIHF 0.60 ns 15

Add ress an d cont rol input pulse widt h (fo r each input) tIPW 2.2 ns

Add ress an d cont rol input setup t ime (slew rate 0.5 V/ns) tISF 0.60 ns 15

Da ta -ou t Low -Z w indo w fro m CK/CK# tLZ 0.70 ns 19, 43

LOAD MOD E REGISTER com ma nd cycle t ime tMRD 10 ns

DQDQS hold, DQS to f irst DQ to go non -valid, per access tQH tHP -tQHS ns 26, 27

Data hold skew fa ctor tQHS 0.50 ns

ACTIVE-to -READ w ith a uto precha rge comm a nd tRAP 15 ns

ACTIVE-t o -PRECHARGE co mma nd tRAS 40 70,000 ns 36

ACTIVE-to -ACTIVE/AUTO REFRESH co mma nd p erio d tRC 55 ns

ACTIVE-to -READ or WRITE de la y tRCD 15 ns

REFRESH-t o -REFRESH co mm a nd int er va l tREFC 70.3 s 24

REFRESH-to -REFRESH comm a nd int erva l (Aut o mo tive ) tREFCAT 17.55 s 24

Averag e pe riod ic refresh interval tREFI 7.8 s 24

Averag e pe riod ic refresh interval (Auto mot ive) tREFIAT 1.95 s 24

AUTO REFRESH com ma nd pe riod tRFC 70 ns 50PRECHARGE comm a nd period tRP 15 ns

DQS read preamble tRPRE 0.9 1.1 tCK 44

DQS read postamble tRPST 0.4 0.6 tCK 44

ACTIVE ba nk at o ACTIVE ba nk bcommand tRRD 10 ns

Terminat ing volta ge d elay to VDD tVTD 0 ns

DQS write preamble tWPRE 0.25 tCK

DQS write preamble setup time tWPRES 0 ns 21, 22

DQS write postamb le tWPST 0.4 0.6 tCK 20

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Write recovery time tWR 15 ns

Inte rna l WRITE-to -READ comm a nd de lay tWTR 2 tCK

Exit SELF REFRESH-t o -no n-READ co mm a nd tXSNR 70 ns

Exit SELF REFRESH-t o -READ com ma nd tXSRD 200 tCK

Data va lid output w indow n/a tQH - tDQSQ ns 26

Table 18: Electrical Characteristics and Recommended AC Operat ing Condit ions (-5B) (cont inued)Not es 16, 1618, 34 apply to t he e ntire ta ble; Not es appea r on pa ge 35;


AC Characteristics -5B


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Table 19: Electrical Characteristics and Recommended AC Operating Condit ions (-6)Notes: 16, 1618, 34 apply to the en t ire ta ble; Notes appea r on page 35;


AC Characteristics -6 (FBGA)




Clo ck cycle t ime CL = 2.5 tCK (2.5) 6 13 ns 46, 52

CL = 2 tCK (2) 7.5 13 ns 46, 52










DQS fa lling ed ge from CK rising - hold time tDSH 0.2 tCK

DQS falling edg e t o CK rising - setup time tDSS 0.2 tCK

Half-clock perio d tHP tCH,tCL

ns 35


Add ress an d cont rol input ho ld time (fa st slew ra te) tIHF 0.75 ns

Add ress an d cont rol input ho ld time (slow slew rate ) tIHS 0.8 ns 15


Add ress an d cont rol input setup t ime (fa st slew ra te) tISF 0.75 ns

Add ress an d cont rol input setup t ime (slow slew rat e) tISS 0.8 ns 15



DQ-DQS hold, DQS to f irst DQ to g o n on-valid, per a ccess tQH tHP -tQHS ns 26, 27



ACTIVE-t o -PRECHARGE co mma nd tRAS 42 70,000 ns 36, 54





Averag e pe riod ic refresh intervalt

REFI 7.8 s 24Averag e pe riod ic refresh interval (Auto mot ive) tREFIAT 1.95 s 24

AUTO REFRESH com ma nd pe riod tRFC 72 ns 50

PRECHARGE comm a nd period tRP 15 ns



ACTIVE ba nk at oACTIVE ba nk bcommand tRRD 12 ns

Terminat ing volta ge d elay to VSS tVTD 0 ns


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Table 19: Electrical Characteristics and Recommended AC Operating Condit ions (-6) (cont inued)Not es: 16, 1618, 34 apply to the ent ire ta ble; Not es appea r on pa g e 35;


AC Characteristics -6 (FBGA)


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Table 20: Electr ical Characterist ics and Recomm ended AC Operat ing Condit ions (-6T)Notes: 16, 1618, 34 apply to the en t ire ta ble; Notes appea r on page 35;


AC Characteristics -6T (TSOP)




Clo ck cycle t ime CL = 2.5 tCK (2.5) 6 13 ns 46, 52

CL = 2 tCK (2) 7.5 13 ns 46, 52













ns 35



Add ress an d cont rol input ho ld time (slow slew rate ) tIHS 0.8 ns 15



Add ress an d cont rol input setup t ime (slow slew rat e) tISS 0.8 ns 15




















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Table 20: Electrical Characteristics and Recommended AC Operating Condit ions (-6T) (cont inued)Not es: 16, 1618, 34 apply to the ent ire ta ble; Not es appea r on pa g e 35;


AC Characteristics -6T (TSOP)


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Table 21: Electr ical Characterist ics and Recomm ended AC Operat ing Condit ions (-75E)Notes: 16, 1618, 34 apply to the en t ire ta ble; Notes appea r on page 35;


AC Characteristics -75E




Clo ck cycle t ime CL = 2.5 tCK (2.5) 7.5 13 ns 46, 52

CL = 2 tCK (2) 7.5 13 ns 46, 52













ns 35



Add ress an d cont rol input ho ld time (slow slew rate ) tIHS 1 ns 15



Add ress an d cont rol input setup t ime (slow slew rat e) tISS 1 ns 15




















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Table 21: Electrical Characteristics and Recomm ended AC Operat ing Condit ions (-75E) (cont inued)Not es: 16, 1618, 34 apply to the ent ire ta ble; Not es appea r on pa g e 35;


AC Characteristics -75E


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Table 22: Electrical Characteristics and Recommended AC Operat ing Condit ions (-75Z)Notes: 16, 1618, 34 apply to the en t ire ta ble; Notes appea r on page 35;


AC Characteristics -75Z




Clo ck cycle t ime CL = 2.5 tCK (2.5) 7.5 13 ns 46

CL = 2 tCK (2) 7.5 13 ns 46








WRITE com ma nd -to -first DQS la tching tra nsition tDQSS 0.75 1.25 tCK










Add ress an d cont rol input setup t ime (slow slew rat e) tISS

1 ns 15












Averag e pe riod ic refresh interval (Auto mot ive) tREFIAT 1.95 s 24AUTO REFRESH com ma nd pe riod tRFC 75 ns 50








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Table 22: Electrical Characteristics and Recomm ended AC Operat ing Condit ions (-75Z) (cont inued)Not es: 16, 1618, 34 apply to the ent ire ta ble; Not es appea r on pa g e 35;


AC Characteristics -75Z


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Table 23: Electrical Characteristics and Recommended AC Operating Condit ions (-75)Notes: 16, 1618, 34 apply to the en t ire ta ble; Notes appea r on page 35;


AC Characteristics -75




Clo ck cycle t ime CL = 2.5 tCK (2.5) 7.5 13 ns 46

CL = 2 tCK (2) 10 13 ns 46








WRITE com ma nd -to -first DQS la tching tra nsition tDQSS 0.75 1.25 tCK










Add ress an d cont rol input setup t ime (slow slew rat e) tISS

1 ns 15












Averag e pe riod ic refresh interval (Auto mot ive) tREFIAT 1.95 s 24AUTO REFRESH com ma nd pe riod t rFC 75 ns 50


DQS read preamble tRPRE 0.9 1.1 t CK 44


ACTIVE ba nk a to ACTIVE ba nk b com ma nd tRRD 15 ns


DQS write preamble tWPRE 0.25 t CK


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DQS write postamb le t WPST 0.4 0.6 tCK 20

Write recovery time t WR 15 ns





Table 24: Input Slew Rate Derat ing Values for Addresses and CommandsNote: 15 applies to the ent ire table; Notes appea r on page 35;


Speed Slew Rate tIS t IH Units

-75Z/-75E 0.500 V/ns 1.00 1 ns

-75Z/-75E 0.400 V/ns 1.05 1 ns

-75Z/-75E 0.300 V/ns 1.10 1 ns

Table 25: Input Slew Rate Derating Values for DQ, DQS, and DMNote: 32 applies to the ent ire table; Notes appea r on page 35;


Speed Slew Rate tDS tDH Units

-75Z/-75E 0.500 V/ns 0.50 0.50 ns

-75Z/-75E 0.400 V/ns 0.55 0.55 ns-75Z/-75E 0.300 V/ns 0.60 0.60 ns

Table 23: Electrical Characteristics and Recommended AC Operat ing Condit ions (-75) (cont inued)Not es: 16, 1618, 34 apply to the ent ire ta ble; Not es appea r on pa g e 35;


AC Characteristics -75


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Notes1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conductedat nominal reference/supply voltage levels, but the related specifications and the

device operation are guaranteed for the full voltage range specified.3. Outputs (except for IDD measurements) measured with equivalent load:

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environ-ment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#),and parameter specifications are guaranteed for the specified AC input levels undernormal use conditions. The minimum slew rate for the input signals used to test the

device is 1 V/ns in the range between VIL(AC) and VIH(AC).5. The AC and DC input level specifications are as defined in the SSTL_2 standard (that

is, the receiver will effectively switch as a result of the signal crossing the AC inputlevel and will remain in that state as long as the signal does not ring back above[below] the DC input LOW [HIGH] level).

6. All speed grades are not offered on all densities. Refer to page 1 for availability.

7. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations inthe DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may notexceed 2% of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC errorand an additional 25mV for AC noise. This measurement is to be taken at the nearest

VREF bypass capacitor.

8. VTT is not applied directly to the device. VTT is a system supply for signal termination

resistors, it is expected to be set equal to VREF, and it must track variations in the DClevel of VREF.

9. VID is the magnitude of the difference between the input level on CK and the inputlevel on CK#.

10. The value of VIXand VMP is expected to equal VDDQ/2 of the transmitting device andmust track variations in the DC level of the same.

11. IDD is dependent on output loading and cycle rates. Specified values are obtainedwith minimum cycle times at CL = 3 for -5B; CL = 2.5, -6/-6T/-75; and CL = 2,-75E/-75Z speeds with the outputs open.

12. Enables on-chip refresh and address counters.

13. IDD specifications are tested after the device is properly initialized and is averaged atthe defined cycle rate.

14. This parameter is sampled. VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V, VREF = VSS,f= 100 MHz, TA= 25C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.2V. DM input isgrouped with I/O pins, reflecting the fact that they are matched in loading.

15. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If the slew rate isless than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each100 mV/ns reduction in slew rate from the 500 mV/ns. tIH has 0ps added, that is, itremains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -5B,-6, and -6T, slew rates must be greater than or equal to 0.5 V/ns.

Output(VOUT)

Referencepoint

50

VTT

30pF

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16. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point atwhich CK and CK# cross; the input reference level for signals other than CK/CK# isVREF.

17. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including self

refresh mode, VREF must be powered within specified range. Exception: during theperiod before VREF stabilizes, CKE < 0.3 VDD is recognized as LOW.

18. The output timing reference level, as measured at the timing reference point (indi-cated in Note 3), is VTT.

19. tHZ and tLZ transitions occur in the same access time windows as data valid transi-tions. These parameters are not referenced to a specific voltage level, but specify

when the device output is no longer driving (High-Z) or begins driving (Low-Z).

20. The intent of the Dont Care state after completion of the postamble is the DQS-driven signal should either be HIGH, LOW, or High-Z, and that any signal transition

within the input switching region must follow valid input requirements. That is, ifDQS transitions HIGH (above VIH[DC] MIN) then it must not transition LOW (below

VIH[DC] prior to tDQSH [MIN]).

21. This is not a device limit. The device will operate with a negative value, but systemperformance could be degraded due to bus turnaround.

22. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-mand. The case shown (DQS going from High-Z to logic LOW) applies when no

WRITEs were previously in progress on the bus. If a previous WRITE was in progress,DQS could be HIGH during this time, depending on tDQSS.

23. MIN (tRC or tRFC) for IDD measurements is the smallest multiple oftCK that meets theminimum absolute value for the respective parameter. tRAS (MAX) for IDD measure-ments is the largest multiple oftCK that meets the maximum absolute value for tRAS.

24. The refresh period is 64ms (commerial and industrial) or 16ms (automotive). Thisequates to an average refresh rate of 7.8125s (commercial and industrial) or 1.95us(automotive). However, an AUTO REFRESH command must be asserted at least onceevery 70.3s(commerial and industrial) or 17.55s (automotive); burst refreshing or

posting by the DRAM controller greater than 8 REFRESH cycles is not allowed.25. The I/O capacitance per DQS and DQ byte/group will not differ by more than this

maximum amount for any given device.

26. The data valid window is derived by achieving other specifications: tHP (tCK/2),tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct propor-tion to the clock duty cycle and a practical data valid window can be derived. Theclock is allowed a maximum duty cycle variation of 45/55, because functionality isuncertain when operating beyond a 45/55 ratio. The data valid window deratingcurves are provided in Figure 12 on page 37 for duty cycles ranging between 50/50and 45/55.

27. Referenced to each output group: x4 = DQS with DQ0DQ3; x8 = DQS with DQ0DQ7;x16 = LDQS with DQ0DQ7 and UDQS with DQ8DQ15.

28. This limit is actually a nominal value and does not result in a fail value. CKE is HIGHduring the REFRESH command period (tRFC [MIN]), else CKE is LOW (that is, duringstandby).

29. To maintain a valid level, the transitioning edge of the input must:

29a. Sustain a constant slew rate from the current AC level through to the target AClevel, VIL(AC) or VIH(AC).

29b. Reach at least the target AC level.

29c. After the AC target level is reached, continue to maintain at least the target DClevel, VIL(DC) or VIH(DC).

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30. The input capacitance per pin group will not differ by more than this maximumamount for any given device.

31. CK and CK# input slew rate must be 1 V/ns (2 V/ns if measured differentially).

Figure 12: Derating Data Valid Window (tQH tDQSQ)

32. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be addedto tDS and tDH for each 100 mV/ns reduction in slew rate. For -5B, -6, and-6T speed grades, the slew rate must be 0.5 V/ns. If the slew rate exceeds 4 V/ns,functionality is uncertain.

33. V DD must not vary more than 4% if CKE is not active while any bank is active.

34. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary bythe same amount.

35. tHP (MIN) is the lesser oftCL (MIN) and tCH (MIN) actually applied to the device CKand CK# inputs, collectively, during bank active.

36. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN)can be satisfied prior to the internal PRECHARGE command being issued.

37. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mVor 2.9V (+300mV or 2.9V maximum for -5B), whichever is less. Any negative glitchmust be less than 1/3 of the clock cycle and not exceed either 300mV or 2.2V (2.4V for-5B), whichever is more positive. The average cannot be below the +2.5V (2.6V for -5B)minimum.

38. Nor

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