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E C E N 5 2 6 3 D i g i t a l V L S I D e s i g n

Array Multiplier March 13, 2013 page 1 of 10

Array Multiplier

a a a a a ab b b b b b

p1p1p1p1p1p1

p2p2p2p2p2p2

longest delay

pnpnpnpnpnpn

delay ~ # digits in word

+ # partial products

# partial products can be reduced by using

radix > 2 multiplier

multiplicand

multiplier1 0 1 1 1 0

0 1 0 0 1 1

1 0 1 1 1 0

1 0 1 1 1 0

0 0 0 0 0 0

0 0 0 0 0 0

1 0 1 1 1 0

0 0 0 0 0 0

0 0 1 1 0 1 1 0 1 0 1 0

1 0 1 1 1 0

1 0 31 0 0 0 1 0 1 0

0 0 0 0 0 0

1 0 1 1 1 0

0 0 1 1 0 1 1 0 1 0 1 0

1 0 1 1 1 0

3

1 0 1 1 1 0

1 0 1 1 1 0

1 0 0 0 1 0 1 0

must pre-calculate 3x

multiplicand which

requires extra adder

radix 4

(2 bits at a time)

Could take 3 bits at time (radix 8), but need 3x, 5x, 6x, 7x multiplicand.

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Trick: recode multiplier changing all 3s to 4 - 1. This can be done with a shifter and 2s

complement hardware and does not need an extra adder.

Example

1 1 1 1 1 1 0 1 0 0 1 0

1 0 1 1 1 0

1 0 1 1 1 0

0 0 1 1 0 1 1 0 1 0 1 0

1 0 1 1 1 0(+1)(+1)(-1)

1 0 3 1 1 -1sign extension

of negative

partial product2s complement

of multiplicand

Booth algorithm replaces any string of 1s (including 3s) with single digits isolated by

strings of 0s.

01111110

10000000

00000010

10000010

Booth recoding

bibi 1 bi

0 0 0

0 1 1

1 0 1

1 1 0

(recoded)

left side of string of 1s

right side of string of 1s

(original)

Example

multiplier 0 1 0 0 1 1

assume zero

recodedmultiplier 1 1 0 1 0 1

(+1) (+1) (-1)

Now that 3s are gone, combine each pair bits into single recorded digit to reduce number

of partial products.

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Modified Booth Recoding

bi+1 bi bi-1

Booth

Recoding

bi+1 bi

Modified

Booth

Recoding

0 0 0 0 0 0

0 0 1 0 1 +1

0 1 0 1 1 +1

0 1 1 1 0 +2

1 0 0 1 0 -2

1 0 1 1 1 -1

1 1 0 0 1 -1

1 1 1 0 0 0

implemented byshift, comp, zero

See also Table 11.12, p. 481. The modified Booth recoded multiplier digits are -2, -1, 0, 1,

2 (never 3). When the multiplicand is multiplied by one of these digits to get the partial

product, the partial product is generated by a combination of shifting, complementing or

zero-ing without any extra adders.

Suppose we try to use an even higher number base to further reduce the number of partial

products. Consider base 8 which combines three binary bits into one digit which produces

only 1/3 of the original partial products. However, we must find ways to recode the base 8

digits so that there are no non-powers of 2.0 is OK1 is OK2 is OK3 = ?4 is OK

5 = ?6 = 8 - 2 is OK7 = 8 - 1 is OK

Since there is no way to recode the 3 and 5 digits, extra adders must be provided to pre-

compute multplying by these digits. See also Table 11.13, p. 484. This negates most of

the advantage of going to the higher number base. Most multiplier designs use modified

Booth recoding and multiply by two bits at a time which is what we will assume from now

on.

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Implementation

Multiplicand (A)

Partial Product GenMultiplierEncoder

multiplier(B)

MultiplierEncoder

Carry

Carry

Adder

Adder (Carry Save)

Partial Product Gen

Adder (Carry Save)

Fast Adder

Product

Note: the text in section 11.9 does not make it clear that the carry save adders and the par-

tial product generators are intermixed.

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Carry Save Adder (CSA)

FA FA FA

FA FA FA

No carry delay! (within a CSA stage)

CSA array

Fast Adder

CSA

CSA

CS CS CS CS

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Partial Product Generator

recoded digit operation

0 0 => partial product

+ 1 multiplicand => partial product

+ 2 shifted multiplicand => partial product

- 1 complemented multiplicand => partial product

- 2 shifted & complemented multiplicand => partial product

ZERO

Ai Ai-1

COMP

MUX MUXSHIFT

P.P.i P.P.i-1

The text uses a slightly different but equivalent design for the partial product generator

with different control lines in Fig. 11.80, p. 482.

Carry Generation

ZERO

COMP

SHIFT

Cin

.

two ways to get a zero p.p.p.p. bits Cin

000 0 0

111 1 1

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Multiplier Encoder

bi+1 bi bi-1 Recoded

Digit

COMP SHIFT ZERO

0 0 0 0 x x 1

0 0 1 +1 0 0 0

0 1 0 +1 0 0 0

0 1 1 +2 0 1 0

1 0 0 -2 1 1 0

1 0 1 -1 1 0 0

1 1 0 -1 1 0 0

1 1 1 0 x x 1

COMP bi 1+=

SHIFT bi

bi 1 bi bi 1+=

ZERO bi 1+ bi bi 1 bi 1+ bi bi 1 + =

This is similar to Table 11.12, p. 481 but with different control lines.

Sign Extension ProblemOur original example treated the multiplicand as unsigned so that all of the partial prod-

ucts on page 1 of these notes are positive. If we treat the multiplicand as signed, then all

of the negative multiplicands must be sign extended to give correct negative partial prod-

ucts.

1 0 1 1 1 0

0 1 0 0 1 1

1 1 1 1 1 1 1 0 1 1 1 0

1 1 1 1 1 1 0 1 1 1 00 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 0 1 1 1 0

0 0 0 0 0 0 0

1 1 1 0 1 0 1 0 1 0 1 0

signextension

regard as negative number

0 0 1 1 0 1 1 0 1 0 1 0

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The non-zero sign extension bits cause the product of signed numbers to have a different

bit pattern than the product of unsigned numbers. This is quite different than an adder

where the bit pattern of the sum is the same pattern both for signed and unsigned operands.

Whenever the sign of the partial product is negative, non-zero sign extension bits must be

added.

We can still do Booth recoding when the multiplicand is signed. In this case, the sign of

the partial product is the exclusive-or of the sign of the multiplicand and the sign of the

recoded multiplier digit. Then the partial product is sign extended as before.

0 0 0 0 0 0 0 1 0 0 1 0

1 1 1 1 1 0 1 1 1 0

1 1 1 0 1 1 1 0

1 1 1 0 1 0 1 0 1 0 1 0

1 0 1 1 1 0(+1)(+1)(-1)

We can rewrite the first non-zero sign extension as

1 0 0 0-1

1 1 1 1

where bits to the left of the dashed line are not represented in the product and can be

ignored. Using this technique, the sign extension part of the partial products for a Booth

encoded multiplier can be written as

S0 S0 S0 S0

S1 S1S1S1

Sn-1Sn-1 Sn

0 0 0(-S0)

0 0(-S1)

0(-Sn-1)

S0

S1

Sn-1

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111 1 1 1 1 adding zero

0 0 0(-S0)

0 0(-S1)

0(-Sn-1)

0 0 1 S0

+1

1 S1

1 Sn-1

+1

0 0

1-S SS0 1 1

1 0 0trick 1 - S = S



This is equivalent to the simplified sign extension in Fig. 11.82, p.483.

Partial Product Generation for Sign Extension

ZERO

COMP

SHIFT MUX

PPnPPn+1

Si

PPn-1

An-1 Sign bit ofmultiplicand

1

MUXSIGNED

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6 X 6 Signed Booth Multiplier Example

B.E.

B0B1

PPG

PPG

PPG

PPG

PPG

PPG

PPG

PPG H

A

FA

PPG

PP

G

PPG

PPG

HA

HA

HA

HA

PPG

PPG

PPG

PPG

PPG

PPG

HA

FA

FA

FA

FA

FA

0

0

LookAheadCarryAdder

P11

P10

P9

P8

97

P6

P5

P4

P3

P2

P1

P0

B.E.

B.E.

B2B3

B4B5

3 3

3

1

A5

A4

A3

A2

A1

A0

1

1

1

0

Note: unsigned multiplier has extra partial product as shown in Fig. 11.81, p. 482.

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