multi-cycle cpu organization - usc...
TRANSCRIPT
© Mark Redekopp, All rights reserved
Multi-Cycle CPU Organization
Datapath and Control
© Mark Redekopp, All rights reserved
Single-Cycle CPU Datapath
I-Cache
0
1
PC
+
Addr.
Instruc.
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
Sign
Extend
AL
U Res.
Zero
0
1
Sh.
Left
2+
D-Cache
Addr.
Read
Data
Write
Data
A
B
4
0
1
16 32
5
5
0
1
RegDst
ALUSrc
5
MemtoReg
MemWrite
MemRead
ALU control
PCSrcControl
RegWrite
ALUSrc
RegDst
MemtoReg
Branch
MemRead & MemWrite
INST[5:0]
[31:2
6]
[25:21]
[20:16]
[15:11]
[15:0
]
ALUOp[1:0]
ALUOp[1:0]
© Mark Redekopp, All rights reserved
Multicycle CPU Implementation
• Single cycle CPU sets the clock period according to the
longest instruction execution time
• Rather than making every instruction “pay” the worst
case time, why not make each instruction “pay” just for
what it uses
– Example: Pay Parking
• Parking meters: Cost proportional to time spent
• Flat fee parking lot: One price no matter the time
• Multicycle CPU implementation breaks instructions into
smaller, shorter sub-operations
– Clock period according to the longest sub-operation
• Instructions like ADD or Jump with few sub-operations
will take fewer cycles while more involved instructions
like LW will take more cycles
© Mark Redekopp, All rights reserved
Single vs. Multi-Cycle CPU
• Single Cycle CPU design makes all instructions wait for the full clock
cycle and the cycle time is based on the SLOWEST instruction
• Multi-cycle CPU will break datapath into sub-operations with the
cycle time set by the longest sub-operation. Now instructions only
take the number of clock cycles they need to perform their sub-ops.
Instruc.
Fetch
Decode
/ Reg.
Fetch
ALUMemory
Access
Write
Result
add
lw CPI=1
Instruc.
Fetch
Decode
/ Reg.
Fetch
ALUMemory
Access
Write
ResultlwRE
G.
RE
G.
RE
G.
RE
G. CPI=n
Single-Cycletime
time Multi-cycle
© Mark Redekopp, All rights reserved
Wasted
Wasted
Wasted
Single-/Multi-Cycle Comparison
In single-cycle implementations,
the clock cycle time must be set
for the longest instruction. Thus,
shorter instructions waste time if
they require a shorter delay.
In multi-cycle CPU, each
instruction is broken into separate
short (and hopefully time-
balanced) sub-operations. Each
instruction takes only the clock
cycles needed, allowing shorter
instructions to finish earlier and
have the next instruction start.
CLK
R-Type
BEQ
SW
LW
CLK
R-Type
BEQ
SW
LW
Fetch / Reg. Read /
ALU Op / Reg. Write
Fetch / Reg. Read /
Update PC
Fetch / Reg. Read /
Calc. Addr / Mem Write.
Fetch / Reg. Read / Calc. Addr. /
Mem Read / Reg. Write
FetchReg.
Read
ALU
Op
FetchReg.
Read
Update
PC
Reg.
Write
FetchReg.
Read
Calc.
Addr.
Mem
Write
FetchReg.
Read
Calc.
Addr.
Mem
Read
Reg.
Write
Next
Instruc.
Next Instruc.
Next
Instruc.
© Mark Redekopp, All rights reserved
Sharing Resources in Single-Cycle
• Single-cycle CPU
required multiple:
– Adders/ALU
– Memories (instruc. & data)
because all operations
occurred during a single
clock cycle which limited
our control of the flow of
data signalsShared
Mem.
Addr.
Dout.
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
Sign
Extend
16
5
5
0
1
RegDst
5
Control
[31:2
6]
[25:21]
[20:16]
[15:11]
[15:0
]
0
1
PC
Mem. Addr.
Din.
Mem. Write
Data
© Mark Redekopp, All rights reserved
Sharing Resources in Multicycle CPU
• Any resource needed in different clock
cycles (time steps) can be shared/re-used
– 1 ALU and 2 adders in single-cycle CPU can
be replaced by just the one ALU (& some
muxes)
– Separate instruction and data memories can
be replaced with a single memory
© Mark Redekopp, All rights reserved
Temporary Registers
• Another implication of a multi-cycle implementation is that
data may be produced in one cycle (step) but consumed
in a later cycle
• This may necessitate saving/storing that value in a
temporary register
– If the producer can keep producing across multiple cycles (i.e. is
not needed for another subsequent operation) then we can do
without the temporary register
– If the producer is needed for another operation in a subsequent
cycle, then we must save the value it produced in a temporary
register
© Mark Redekopp, All rights reserved
Temporary Registers
• If the producer can keep
producing across multiple
cycles (i.e. is not needed for
another subsequent
operation) then we can do
without the temporary
register
• If the producer is needed for
another operation in a
subsequent cycle, then we
must save the value it
produced in a temporary
register
Temporary Register not
Necessary
Temp Register Necessary
CLK
Producer
(ALU)
Consumer
(PC)
Branch Target
Branch
Target
CLK
Producer
(ALU)
Consumer
(PC)
Branch
Target
Branch
Target
Temp
Reg.
Branch
Target
Next
Value
© Mark Redekopp, All rights reserved
Instruction Register
• Do we need a register to store
instruction
– In single-cycle CPU: NO
• Separate instruction memory +
stable PC value during entire cycle
= Stable instruction value for entire
execution of instruction
– In multi-cycle CPU: YES
• Single memory may need to be
used to read or write data after
reading instruction. We must buffer
/ save the instruction somewhere
(i.e. IR)
I-Cache
PC
Addr.
Instruc.
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
Sign
Extend
16
5
5
0
1
RegDst
5
Control
[31:2
6]
[25:21]
[20:16]
[15:11]
[15:0
]
PC
Memory
Addr.
Read
Data
Write
Data
0
Ins
tru
cti
on
R
eg
.
1
Data
read/write
address
from ALU
Single-Cycle CPU Datapath
Multicycle CPU Datapath
© Mark Redekopp, All rights reserved
More on Temporary Registers
• Do temporary registers need a write
enable (i.e. do we need IRwrite
signal?
• Unless it is acceptable for the
register to be written on every clock
cycle, then we do need a write
enable
– Based on our design, we only write the
IR after the cycle we read the
instruction and not on other
cycles…thus we need an IRwrite
Instruc.
Reg.
IRW
rite
D Q
CLK
© Mark Redekopp, All rights reserved
Multi-Cycle CPU DatapathP
C
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRW
rite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
control
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
© Mark Redekopp, All rights reserved
Multi-Cycle CPU DatapathP
C
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRW
rite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2ALU
control
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
AL
US
elA
ALUSelB
PCSource
TargetWrite
IorD
RegDst
MemtoReg
© Mark Redekopp, All rights reserved
Single vs. Multi-Cycle CPU
Single-Cycle CPU Multi-Cycle CPU
Single LONG clock Several SHORT clocks
No sharing of resources Sharing resources possible
ALU & 2 separate adders Single ALU does all three jobs
Separate instruction & data memory Single unified memory
No need for any temp. register Need for temp. registers like IR
PCWrite Unneeded PCWrite Needed
Control unit not an FSM Control Unit is an FSM
© Mark Redekopp, All rights reserved
Instruction Fetch + PC Increment
PC
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRW
rite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2ALU
control
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
AL
US
elA
ALUSelB
PCSource
TargetWrite
IorD
RegDst]
MemtoReg
New PC
(PC + 4)
New PC
(PC + 4)In
str
uc
.
© Mark Redekopp, All rights reserved
R-Type ExecutionP
C
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRW
rite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2ALU
control
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
AL
US
elA
ALUSelB
PCSource
TargetWrite
IorD
RegDst]
MemtoReg
Result
Op. B
Op. A
© Mark Redekopp, All rights reserved
LW ExecutionP
C
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRW
rite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2ALU
control
0
1
2
Target
Reg.
Sh.
Left 2
[rd]
4
[rt]
[rs]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
AL
US
elA
ALUSelB
PCSource
TargetWrite
IorD
RegDst]
MemtoReg
Base RegEff. Addr.
Offset
Read Data
© Mark Redekopp, All rights reserved
SW ExecutionP
C
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRW
rite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2ALU
control
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
AL
US
elA
ALUSelB
PCSource
TargetWrite
IorD
RegDst]
MemtoReg
Base RegEff. Addr.
Offset
Write Data
© Mark Redekopp, All rights reserved
BEQ Execution Step 1P
C
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRW
rite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2ALU
control
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
AL
US
elA
ALUSelB
PCSource
TargetWrite
IorD
RegDst]
MemtoReg
Target PC
(PC+4+Offset)
PC+4
(PC was already incremented in fetch step)
© Mark Redekopp, All rights reserved
BEQ Execution Step 2P
C
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRW
rite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2ALU
control
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
AL
US
elA
ALUSelB
PCSource
TargetWrite
IorD
RegDst]
MemtoReg
PCWriteCond
Target PC
(PC+4+Offset)
Op. A
Op. B
© Mark Redekopp, All rights reserved
Jump ExecutionP
C
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRW
rite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2ALU
control
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
AL
US
elA
ALUSelB
PCSource
TargetWrite
IorD
RegDst]
MemtoReg
Jump PC
(PC[31:28] || IR[25:0] || 00)
© Mark Redekopp, All rights reserved
Controlling the Datapath
• Now we need to implement the logic for
the control signals
• This will require an FSM for our multi-cycle
CPU (since we will have sub-operations or
steps to execute each instruction)
© Mark Redekopp, All rights reserved
Multi-Cycle CPU
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
© Mark Redekopp, All rights reserved
Control Signal ExplanationSignal Name Effect when Deasserted Effect when Asserted
MemRead None Read data from memory
MemWrite None Write to data memory
ALUSelA Select the PC value Selects the rs register value
RegDst Register to write is specified by rt
field
Register to write is specified by rd
field
RegWrite None Register file will write the specified
register
MemtoReg Reg. file write data comes from
ALU
Reg. file write data comes from
memory read data
IorD PC is used as address to
memory
ALU output is used as address to
memory
IRWrite None Memory read data is written to IR
© Mark Redekopp, All rights reserved
Control Signal Explanation
Signal Name Value Effect
ALUSelB
00 Selects the rt register value
01 Selects the constant 4
10 Selects the sign extended lower 16-bits of IR
11 Selects the sign extended and shifted lower 16-bits of IR
ALUOp
00 ALU performs an ADD operation
01 ALU performs a SUB operation
10 The function code field of instruction will determine ALU op.
PCSource
00 Selects the ALU output to pass back to the PC input
01 Selects the target register value to pass back to the PC input
10 Selects the jump address value to pass back to the PC input
© Mark Redekopp, All rights reserved
Generating a State Diagram
• Start with states to fetch instruction, increment PC, &
decode it
– These are common to any instruction because at this point we
don’t know what instruction it is
• Once decoded use a separate sequence of states for
each instruction
– One state for each sub-operation of each instruction
• Goal is to find state breakdown that leads to short, equal
timed steps
– Short: Shorter the time delay of the step => Faster clock rate
– Equal-timed: Clock cycle is set by the slowest state; if the
delays in states are poorly balanced, some states will have to
pay a longer delay even though they don’t need it
© Mark Redekopp, All rights reserved
Multi-cycle CPU FSMMemRead
ALUSelA=0
IorD=0
IRWrite
ALUSelB=01
ALUOp=00
PCSource=00
PCWrite
ALUSelA=0
ALUSelB=11
ALUOp=00
TargetWrite
ALUSelA=1
ALUSelB=10
ALUOp=00
IorD=1
MemRead
ALUSelA=1
ALUSelB=10
ALUOp=00
IorD=1
MemtoReg=1
RegDst=0
RegWrite
MemRead
ALUSelA=1
ALUSelB=10
ALUOp=00
IorD=1
MemWrite
ALUSelA=1
ALUSelB=10
ALUOp=00
IorD=1
ALUSelA=1
ALUSelB=00
ALUOp=10
ALUSelA=1
ALUSelB=00
ALUOp=10
RegDst=1
MemtoReg=0
RegWrite
ALUSelA=1
ALUSelB=00
ALUOp=01
PCWriteCond
PCSource=01
PCWrite
PCSource=10
(Op=‘BEQ’)
(Op=‘JMP’)
Mem. Addr.
Computation Memory
Access
Write-back
Write-back
Execution
Branch
Completion
Jump
Completion
Instruc. Fetch Instruc. Decode +
Reg. Fetch
01
2
Memory
Access
3
4
5 7
6 8 9
Reset
© Mark Redekopp, All rights reserved
State 0 = Fetch
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
MemRead
ALUSelA=0
IorD=0
IRWrite
ALUSelB=01
ALUOp=00
PCSource=00
PCWrite
© Mark Redekopp, All rights reserved
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
State 1 = Decode / Reg. FetchALUSelA=0
ALUSelB=11
ALUOp=00
TargetWrite
© Mark Redekopp, All rights reserved
Questions
• After state 0 (fetch) we store the instruction in
the IR, after state 1 when we fetch register
operands do we need to store operands in temp
reg’s (e.g. AReg, BReg)?
• Do we need RegReadA, RegReadB control
signals?
© Mark Redekopp, All rights reserved
LW/SW State 2
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
ALUSelA=1
ALUSelB=10
ALUOp=00
IorD=1
© Mark Redekopp, All rights reserved
LW State 3
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
MemRead
ALUSelA=1
ALUSelB=10
ALUOp=00
IorD=1
© Mark Redekopp, All rights reserved
LW State 4
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
MemRead
ALUSelA=1
ALUSelB=10
ALUOp=00
IorD=1
MemtoReg=1
RegDst=0
RegWrite
© Mark Redekopp, All rights reserved
SW State 5
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
MemWrite
ALUSelA=1
ALUSelB=10
ALUOp=00
IorD=1
© Mark Redekopp, All rights reserved
R-Type State 6
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
ALUSelA=1
ALUSelB=00
ALUOp=10
© Mark Redekopp, All rights reserved
R-Type State 7
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
ALUSelA=1
ALUSelB=00
ALUOp=10
RegDst=1
MemtoReg=0
RegWrite
© Mark Redekopp, All rights reserved
Questions
• For R-Type or LW…
– Can we turn on RegWrite one state earlier?
– Can we set the RegDst signal earlier?
© Mark Redekopp, All rights reserved
BEQ State 8
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
ALUSelA=1
ALUSelB=00
ALUOp=01
PCWriteCond
PCSource=01
© Mark Redekopp, All rights reserved
Jump State 9
Memory
Addr.
Read
Data
Write
Data
Me
mR
ea
d
0
1
Me
mW
rite
Instruc.
Reg.
Instruc[31:26]
Instruc[25:0]
IRWrite
Register File
Read
Reg. 1 #
Read
Reg. 2 #
Write
Reg. #
Write
Data
Read
data 1
Read
data 2
0
1
0
1
AL
U Res.
Zero
0
1
0
1
2
3
Sign
Extend
Sh.
Left 2
ALU
Ctrl
0
1
2
Target
Reg.
Sh.
Left 2
[15:11]
4
[20:16]
[25:21]
[15:0]
[5:0]
Reg
Write
PC[31:28]
16 32
26 30
32
PC
Wri
te
[5:0
]
Me
mto
Reg
Reg
Dst
IorD
ALUSelA
ALUSelB
ALUOp
TargetWrite
PCSource
PC
PCWrite
PCWriteCond
Zero
Control
Unit
PCWrite
PCSource=10