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XilinxMulti-CyclePathTutorial

byEkawat“Ice”Homsirikamol

ver1.0

May3,2010

Bydefault,thesynthesisandimplementationtoolstreatallpathsassinglecyclepaths,i.e.,any

combinationalpathbetweentworegistersintheimplementedcircuitisassumedtohaveapropagation

delayshorterthanoneclockcycle.Hence,ifyouhaveacombinationalpathbetweentworegistersthat

takes more than one clock cycle to propagate through, a constraint file is required. Without the

constraint file the toolwill not knowwherethemulti-cyclepath islocated. For Xilinx,wecan either

specifythesepathsforsynthesis(usingUCFfile)orforimplementation(usingXCFfile).Allconstraints

appliedduringsynthesiswillpropagatetoimplementation.Thefulldetailsonhowtocreateaconstraint

file can be found in theConstraints Guide, http://www.xilinx.com/support/documentation/dt_ise11-

1.htm.

Inthistutorial,wewillshowhowtocreateaconstraintfileforamulti-cyclepathusingXilinxISE

v.11.1.WeassumetheuseofSpartan3FPGA(xc3s50pq208-5).Anexampleusedinthistutorialisthe

radix-2 sequential multiplier

based on the shift/add

algorithm, right-shift version

with carry save adder (CSA).

Sourcecodesforthisexample

areprovidedwiththistutorial.

The circuit contains two

critical paths: single-cycle

path, passing through the

carrysaveadderandomitting

the carry propagate adder,

andamulti-cyclepathpassing

through both the carry save

adderandthecarrypropagate

adder. Compared to the

version based on the carry

propagate adder only, the

execution time is reduced

considerably,especiallyforthe

large values of the operand

size k. In this example, we

assumek=64. Figure1:Datapath

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BasicImplementation

Beforeweproceedanyfurther,letusmakesurethatthecriticalpathisalwaysincludedinthePost-PAR

statictimingreport.Tomakeithappen,selectthe" ProcessProperties"of"ImplementDesign->Place&

Route->GeneratePost-Place&RouteStaticTiming"locatedinsidetheProcesseswindow,underDesign

tab.Then,specifythefollowingsettings.

Figure2:Post-PARStaticTimingReportSettings

Oncedone,youcan implement thedesignand viewthe results.Belowisaportionofthegenerated

Post-PARStaticTimingReport:

Figure3:Post-PARStaticTimingReport

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Similarly,thePARreportwillshowthefollowingresultasyourclockspeed:

Figure4:PARReportwithoutUCFfile

Asexpected,thecriticalpathinPost-PARStaticTimingReportgoesthroughtheCPAunit.However,this

isnottheactualcriticalpathforthiscircuit.Hence,thetoolneedstobeinformedthatthepaththat

goesthroughtheCPAisallowedtotakemultipleclockcycles.Theexactnumberofclockcyclesdepends

on the operand size, FPGA device used for implementation, and other factors. This number can be

determined,forexample,by firstimplementingthecircuitwithamulti-cyclepath,thenwithoutmulti-

cycle path, and then computing the ratio of the obtained clock periods, and rounding it up to the

nearestinteger.

ConstraintFileCreation

Letusnowtrytocreateaconstraintfiletospecifythemulti-cyclepath.First,goto "ConstraintsEditor"

under"Tools"tab.InsideConstraintsEditor ,createatimingconstraintfor"ClockDomains"bygoingto

"TimingConstraints->ClockDomains" locatedinside"ConstraintType" window.Then,specifytheclock

periodasshownbelow:

Figure5:ClockPeriod

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Thetoolwilltrytooptimizetheclknetbasedonthegiventimeperiod.Then,wewillneedtospecifythe

exceptionpath.Thiscanbedonebynavigatingto"TimingConstraints->Exceptions->Paths" .Insidethe

PathExceptionspopup,wewillgiveTIMESPECnameasTS_multipath.Fromgroupremainsdefaultas All

FlipFlops.Thisfieldtellsthetoolwherethebeginningofthepathislocated.Then,expandthe Through

 pointsbyselectingtheplussignandcreatinganewthroughpointconstraint.Thisstepwilltellthetools

whichpath needs to be considered as amulti-cyclepath. If Through Point is omitted, the tool will

assume that all paths starting from the source and ending with the destination are all exceptions.

Referringtothesourcecode,the addout  net isthemulti-cyclepathsignal.Wecanselectthisnetby

specifyingtheThroughPointsasshownbelow:

Figure6:ThroughPoints

Then,underTogroup,thedestinationmustbeselected.Inourcase,thedestinationis ppregister.We

cancreatethedestinationgroupbyselectingtheCreatebuttonandfillingthepopupasshownbelow:

Figure7:Togroups

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Again,aFilterisusedtocreatethegroup.YoucanalsotrycreatingthegroupwithoutusingtheFilter,

buttheresultingUCFfilewilllookmuchmessierandthedesignwillnotbeflexibleasthenetsarefixed.

Hence,ifadesignsizeischanged,thisUCFfilemaynotbefunctioningcorrectly.

Whendone,selectConstraintTypeas”RelativetootherpathTIMESPEC"withReferenceTIMESPEC as

TS_clk,withamultiplyfactorof2.ThefinalPathExceptionsshouldlooklikethoseshowninthebelowfigure:

Figure8:FinalPathExceptions

PressOK ,thennavigatetoTimingConstraintsunderConstraintTypewindow.Youwillseethecode

generatedinsideyourUCFfileasshownbelow:

Figure9:FinalUCFfile

Thelinesnumber1-3specifythegroupnamesandtheirassociatednetsandinstances.Linenumber4

istellingthetooltooptimizefortheclockperiodequalto6.5nswiththe50%dutycycle.Linenumber5

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tellsthatanypathstartingfromanyflipflopthatgoesthrough"addout"signalandendingwiththe"pp"

groupcanhavethecriticalpathequaltotwotimestheclockperiod.Savetheconstraintfilebyusing

"ctrl+s"keyonyourkeyboard.Theconstraintfileisnowreadyforimplementation.

DesignOptimization

ImplementthedesignwiththeUCFfile.Oncedone,youshouldseethatthePARresultfilecontainsthe

followingsummary:

Figure10:PARresultwithUCF(TS_clk=6.5ns)

AsopposedtoimplementationwithoutUCFfile(Figure4),wecannowseetwoseparateresultsforeach

ofourconstraints.ClockpathwithoutCPAandwithCPAare5.583nsand12.403ns,respectively.Inthis

case, the tool tries to optimize thedesign for thebasic clock period 6.5 ns, and optimize the path

throughCPAtothedelaysmallerthantwicetheclockperiod.Notethatwedonotneedtosetourclock

period to5.583nswhenweactually implement thedesignonFPGA. Infact, ifweuse thedesignon

FPGAwiththe aboveclock period, the designwillprobablyfailto operatecorrectly astheminimum

delayofthemulti-cyclepathis12.403ns;whichisbiggerthantwicetheclockperiod.Theresultsshown

abovearetheminimumpossiblevaluesforeachpathseparately.Wewillneedtoselectanappropriate

valueforourclockwhentheaboveconstraintsaretakenintoconsideration.Thebestcourseistouse

theclockperiodasspecifiedinsidetheUCFfileortomodifytheconstraintfilesothetoolscanoptimize

thepathaccordingly.

Letustrytooptimizethepath.Again,weneedtogobackandeditthetimingconstraintforourclock

domainfromtheconstrainteditor.Thevalueshouldbesetfor5ns.Afterre-implementingthedesign,

youshouldreceivethefollowingresult:

Figure11:PARresultwithUCF(TS_clk=5.0ns)

Theresultsdonotmeetthetimingrequirement.Whenconstraintisnotmet,timingscoreisnotequal

to0.Letusrelaxourrequirementandimplementthedesignfor5.2ns.

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Figure12:PARresultwithUCF(TS_clk=5.2ns)

Allconstraintsaremetfortheclockperiodof5.2ns.Thesestepscanberepeateduntilanoptimalresult

isreached.

Letuslookattheimprovementofourcircuit’slatencywhenamulti-cyclepathisspecified.Fork=64,

thetotalnumberofclockcyclesrequiredwithoutmulti-cyclepathis128.Whenamulti-cyclepathis

specified,thetotalnumberofclockcyclesrequiredis127+2=129.Thetotallatencieswithandwithout

multi-cyclepathare5.2*129=670.8nsand 10.943*128=1400.7 ns. Theperformanceof the circuitwithamulti-cyclepathishigherby108%!

CriticalPathVerification

Intheprevioussection,wehavelearnedhowtospecifyamulti-cyclepath.Buthowcanweverifythat

thecriticalpathwereceivedistheonethatweexpected?Inamorecomplexcircuit,thereisalwaysthe

possibilitythatwemightmisssomethroughpoints.LookingatthePost-PARStaticTimingReportfrom

ISE,thereportdoesnotshowanyinformationonthemulti-cyclepath.Infact,itonlyshowsthesame

criticalpathevenwhenUCFfileisspecified.

Toobtainthecriticalpathinformation,wewillneedtoopentheTimingAnalyzerprogram.Thisprogram

isnormallylocatedinthefollowinglocation"StartMenu(Windowsbutton)->Programs->Xilinx->ISE->

 Accessories->TimingAnalyzer".Then,openourdesignbychoosing"File->OpenDesign"andselect

top_mult.ncdfromtheISEproject'sworkspace,top_mult.pcf shouldbeselectedautomatically.Next,

selecttheUCFfile,top_mult.ucf,underUserconstraintsfileandpressOK .Select"Timing->Run

 Analysis"andanalyzeagainst"designtimingconstraint" .UnderTimingConstrainttab,youwillseethat

thetwoconstraintsareselectedforanalyzing.ThenmakesurethatReportOptionstabcontainthe

followingsettingssothatthecriticalpathisgenerated:

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Figure13:ReportOptionsofTimingAnalyzer

PressOK.

Figure14:Post-PARStaticTimingReportofTimingAnalyzer(TS_clkconstraint)

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Lookingatthegeneratedtimingreport,wecanseethatthecriticalpathfortheTS_clkperioddoesnot

anylongergothroughtheCPAunit.ThepaththatgoesthroughtheCPAunitisTS_multipath,whichis

whatweexpected.