multiple-choice questions (mcq) examination … · 2018-02-21 · demo-examination test and...

University of Duisburg-Essen

Prof. Dr.-Ing. Axel Hunger Institute of Computer Engineering

WS 2017 / 2018

DEMO-EXAMINATION Test and Reliability of Digital Systems Page: 1 of 18

Name Matriculation number Type

MULTIPLE-CHOICE QUESTIONS (MCQ) EXAMINATION

DURATION: 120 MINUTES

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Solution approaches are not assessed.

For each subtask there is only one correct solution.

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Mark the appropriate box(es) on the solution sheet! Any answer on the ASSIGNMENT SHEETS will NOT be considered.

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Return everything, i.e. assignment sheets, solution sheet and any additional sheets - used and un-used. Only exams that are returned completely will be assessed.

FILL-IN YOUR NAME AND MATRICULATION NUMBER ON THE ASSIGNMENT SHEET AND THE SOLUTION SHEET!



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(4 Points)

1.1 Which of the following is true?

A: The occurrence of a fault results in a failure.

B: Weibull distribution properly models all three phases of the bathtub curve.

C: Path sensitization works only, when we consider one path at a time.

D: System-level redundancy is always hot redundancy.

E: Majority voting is a concept to implement a non-redundant system.

F: None of these.

1.2 Which of the following is true?

G: We use test generation methods to propagate a fault to the primary input of a circuit.

H: A Markoff Chain is used to determine state transitions of a given system with given failure- / repair-rates.

I: A parallel system is also known as a n-out-of-n system.

J: A Reliability Block Diagram visualizes the electric configuration of a system.

K: Boolean Difference is a method which requires analysis of a circuit structure.

L: None of these.



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(11 Points)

2.1 Given is the reliability block diagram shown in figure 2-1. The RBD is composed of identical and independent components. Each component has the same reliability R. For a single component, tm represents the average life time.

Fig. 2-1: Reliability circuit diagram

What is the reliability at the average life time tm of the circuit shown in figure 2-1? (Rounded mathematically to the 2nd decimal place).

A: R(tm) = 0,49 B: R(tm) = 0,69 C: R(tm) = 0,28

D: R(tm) = 0,37 E: R(tm) = 0,76 F: None of these.



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2.2 Given are the graphs shown in Figure 2-2. Each graph represents one of the reliability functions of configurations Co to CIII. Each configuration is composed of identical and independent components. Each component has the same reliability R. For a single component, tm represents the average life time. The graph C0 in Figure 2-2 illustrates the reliability function for configuration C0 and is only for comparison (not part of the task). Which configuration CI to CIII represents the shown graph?

Graph 2-2

G: CI represents the graph. H: CII represents the graph. I: CIII represents the graph.

J: None of these.



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(19 Points)

3.1 Given is a repairable system with 3 components and the following attributes:

System 1 can fail with the rate λ1, system 3 can fail with the rate λ3.

System 2 can only fail individually with the rate λ2.

System 3 can only fail after system 2 failed or as a result of a common mode error with system 1. The additional failure probability of the common mode error is PCM.

Each system can only be repaired individually. The repair rates are μx with x=system number.

System 2 can only be repaired if system 3 is functional.

System 1 cannot be repaired if system 2 or 3 is not functional.

Which of the following Markoff-chains represent the described system? (Definition: State Bx = System x is functional, State Ax = System x is non-functional)

A:

B:

C:

D:

E: None of these.



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3.2 Given is the Markoff-chain shown in figure 3-1 and the associated system state table shown in figure 3-2. (Definition: State Bx = System x is functional, State Ax = System x is non-functional, λx = failure rate of system x, μx = repair rate of system x, PCM,X = Common Mode Error).

B1 ʌ B2 ʌ B3 = MZ0

A1 ʌ B2 ʌ B3 = MZ1

A1 ʌ A2 ʌ B3 = MZ2

A1 ʌ A2 ʌ A3 = MZ3

B1 ʌ A2 ʌ B3 = MZ4

B1 ʌ A2 ʌ A3 = MZ5

Fig. 3-1: Markoff-chain Fig. 3-2: System States

Which of the following statements, regarding the Markoff-chain from Figure 3-1 is true?

F: System 1 can only break down individually.

G: System 1 can only break down as a result of a common mode error.

H: System 1 can be repaired individually with no restrictions.

I: System 1 can only be repaired if system 2 is working.

J: None of these.


K: System 2 can only break down individually.

L: System 2 can break down individually or as a result of a common mode error.

M: System 2 can only break down as a result of a common mode error or follow up error.

N: System 2 can only be repaired individually with no restrictions.

O: None of these.


P: System 3 can only break down individually.

Q: System 3 can only break down as a result of a common mode error.

R: System 3 can break down as a result of a common mode error or follow up error.

S: System 3 can only be repaired if system 2 is working.

T: None of these.



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3.3 Given is the Markoff-chain shown in figure 3-3. The associated failure and repair rates are given as following:

Failure rates: λx = 5*10-3 h-1 with x ϵ (1,2,3)

Repair rates: μy = 3*10-3 h-1 with y ϵ (1,2,3)

Probability of a common mode error: PCM = 0.2

Fig. 3-3: Markoff-chain

What is the probability of State MZ6 at t1 = 1 hour after t0 for the Markoff state diagram shown in figure 3-3, with t0 = time when the system is initialized the first time[Rounded to the ninth decimal number)?

U: P(MZ6, t1) ≈ 5.125 * 10-6 V: P(MZ6, t1) ≈ 1.822 * 10-6

W: P(MZ6, t1) ≈ 1.827 * 10-6 X: P(MZ6, t1) ≈ 5.1 * 10-6

Y: P(MZ6, t1) ≈ 25.125 * 10-6 Z: None of these.



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(18 Points)

Given is a logical circuit for realizing function Z(x1, x2, x3) [See fig. 4-1]. The (incomplete) fault table excerpt given in figure 4-2 needs to be completed in order to analyze single stuck-at faults of the circuit. Note that the stuck at fault error at the output Z is ignored.

Fig. 4-1: Logical circuit

Input and fault free output Output Z under condition of a single stuck-at-fault (sa0 / sa1)

Testpattern X1 X2 X3 Z X1|sa0 X1|sa1 X2|sa0 X2|sa1 X3|sa0 X3|sa1 y1|sa0 y1|sa1 y2|sa0 y2|sa1

TP1 0 0 0 0 0 0 0 0 1 0 0 1

TP2 0 0 1 1 1 1 1 1 0 0 1

TP3 0 1 0 1 0 0 1 1 0 1 0 1

TP4 0 1 1 1 1 0 1 1 1 0 1 1

TP5 1 0 0 0 0 0 0 0 1 0 0

TP6 1 0 1 1 1 1 1 0 1 0 1 1

TP7 1 1 0 0 1 0 0 0 0 1 0 0

TP8 1 1 1 0 0 1 0 0 0 0 1 0

Fig. 4-2: (Incomplete) fault table

4.1 How many fault equivalency classes can be formed from the stuck at fault errors in the table from figure 4-2.

A: 5 fault equivalency classes B: 6 fault equivalency classes

C: 7 fault equivalency classes D: 8 fault equivalency classes

E: None of these.



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Given is a logical circuit for realizing function Z(x1, x2, x3) [See fig. 4-3]. The fault table excerpt given in figure 4-4 represents the output for single stuck-at faults of the circuit. Note that the stuck at fault error at the output Z is ignored.


Input and fault free output Output Z under condition of a single stuck-at-fault (sa0 / sa1)

Test X1 X2 X3 Z X1|sa0 X1|sa1 X2|sa0 X2|sa1 X3|sa0 X3|sa1 y1|sa0 y1|sa1 y2|sa0 y2|sa1 y3|sa0 y3|sa1

TP1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1

TP2 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1

TP3 0 1 0 1 1 1 0 1 1 0 1 1 0 1 0 1

TP4 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1

TP5 1 0 0 1 0 1 1 1 1 0 1 1 0 1 0 1

TP6 1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 1

TP7 1 1 0 1 1 1 1 1 1 0 1 1 0 1 0 1

TP8 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1

Fig. 4-4: Fault table for circuit from figure 4-3

4.2 How many fault equivalency classes can be formed from the stuck at fault errors in the table from figure 4-4.

F: 4 fault equivalency classes G: 7 fault equivalency classes

H: 8 fault equivalency classes I: 9 fault equivalency classes

J: None of these.

4.3 Which of the following fault functions belong to the fault table from figure 4-4.

K: 𝑥2 ∗ 𝑥3 L: 𝑥1 ∗ (𝑥2 + 𝑥3)

M: 𝑥3 ∗ (𝑥1 + 𝑥2) N: 𝑥1 + 𝑥2

O: None of these.



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4.4 Which of the following set of test patterns fulfill the criteria for the minimal test pattern set to the fault table from figure 4-4.

P: TPmin = (TP1,TP2,TP6,TP7,TP8) Q: TPmin = (TP1,TP3,TP5,TP6)

R: TPmin = (TP1,TP3,TP6,TP7) S: TPmin = (TP1,TP2,TP4,TP5,TP6,TP8)

T: The minimal Test set contains every TP from Figure 4-3

U: None of these.

4.5 Which errors of the fault table from figure 4-4 can be found by diagnostic testing?

V: x1|sa0, x2|sa0 & y2|sa1 W: x1|sa0, x2|sa0 & y1|sa1

X: x1|sa0 & x2|sa0 Y: x1|sa0, x2|sa0, x1|sa1 , x2|sa1 & y2|sa1

Z: None of these.



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(14 Points) Consider the logical circuit in Figure 5.1 for realizing function Z(x1,x2,x3).


5.1 Which of the following logical functions is the result of the Boolean difference 𝛿𝑍

𝑥2 for the

circuit shown in figure 5-1?

A: 𝑥1 + 𝑥3 ∗ 𝑥1 B: 𝑥1 + 𝑥3 C: 𝑥2 ∗ 𝑥3

D: 𝑥1 ∗ 𝑥3 + 𝑥3 E: 𝑥1 + 𝑥3 F: 𝑥2 + 𝑥3 + 𝑥1

G: None of these.

5.2 Which of the following logical functions is the result of the Boolean difference 𝛿𝑍

𝑥3 for the

circuit shown in figure 5-1?

H: (𝑥2

+ 𝑥1) ∗ 𝑥1 I: 𝑥2 + 𝑥1 J: 𝑥2 ∗ 𝑥1

K: 𝑥2 ∗ 𝑥3 L: 𝑥2 + (𝑥1 ∗ 𝑥2) M: 𝑥2 + 𝑥3 + 𝑥1

N: None of these.

5.3 Which of the following test patterns qualifies for testing the primary input x1 of the circuit shown in figure 5-1 for single stuck at faults?

O: 𝑥1 𝑥2 𝑥3

0 1 0

P: 𝑥1 𝑥2 𝑥3

1 1 0

Q: 𝑥1 𝑥2 𝑥3

1 0 1

R: 𝑥1 𝑥2 𝑥3

0 0 1

S: 𝑥1 𝑥2 𝑥3

1 1 1

T: 𝑥1 𝑥2 𝑥3

1 0 0

U: None of these.



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(13 Points)

Consider the logical circuit shown in figure 6.1

Fig. 6.1: Logical circuit

6.1 According to SCOAP, regarding y3, which of the following is true?

A: COY(y3) = 2 B: COY(y3) = 3 C: COY(y3) = 4

D: COY(y3) = 5 E: COY(y3) = 6 F: COY(y3) = 7

G: None of these.


H: CCY0(y3) = CCY0(y2) + CCY0(x3) + 1. I: CCY0(y3) = CCY1(y1) + CCY0(x3) + 1.

J: CCY0(y3) = CCY1(y2) + CCY1(x2) + 1. K: CCY0(y3) = CCY0(y3) + CCY0(x3) + 1.

L: CCY0(y3) = CCY0(x1) + CCY0(x2) + 1. M: CCY0(y3) = CCY1(x1) + CCY1(x3) + 1.

N: None of these.


O: CCY1(Z) = 2 P: CCY1(Z) = 3 Q: CCY1(Z) = 4

R: CCY1(Z) = 5 S: CCY1(Z) = 6 T: CCY1(Z) = 7

U: None of these.



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(15 Points)

Consider the logical circuit in Figure 7-1 for realizing function Z(x1, x2, x3, x4).


7.1 Which of the following tables represent the result of a path sensitization for a single stuck at one fault at the internal node y2 (y2|sa1), from the circuit shown in figure 7-1?

A: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

0 0 0 1 1 1 0 0 1 1

B: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

1 0 0 0 1 1 1 1 1 0

C: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

0 0 1 1 1 1 1 1 1 0

D: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

1 1 1 1 0 0 1 1 1 0

E: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

0 1 0 1 1 0 0 0 1 1

F: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

0 0 0 0 1 0 0 0 0 0

G: Due to collision, no test pattern can be found H: None of these.

7.2 Which of the following tables represent the result of a path sensitization for a single stuck at zero fault at the internal node y1 (y1|sao), from the circuit shown in figure 8-1?

I: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

0 0 1 1 1 1 1 1 1 0

J: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

0 0 0 0 0 0 0 0 0 0

K: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

0 0 1 1 1 1 0 1 1 1

L: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

0 1 1 1 0 0 1 1 1 1

M: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

0 1 0 1 1 0 0 1 1 0

N: x1 x2 x3 x4 y1 y2 y3 y4 y5 Z

1 1 1 1 1 1 1 1 1 0

O: Due to collision, no test pattern can be found P: None of these.



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Consider the logical circuit in Figure 7-1 for realizing function Z(x1, x2, x3, x4, x5).


7.3 Which of the following tables represent the result of a path sensitization for a single stuck at one fault at the primary input x2 (x2|sa1), from the circuit shown in figure 7-2?

Q: x1 x2 x3 x4 x5 y1 y2 y3 y4 y5 y6 y7 Z

1 0 0 1 1 1 1 0 1 0 0 0 1

R: x1 x2 x3 x4 x5 y1 y2 y3 y4 y5 y6 y7 Z

1 0 0 1 1 0 1 0 0 1 0 1 1

S: x1 x2 x3 x4 x5 y1 y2 y3 y4 y5 y6 y7 Z

0 0 0 1 1 1 1 0 1 0 0 0 1

T: x1 x2 x3 x4 x5 y1 y2 y3 y4 y5 y6 y7 Z

1 0 1 1 0 1 0 1 0 0 1 1 0

U: x1 x2 x3 x4 x5 y1 y2 y3 y4 y5 y6 y7 Z

0 0 0 1 1 1 1 1 0 1 1 1 0

V: Due to collision, no test pattern can be found

W: None of these.



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(16 Points)

Consider the logical circuit in Figure 8.1 for realizing function Z(x1, x2, x3, x4).

Fig. 8.1: Logical circuit

8.1 Which of the following general test patterns sets represent the complete result of a D-algorithm analysis of a single stuck at fault at x3?

A: x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

0 1 D X 0 1 �̅� 1 0 1 D 0 0 1 �̅� 0

B: x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

0 1 D X 0 1 �̅� 1 0 1 D 0

C: x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

X 1 D X X 1 �̅� 1 X 1 D 0 X 1 �̅� 0

D: x1 x2 x3 x4

& x1 x2 x3 x4

0 0 D 1 0 0 �̅� 1

E: x1 x2 x3 x4

& x1 x2 x3 x4

0 1 D X 0 1 �̅� 1

F: x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

0 0 D X 0 0 �̅� 0 0 1 D X

G: Due to collision, no test pattern can be found

H: None of these.



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8.2 Which of the following general test patterns sets represent the complete result of a D-algorithm analysis of a single stuck at fault at x1?

I: x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

�̅� 1 0 0 �̅� 1 0 0 �̅� 1 0 0 �̅� 1 0 0

J: x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

D 1 1 0 �̅� 1 1 0 D 1 0 0

K: x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

D 1 1 0 �̅� 1 1 0 D 1 1 1 �̅� 1 1 1

L: x1 x2 x3 x4

& x1 x2 x3 x4

�̅� 1 1 1 D 1 1 1

M: x1 x2 x3 x4

& x1 x2 x3 x4

�̅� 0 1 0 D 0 1 0

N: x1 x2 x3 x4

& x1 x2 x3 x4

& x1 x2 x3 x4

�̅� 0 1 0 D 0 1 0 D 0 1 1

O: Due to collision, no test pattern can be found

P: None of these.



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(12 Points)

Consider the logical circuit for realizing function Z(x1, x2, x3, x4), shown in figure 6-1.

Figure 9-1

Table 9-2 shows possible solutions for a D-algorithm Analysis of a single stuck at fault at the primary input x3.

Nbr. Pattern:

Nbr. Pattern:

a) x1 x2 x3 x4

0 0 𝐷 0

f) x1 x2 x3 x4

1 0 𝐷 0

b) x1 x2 x3 x4

1 1 𝐷 0

g) x1 x2 x3 x4

1 1 𝐷 0

c) x1 x2 x3 x4

0 0 𝐷 0

h) x1 x2 x3 x4

0 0 𝐷 1

d) x1 x2 x3 x4

1 1 𝐷 1

i) x1 x2 x3 x4

1 0 𝐷 0

e) x1 x2 x3 x4

1 1 𝐷 1

k) x1 x2 x3 x4

0 0 𝐷 1

Table 9-2 – Possible test pattern solutions



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9.1 Which of the following statements is true, regarding a D-algorithm analysis of the circuit shown in figure 6-1 and the solutions shown in table 6-2:

A: Only Test Pattern b) is correct B: Only Test Pattern f) is correct

C: Only Test Pattern e) is correct D: Only Test Pattern k) is correct

E: Only Test patterns a) and c) are correct F: Only Test patterns b) and g) are correct

G: Only Test patterns f) and i) are correct H: Only Test patterns h) and k) are correct

I: Only Test patterns a), c) & h) are correct J: Only Test patterns b), d) & g) are correct

K: Only Test patterns f), g) & i) are correct L: Only Test patterns c), h) & k) are correct

M: Due to collision, no test pattern is possible. N: None of these.

multiple-choice questions (mcq) examination … · 2018-02-21 · demo-examination test and...

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